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   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * (C) Copyright 2007
   7  * Texas Instruments Inc.
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * (C) Copyright 2004
  11  * Texas Instruments, <www.ti.com>
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #include <linux/linkage.h>
  30 #include <asm/assembler.h>
  31 #include <mach/hardware.h>
  32
  33 #include <mach/io.h>
  34
  35 #include "sdrc.h"
  36 #include "cm.h"
  37
  38         .text
  39
  40 /*
  41  * Change frequency of core dpll
  42  * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
  43  * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
  44  *      SDRC rates < 83MHz
  45  */
  46 ENTRY(omap3_sram_configure_core_dpll)
  47         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
  48         ldr     r4, [sp, #52]           @ pull extra args off the stack
  49         dsb                             @ flush buffered writes to interconnect
  50         cmp     r3, #0x2
  51         blne    configure_sdrc
  52         cmp     r4, #0x1
  53         bleq    unlock_dll
  54         blne    lock_dll
  55         bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
  56         bl      configure_core_dpll
  57         bl      enable_sdrc
  58         cmp     r4, #0x1
  59         bleq    wait_dll_unlock
  60         blne    wait_dll_lock
  61         cmp     r3, #0x1
  62         blne    configure_sdrc
  63         isb                             @ prevent speculative exec past here
  64         mov     r0, #0                  @ return value
  65         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
  66 unlock_dll:
  67         ldr     r11, omap3_sdrc_dlla_ctrl
  68         ldr     r12, [r11]
  69         orr     r12, r12, #0x4
  70         str     r12, [r11]              @ (no OCP barrier needed)
  71         bx      lr
  72 lock_dll:
  73         ldr     r11, omap3_sdrc_dlla_ctrl
  74         ldr     r12, [r11]
  75         bic     r12, r12, #0x4
  76         str     r12, [r11]              @ (no OCP barrier needed)
  77         bx      lr
  78 sdram_in_selfrefresh:
  79         ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
  80         ldr     r12, [r11]              @ read the contents of SDRC_POWER
  81         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
  82         orr     r12, r12, #0x40         @ enable self refresh on idle req
  83         bic     r12, r12, #0x4          @ clear PWDENA
  84         str     r12, [r11]              @ write back to SDRC_POWER register
  85         ldr     r12, [r11]              @ posted-write barrier for SDRC
  86         ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
  87         ldr     r12, [r11]
  88         bic     r12, r12, #0x2          @ disable iclk bit for SDRC
  89         str     r12, [r11]
  90 wait_sdrc_idle:
  91         ldr     r11, omap3_cm_idlest1_core
  92         ldr     r12, [r11]
  93         and     r12, r12, #0x2          @ check for SDRC idle
  94         cmp     r12, #2
  95         bne     wait_sdrc_idle
  96         bx      lr
  97 configure_core_dpll:
  98         ldr     r11, omap3_cm_clksel1_pll
  99         ldr     r12, [r11]
 100         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
 101         and     r12, r12, r10
 102         orr     r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
 103         str     r12, [r11]
 104         ldr     r12, [r11]              @ posted-write barrier for CM
 105         mov     r12, #0x800             @ wait for the clock to stabilise
 106         cmp     r3, #2
 107         bne     wait_clk_stable
 108         bx      lr
 109 wait_clk_stable:
 110         subs    r12, r12, #1
 111         bne     wait_clk_stable
 112         nop
 113         nop
 114         nop
 115         nop
 116         nop
 117         nop
 118         nop
 119         nop
 120         nop
 121         nop
 122         bx      lr
 123 enable_sdrc:
 124         ldr     r11, omap3_cm_iclken1_core
 125         ldr     r12, [r11]
 126         orr     r12, r12, #0x2          @ enable iclk bit for SDRC
 127         str     r12, [r11]
 128 wait_sdrc_idle1:
 129         ldr     r11, omap3_cm_idlest1_core
 130         ldr     r12, [r11]
 131         and     r12, r12, #0x2
 132         cmp     r12, #0
 133         bne     wait_sdrc_idle1
 134 restore_sdrc_power_val:
 135         ldr     r11, omap3_sdrc_power
 136         str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
 137         bx      lr
 138 wait_dll_lock:
 139         ldr     r11, omap3_sdrc_dlla_status
 140         ldr     r12, [r11]
 141         and     r12, r12, #0x4
 142         cmp     r12, #0x4
 143         bne     wait_dll_lock
 144         bx      lr
 145 wait_dll_unlock:
 146         ldr     r11, omap3_sdrc_dlla_status
 147         ldr     r12, [r11]
 148         and     r12, r12, #0x4
 149         cmp     r12, #0x0
 150         bne     wait_dll_unlock
 151         bx      lr
 152 configure_sdrc:
 153         ldr     r11, omap3_sdrc_rfr_ctrl
 154         str     r0, [r11]
 155         ldr     r11, omap3_sdrc_actim_ctrla
 156         str     r1, [r11]
 157         ldr     r11, omap3_sdrc_actim_ctrlb
 158         str     r2, [r11]
 159         ldr     r2, [r11]               @ posted-write barrier for SDRC
 160         bx      lr
 161
 162 omap3_sdrc_power:
 163         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 164 omap3_cm_clksel1_pll:
 165         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 166 omap3_cm_idlest1_core:
 167         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 168 omap3_cm_iclken1_core:
 169         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 170 omap3_sdrc_rfr_ctrl:
 171         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 172 omap3_sdrc_actim_ctrla:
 173         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 174 omap3_sdrc_actim_ctrlb:
 175         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 176 omap3_sdrc_dlla_status:
 177         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 178 omap3_sdrc_dlla_ctrl:
 179         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 180 core_m2_mask_val:
 181         .word 0x07FFFFFF
 182
 183 ENTRY(omap3_sram_configure_core_dpll_sz)
 184         .word   . - omap3_sram_configure_core_dpll