git.oblomov.eu Git - linux-2.6/blob - drivers/spi/spi_bfin5xx.c

   1 /*
   2  * File:         drivers/spi/bfin5xx_spi.c
   3  * Based on:     N/A
   4  * Author:       Luke Yang (Analog Devices Inc.)
   5  *
   6  * Created:      March. 10th 2006
   7  * Description:  SPI controller driver for Blackfin 5xx
   8  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   9  *
  10  * Modified:
  11  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
  12  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
  13  *
  14  * Copyright 2004-2006 Analog Devices Inc.
  15  *
  16  * This program is free software ;  you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation ;  either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program ;  see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/device.h>
  35 #include <linux/ioport.h>
  36 #include <linux/errno.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/spi/spi.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/errno.h>
  43 #include <linux/delay.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/delay.h>
  48 #include <asm/dma.h>
  49
  50 #include <asm/bfin5xx_spi.h>
  51
  52 MODULE_AUTHOR("Luke Yang");
  53 MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");
  54 MODULE_LICENSE("GPL");
  55
  56 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  57
  58 #define DEFINE_SPI_REG(reg, off) \
  59 static inline u16 read_##reg(void) \
  60             { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
  61 static inline void write_##reg(u16 v) \
  62             {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
  63              SSYNC();}
  64
  65 DEFINE_SPI_REG(CTRL, 0x00)
  66 DEFINE_SPI_REG(FLAG, 0x04)
  67 DEFINE_SPI_REG(STAT, 0x08)
  68 DEFINE_SPI_REG(TDBR, 0x0C)
  69 DEFINE_SPI_REG(RDBR, 0x10)
  70 DEFINE_SPI_REG(BAUD, 0x14)
  71 DEFINE_SPI_REG(SHAW, 0x18)
  72 #define START_STATE ((void*)0)
  73 #define RUNNING_STATE ((void*)1)
  74 #define DONE_STATE ((void*)2)
  75 #define ERROR_STATE ((void*)-1)
  76 #define QUEUE_RUNNING 0
  77 #define QUEUE_STOPPED 1
  78 int dma_requested;
  79
  80 struct driver_data {
  81         /* Driver model hookup */
  82         struct platform_device *pdev;
  83
  84         /* SPI framework hookup */
  85         struct spi_master *master;
  86
  87         /* BFIN hookup */
  88         struct bfin5xx_spi_master *master_info;
  89
  90         /* Driver message queue */
  91         struct workqueue_struct *workqueue;
  92         struct work_struct pump_messages;
  93         spinlock_t lock;
  94         struct list_head queue;
  95         int busy;
  96         int run;
  97
  98         /* Message Transfer pump */
  99         struct tasklet_struct pump_transfers;
 100
 101         /* Current message transfer state info */
 102         struct spi_message *cur_msg;
 103         struct spi_transfer *cur_transfer;
 104         struct chip_data *cur_chip;
 105         size_t len_in_bytes;
 106         size_t len;
 107         void *tx;
 108         void *tx_end;
 109         void *rx;
 110         void *rx_end;
 111         int dma_mapped;
 112         dma_addr_t rx_dma;
 113         dma_addr_t tx_dma;
 114         size_t rx_map_len;
 115         size_t tx_map_len;
 116         u8 n_bytes;
 117         void (*write) (struct driver_data *);
 118         void (*read) (struct driver_data *);
 119         void (*duplex) (struct driver_data *);
 120 };
 121
 122 struct chip_data {
 123         u16 ctl_reg;
 124         u16 baud;
 125         u16 flag;
 126
 127         u8 chip_select_num;
 128         u8 n_bytes;
 129         u8 width;               /* 0 or 1 */
 130         u8 enable_dma;
 131         u8 bits_per_word;       /* 8 or 16 */
 132         u8 cs_change_per_word;
 133         u8 cs_chg_udelay;
 134         void (*write) (struct driver_data *);
 135         void (*read) (struct driver_data *);
 136         void (*duplex) (struct driver_data *);
 137 };
 138
 139 static void bfin_spi_enable(struct driver_data *drv_data)
 140 {
 141         u16 cr;
 142
 143         cr = read_CTRL();
 144         write_CTRL(cr | BIT_CTL_ENABLE);
 145         SSYNC();
 146 }
 147
 148 static void bfin_spi_disable(struct driver_data *drv_data)
 149 {
 150         u16 cr;
 151
 152         cr = read_CTRL();
 153         write_CTRL(cr & (~BIT_CTL_ENABLE));
 154         SSYNC();
 155 }
 156
 157 /* Caculate the SPI_BAUD register value based on input HZ */
 158 static u16 hz_to_spi_baud(u32 speed_hz)
 159 {
 160         u_long sclk = get_sclk();
 161         u16 spi_baud = (sclk / (2 * speed_hz));
 162
 163         if ((sclk % (2 * speed_hz)) > 0)
 164                 spi_baud++;
 165
 166         return spi_baud;
 167 }
 168
 169 static int flush(struct driver_data *drv_data)
 170 {
 171         unsigned long limit = loops_per_jiffy << 1;
 172
 173         /* wait for stop and clear stat */
 174         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
 175                 continue;
 176
 177         write_STAT(BIT_STAT_CLR);
 178
 179         return limit;
 180 }
 181
 182 /* stop controller and re-config current chip*/
 183 static void restore_state(struct driver_data *drv_data)
 184 {
 185         struct chip_data *chip = drv_data->cur_chip;
 186
 187         /* Clear status and disable clock */
 188         write_STAT(BIT_STAT_CLR);
 189         bfin_spi_disable(drv_data);
 190         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 191
 192 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
 193         dev_dbg(&drv_data->pdev->dev,
 194                 "chip select number is %d\n", chip->chip_select_num);
 195
 196         switch (chip->chip_select_num) {
 197         case 1:
 198                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
 199                 SSYNC();
 200                 break;
 201
 202         case 2:
 203         case 3:
 204                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
 205                 SSYNC();
 206                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
 207                 SSYNC();
 208                 break;
 209
 210         case 4:
 211                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
 212                 SSYNC();
 213                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
 214                 SSYNC();
 215                 break;
 216
 217         case 5:
 218                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
 219                 SSYNC();
 220                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
 221                 SSYNC();
 222                 break;
 223
 224         case 6:
 225                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
 226                 SSYNC();
 227                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
 228                 SSYNC();
 229                 break;
 230
 231         case 7:
 232                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
 233                 SSYNC();
 234                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
 235                 SSYNC();
 236                 break;
 237         }
 238 #endif
 239
 240         /* Load the registers */
 241         write_CTRL(chip->ctl_reg);
 242         write_BAUD(chip->baud);
 243         write_FLAG(chip->flag);
 244 }
 245
 246 /* used to kick off transfer in rx mode */
 247 static unsigned short dummy_read(void)
 248 {
 249         unsigned short tmp;
 250         tmp = read_RDBR();
 251         return tmp;
 252 }
 253
 254 static void null_writer(struct driver_data *drv_data)
 255 {
 256         u8 n_bytes = drv_data->n_bytes;
 257
 258         while (drv_data->tx < drv_data->tx_end) {
 259                 write_TDBR(0);
 260                 while ((read_STAT() & BIT_STAT_TXS))
 261                         continue;
 262                 drv_data->tx += n_bytes;
 263         }
 264 }
 265
 266 static void null_reader(struct driver_data *drv_data)
 267 {
 268         u8 n_bytes = drv_data->n_bytes;
 269         dummy_read();
 270
 271         while (drv_data->rx < drv_data->rx_end) {
 272                 while (!(read_STAT() & BIT_STAT_RXS))
 273                         continue;
 274                 dummy_read();
 275                 drv_data->rx += n_bytes;
 276         }
 277 }
 278
 279 static void u8_writer(struct driver_data *drv_data)
 280 {
 281         dev_dbg(&drv_data->pdev->dev,
 282                 "cr8-s is 0x%x\n", read_STAT());
 283         while (drv_data->tx < drv_data->tx_end) {
 284                 write_TDBR(*(u8 *) (drv_data->tx));
 285                 while (read_STAT() & BIT_STAT_TXS)
 286                         continue;
 287                 ++drv_data->tx;
 288         }
 289
 290         /* poll for SPI completion before returning */
 291         while (!(read_STAT() & BIT_STAT_SPIF))
 292                 continue;
 293 }
 294
 295 static void u8_cs_chg_writer(struct driver_data *drv_data)
 296 {
 297         struct chip_data *chip = drv_data->cur_chip;
 298
 299         while (drv_data->tx < drv_data->tx_end) {
 300                 write_FLAG(chip->flag);
 301                 SSYNC();
 302
 303                 write_TDBR(*(u8 *) (drv_data->tx));
 304                 while (read_STAT() & BIT_STAT_TXS)
 305                         continue;
 306                 while (!(read_STAT() & BIT_STAT_SPIF))
 307                         continue;
 308                 write_FLAG(0xFF00 | chip->flag);
 309                 SSYNC();
 310                 if (chip->cs_chg_udelay)
 311                         udelay(chip->cs_chg_udelay);
 312                 ++drv_data->tx;
 313         }
 314         write_FLAG(0xFF00);
 315         SSYNC();
 316 }
 317
 318 static void u8_reader(struct driver_data *drv_data)
 319 {
 320         dev_dbg(&drv_data->pdev->dev,
 321                 "cr-8 is 0x%x\n", read_STAT());
 322
 323         /* clear TDBR buffer before read(else it will be shifted out) */
 324         write_TDBR(0xFFFF);
 325
 326         dummy_read();
 327
 328         while (drv_data->rx < drv_data->rx_end - 1) {
 329                 while (!(read_STAT() & BIT_STAT_RXS))
 330                         continue;
 331                 *(u8 *) (drv_data->rx) = read_RDBR();
 332                 ++drv_data->rx;
 333         }
 334
 335         while (!(read_STAT() & BIT_STAT_RXS))
 336                 continue;
 337         *(u8 *) (drv_data->rx) = read_SHAW();
 338         ++drv_data->rx;
 339 }
 340
 341 static void u8_cs_chg_reader(struct driver_data *drv_data)
 342 {
 343         struct chip_data *chip = drv_data->cur_chip;
 344
 345         while (drv_data->rx < drv_data->rx_end) {
 346                 write_FLAG(chip->flag);
 347                 SSYNC();
 348
 349                 read_RDBR();    /* kick off */
 350                 while (!(read_STAT() & BIT_STAT_RXS))
 351                         continue;
 352                 while (!(read_STAT() & BIT_STAT_SPIF))
 353                         continue;
 354                 *(u8 *) (drv_data->rx) = read_SHAW();
 355                 write_FLAG(0xFF00 | chip->flag);
 356                 SSYNC();
 357                 if (chip->cs_chg_udelay)
 358                         udelay(chip->cs_chg_udelay);
 359                 ++drv_data->rx;
 360         }
 361         write_FLAG(0xFF00);
 362         SSYNC();
 363 }
 364
 365 static void u8_duplex(struct driver_data *drv_data)
 366 {
 367         /* in duplex mode, clk is triggered by writing of TDBR */
 368         while (drv_data->rx < drv_data->rx_end) {
 369                 write_TDBR(*(u8 *) (drv_data->tx));
 370                 while (!(read_STAT() & BIT_STAT_SPIF))
 371                         continue;
 372                 while (!(read_STAT() & BIT_STAT_RXS))
 373                         continue;
 374                 *(u8 *) (drv_data->rx) = read_RDBR();
 375                 ++drv_data->rx;
 376                 ++drv_data->tx;
 377         }
 378 }
 379
 380 static void u8_cs_chg_duplex(struct driver_data *drv_data)
 381 {
 382         struct chip_data *chip = drv_data->cur_chip;
 383
 384         while (drv_data->rx < drv_data->rx_end) {
 385                 write_FLAG(chip->flag);
 386                 SSYNC();
 387
 388                 write_TDBR(*(u8 *) (drv_data->tx));
 389                 while (!(read_STAT() & BIT_STAT_SPIF))
 390                         continue;
 391                 while (!(read_STAT() & BIT_STAT_RXS))
 392                         continue;
 393                 *(u8 *) (drv_data->rx) = read_RDBR();
 394                 write_FLAG(0xFF00 | chip->flag);
 395                 SSYNC();
 396                 if (chip->cs_chg_udelay)
 397                         udelay(chip->cs_chg_udelay);
 398                 ++drv_data->rx;
 399                 ++drv_data->tx;
 400         }
 401         write_FLAG(0xFF00);
 402         SSYNC();
 403 }
 404
 405 static void u16_writer(struct driver_data *drv_data)
 406 {
 407         dev_dbg(&drv_data->pdev->dev,
 408                 "cr16 is 0x%x\n", read_STAT());
 409
 410         while (drv_data->tx < drv_data->tx_end) {
 411                 write_TDBR(*(u16 *) (drv_data->tx));
 412                 while ((read_STAT() & BIT_STAT_TXS))
 413                         continue;
 414                 drv_data->tx += 2;
 415         }
 416
 417         /* poll for SPI completion before returning */
 418         while (!(read_STAT() & BIT_STAT_SPIF))
 419                 continue;
 420 }
 421
 422 static void u16_cs_chg_writer(struct driver_data *drv_data)
 423 {
 424         struct chip_data *chip = drv_data->cur_chip;
 425
 426         while (drv_data->tx < drv_data->tx_end) {
 427                 write_FLAG(chip->flag);
 428                 SSYNC();
 429
 430                 write_TDBR(*(u16 *) (drv_data->tx));
 431                 while ((read_STAT() & BIT_STAT_TXS))
 432                         continue;
 433                 while (!(read_STAT() & BIT_STAT_SPIF))
 434                         continue;
 435                 write_FLAG(0xFF00 | chip->flag);
 436                 SSYNC();
 437                 if (chip->cs_chg_udelay)
 438                         udelay(chip->cs_chg_udelay);
 439                 drv_data->tx += 2;
 440         }
 441         write_FLAG(0xFF00);
 442         SSYNC();
 443 }
 444
 445 static void u16_reader(struct driver_data *drv_data)
 446 {
 447         dev_dbg(&drv_data->pdev->dev,
 448                 "cr-16 is 0x%x\n", read_STAT());
 449         dummy_read();
 450
 451         while (drv_data->rx < (drv_data->rx_end - 2)) {
 452                 while (!(read_STAT() & BIT_STAT_RXS))
 453                         continue;
 454                 *(u16 *) (drv_data->rx) = read_RDBR();
 455                 drv_data->rx += 2;
 456         }
 457
 458         while (!(read_STAT() & BIT_STAT_RXS))
 459                 continue;
 460         *(u16 *) (drv_data->rx) = read_SHAW();
 461         drv_data->rx += 2;
 462 }
 463
 464 static void u16_cs_chg_reader(struct driver_data *drv_data)
 465 {
 466         struct chip_data *chip = drv_data->cur_chip;
 467
 468         while (drv_data->rx < drv_data->rx_end) {
 469                 write_FLAG(chip->flag);
 470                 SSYNC();
 471
 472                 read_RDBR();    /* kick off */
 473                 while (!(read_STAT() & BIT_STAT_RXS))
 474                         continue;
 475                 while (!(read_STAT() & BIT_STAT_SPIF))
 476                         continue;
 477                 *(u16 *) (drv_data->rx) = read_SHAW();
 478                 write_FLAG(0xFF00 | chip->flag);
 479                 SSYNC();
 480                 if (chip->cs_chg_udelay)
 481                         udelay(chip->cs_chg_udelay);
 482                 drv_data->rx += 2;
 483         }
 484         write_FLAG(0xFF00);
 485         SSYNC();
 486 }
 487
 488 static void u16_duplex(struct driver_data *drv_data)
 489 {
 490         /* in duplex mode, clk is triggered by writing of TDBR */
 491         while (drv_data->tx < drv_data->tx_end) {
 492                 write_TDBR(*(u16 *) (drv_data->tx));
 493                 while (!(read_STAT() & BIT_STAT_SPIF))
 494                         continue;
 495                 while (!(read_STAT() & BIT_STAT_RXS))
 496                         continue;
 497                 *(u16 *) (drv_data->rx) = read_RDBR();
 498                 drv_data->rx += 2;
 499                 drv_data->tx += 2;
 500         }
 501 }
 502
 503 static void u16_cs_chg_duplex(struct driver_data *drv_data)
 504 {
 505         struct chip_data *chip = drv_data->cur_chip;
 506
 507         while (drv_data->tx < drv_data->tx_end) {
 508                 write_FLAG(chip->flag);
 509                 SSYNC();
 510
 511                 write_TDBR(*(u16 *) (drv_data->tx));
 512                 while (!(read_STAT() & BIT_STAT_SPIF))
 513                         continue;
 514                 while (!(read_STAT() & BIT_STAT_RXS))
 515                         continue;
 516                 *(u16 *) (drv_data->rx) = read_RDBR();
 517                 write_FLAG(0xFF00 | chip->flag);
 518                 SSYNC();
 519                 if (chip->cs_chg_udelay)
 520                         udelay(chip->cs_chg_udelay);
 521                 drv_data->rx += 2;
 522                 drv_data->tx += 2;
 523         }
 524         write_FLAG(0xFF00);
 525         SSYNC();
 526 }
 527
 528 /* test if ther is more transfer to be done */
 529 static void *next_transfer(struct driver_data *drv_data)
 530 {
 531         struct spi_message *msg = drv_data->cur_msg;
 532         struct spi_transfer *trans = drv_data->cur_transfer;
 533
 534         /* Move to next transfer */
 535         if (trans->transfer_list.next != &msg->transfers) {
 536                 drv_data->cur_transfer =
 537                     list_entry(trans->transfer_list.next,
 538                                struct spi_transfer, transfer_list);
 539                 return RUNNING_STATE;
 540         } else
 541                 return DONE_STATE;
 542 }
 543
 544 /*
 545  * caller already set message->status;
 546  * dma and pio irqs are blocked give finished message back
 547  */
 548 static void giveback(struct driver_data *drv_data)
 549 {
 550         struct spi_transfer *last_transfer;
 551         unsigned long flags;
 552         struct spi_message *msg;
 553
 554         spin_lock_irqsave(&drv_data->lock, flags);
 555         msg = drv_data->cur_msg;
 556         drv_data->cur_msg = NULL;
 557         drv_data->cur_transfer = NULL;
 558         drv_data->cur_chip = NULL;
 559         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 560         spin_unlock_irqrestore(&drv_data->lock, flags);
 561
 562         last_transfer = list_entry(msg->transfers.prev,
 563                                    struct spi_transfer, transfer_list);
 564
 565         msg->state = NULL;
 566
 567         /* disable chip select signal. And not stop spi in autobuffer mode */
 568         if (drv_data->tx_dma != 0xFFFF) {
 569                 write_FLAG(0xFF00);
 570                 bfin_spi_disable(drv_data);
 571         }
 572
 573         if (msg->complete)
 574                 msg->complete(msg->context);
 575 }
 576
 577 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 578 {
 579         struct driver_data *drv_data = (struct driver_data *)dev_id;
 580         struct spi_message *msg = drv_data->cur_msg;
 581
 582         dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
 583         clear_dma_irqstat(CH_SPI);
 584
 585         /*
 586          * wait for the last transaction shifted out.  yes, these two
 587          * while loops are supposed to be the same (see the HRM).
 588          */
 589         if (drv_data->tx != NULL) {
 590                 while (bfin_read_SPI_STAT() & TXS)
 591                         continue;
 592                 while (bfin_read_SPI_STAT() & TXS)
 593                         continue;
 594         }
 595
 596         while (!(bfin_read_SPI_STAT() & SPIF))
 597                 continue;
 598
 599         bfin_spi_disable(drv_data);
 600
 601         msg->actual_length += drv_data->len_in_bytes;
 602
 603         /* Move to next transfer */
 604         msg->state = next_transfer(drv_data);
 605
 606         /* Schedule transfer tasklet */
 607         tasklet_schedule(&drv_data->pump_transfers);
 608
 609         /* free the irq handler before next transfer */
 610         dev_dbg(&drv_data->pdev->dev,
 611                 "disable dma channel irq%d\n",
 612                 CH_SPI);
 613         dma_disable_irq(CH_SPI);
 614
 615         return IRQ_HANDLED;
 616 }
 617
 618 static void pump_transfers(unsigned long data)
 619 {
 620         struct driver_data *drv_data = (struct driver_data *)data;
 621         struct spi_message *message = NULL;
 622         struct spi_transfer *transfer = NULL;
 623         struct spi_transfer *previous = NULL;
 624         struct chip_data *chip = NULL;
 625         u8 width;
 626         u16 cr, dma_width, dma_config;
 627         u32 tranf_success = 1;
 628
 629         /* Get current state information */
 630         message = drv_data->cur_msg;
 631         transfer = drv_data->cur_transfer;
 632         chip = drv_data->cur_chip;
 633
 634         /*
 635          * if msg is error or done, report it back using complete() callback
 636          */
 637
 638          /* Handle for abort */
 639         if (message->state == ERROR_STATE) {
 640                 message->status = -EIO;
 641                 giveback(drv_data);
 642                 return;
 643         }
 644
 645         /* Handle end of message */
 646         if (message->state == DONE_STATE) {
 647                 message->status = 0;
 648                 giveback(drv_data);
 649                 return;
 650         }
 651
 652         /* Delay if requested at end of transfer */
 653         if (message->state == RUNNING_STATE) {
 654                 previous = list_entry(transfer->transfer_list.prev,
 655                                       struct spi_transfer, transfer_list);
 656                 if (previous->delay_usecs)
 657                         udelay(previous->delay_usecs);
 658         }
 659
 660         /* Setup the transfer state based on the type of transfer */
 661         if (flush(drv_data) == 0) {
 662                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 663                 message->status = -EIO;
 664                 giveback(drv_data);
 665                 return;
 666         }
 667
 668         if (transfer->tx_buf != NULL) {
 669                 drv_data->tx = (void *)transfer->tx_buf;
 670                 drv_data->tx_end = drv_data->tx + transfer->len;
 671                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 672                         transfer->tx_buf, drv_data->tx_end);
 673         } else {
 674                 drv_data->tx = NULL;
 675         }
 676
 677         if (transfer->rx_buf != NULL) {
 678                 drv_data->rx = transfer->rx_buf;
 679                 drv_data->rx_end = drv_data->rx + transfer->len;
 680                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 681                         transfer->rx_buf, drv_data->rx_end);
 682         } else {
 683                 drv_data->rx = NULL;
 684         }
 685
 686         drv_data->rx_dma = transfer->rx_dma;
 687         drv_data->tx_dma = transfer->tx_dma;
 688         drv_data->len_in_bytes = transfer->len;
 689
 690         width = chip->width;
 691         if (width == CFG_SPI_WORDSIZE16) {
 692                 drv_data->len = (transfer->len) >> 1;
 693         } else {
 694                 drv_data->len = transfer->len;
 695         }
 696         drv_data->write = drv_data->tx ? chip->write : null_writer;
 697         drv_data->read = drv_data->rx ? chip->read : null_reader;
 698         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
 699         dev_dbg(&drv_data->pdev->dev,
 700                 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
 701                 drv_data->write, chip->write, null_writer);
 702
 703         /* speed and width has been set on per message */
 704         message->state = RUNNING_STATE;
 705         dma_config = 0;
 706
 707         /* restore spi status for each spi transfer */
 708         if (transfer->speed_hz) {
 709                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
 710         } else {
 711                 write_BAUD(chip->baud);
 712         }
 713         write_FLAG(chip->flag);
 714
 715         dev_dbg(&drv_data->pdev->dev,
 716                 "now pumping a transfer: width is %d, len is %d\n",
 717                 width, transfer->len);
 718
 719         /*
 720          * Try to map dma buffer and do a dma transfer if
 721          * successful use different way to r/w according to
 722          * drv_data->cur_chip->enable_dma
 723          */
 724         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
 725
 726                 write_STAT(BIT_STAT_CLR);
 727                 disable_dma(CH_SPI);
 728                 clear_dma_irqstat(CH_SPI);
 729                 bfin_spi_disable(drv_data);
 730
 731                 /* config dma channel */
 732                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 733                 if (width == CFG_SPI_WORDSIZE16) {
 734                         set_dma_x_count(CH_SPI, drv_data->len);
 735                         set_dma_x_modify(CH_SPI, 2);
 736                         dma_width = WDSIZE_16;
 737                 } else {
 738                         set_dma_x_count(CH_SPI, drv_data->len);
 739                         set_dma_x_modify(CH_SPI, 1);
 740                         dma_width = WDSIZE_8;
 741                 }
 742
 743                 /* set transfer width,direction. And enable spi */
 744                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 745
 746                 /* dirty hack for autobuffer DMA mode */
 747                 if (drv_data->tx_dma == 0xFFFF) {
 748                         dev_dbg(&drv_data->pdev->dev,
 749                                 "doing autobuffer DMA out.\n");
 750
 751                         /* no irq in autobuffer mode */
 752                         dma_config =
 753                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 754                         set_dma_config(CH_SPI, dma_config);
 755                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 756                         enable_dma(CH_SPI);
 757                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 758                                    (CFG_SPI_ENABLE << 14));
 759
 760                         /* just return here, there can only be one transfer in this mode */
 761                         message->status = 0;
 762                         giveback(drv_data);
 763                         return;
 764                 }
 765
 766                 /* In dma mode, rx or tx must be NULL in one transfer */
 767                 if (drv_data->rx != NULL) {
 768                         /* set transfer mode, and enable SPI */
 769                         dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
 770
 771                         /* disable SPI before write to TDBR */
 772                         write_CTRL(cr & ~BIT_CTL_ENABLE);
 773
 774                         /* clear tx reg soformer data is not shifted out */
 775                         write_TDBR(0xFF);
 776
 777                         set_dma_x_count(CH_SPI, drv_data->len);
 778
 779                         /* start dma */
 780                         dma_enable_irq(CH_SPI);
 781                         dma_config = (WNR | RESTART | dma_width | DI_EN);
 782                         set_dma_config(CH_SPI, dma_config);
 783                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx);
 784                         enable_dma(CH_SPI);
 785
 786                         cr |=
 787                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
 788                                                               14);
 789                         /* set transfer mode, and enable SPI */
 790                         write_CTRL(cr);
 791                 } else if (drv_data->tx != NULL) {
 792                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 793
 794                         /* start dma */
 795                         dma_enable_irq(CH_SPI);
 796                         dma_config = (RESTART | dma_width | DI_EN);
 797                         set_dma_config(CH_SPI, dma_config);
 798                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 799                         enable_dma(CH_SPI);
 800
 801                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 802                                    (CFG_SPI_ENABLE << 14));
 803
 804                 }
 805         } else {
 806                 /* IO mode write then read */
 807                 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 808
 809                 write_STAT(BIT_STAT_CLR);
 810
 811                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
 812                         /* full duplex mode */
 813                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
 814                                (drv_data->rx_end - drv_data->rx));
 815                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 816                         cr |= CFG_SPI_WRITE | (width << 8) |
 817                                 (CFG_SPI_ENABLE << 14);
 818                         dev_dbg(&drv_data->pdev->dev,
 819                                 "IO duplex: cr is 0x%x\n", cr);
 820
 821                         write_CTRL(cr);
 822                         SSYNC();
 823
 824                         drv_data->duplex(drv_data);
 825
 826                         if (drv_data->tx != drv_data->tx_end)
 827                                 tranf_success = 0;
 828                 } else if (drv_data->tx != NULL) {
 829                         /* write only half duplex */
 830                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 831                         cr |= CFG_SPI_WRITE | (width << 8) |
 832                                 (CFG_SPI_ENABLE << 14);
 833                         dev_dbg(&drv_data->pdev->dev,
 834                                 "IO write: cr is 0x%x\n", cr);
 835
 836                         write_CTRL(cr);
 837                         SSYNC();
 838
 839                         drv_data->write(drv_data);
 840
 841                         if (drv_data->tx != drv_data->tx_end)
 842                                 tranf_success = 0;
 843                 } else if (drv_data->rx != NULL) {
 844                         /* read only half duplex */
 845                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 846                         cr |= CFG_SPI_READ | (width << 8) |
 847                                 (CFG_SPI_ENABLE << 14);
 848                         dev_dbg(&drv_data->pdev->dev,
 849                                 "IO read: cr is 0x%x\n", cr);
 850
 851                         write_CTRL(cr);
 852                         SSYNC();
 853
 854                         drv_data->read(drv_data);
 855                         if (drv_data->rx != drv_data->rx_end)
 856                                 tranf_success = 0;
 857                 }
 858
 859                 if (!tranf_success) {
 860                         dev_dbg(&drv_data->pdev->dev,
 861                                 "IO write error!\n");
 862                         message->state = ERROR_STATE;
 863                 } else {
 864                         /* Update total byte transfered */
 865                         message->actual_length += drv_data->len;
 866
 867                         /* Move to next transfer of this msg */
 868                         message->state = next_transfer(drv_data);
 869                 }
 870
 871                 /* Schedule next transfer tasklet */
 872                 tasklet_schedule(&drv_data->pump_transfers);
 873
 874         }
 875 }
 876
 877 /* pop a msg from queue and kick off real transfer */
 878 static void pump_messages(struct work_struct *work)
 879 {
 880         struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages);
 881         unsigned long flags;
 882
 883         /* Lock queue and check for queue work */
 884         spin_lock_irqsave(&drv_data->lock, flags);
 885         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 886                 /* pumper kicked off but no work to do */
 887                 drv_data->busy = 0;
 888                 spin_unlock_irqrestore(&drv_data->lock, flags);
 889                 return;
 890         }
 891
 892         /* Make sure we are not already running a message */
 893         if (drv_data->cur_msg) {
 894                 spin_unlock_irqrestore(&drv_data->lock, flags);
 895                 return;
 896         }
 897
 898         /* Extract head of queue */
 899         drv_data->cur_msg = list_entry(drv_data->queue.next,
 900                                        struct spi_message, queue);
 901         list_del_init(&drv_data->cur_msg->queue);
 902
 903         /* Initial message state */
 904         drv_data->cur_msg->state = START_STATE;
 905         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 906                                             struct spi_transfer, transfer_list);
 907
 908         /* Setup the SSP using the per chip configuration */
 909         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 910         restore_state(drv_data);
 911         dev_dbg(&drv_data->pdev->dev,
 912                 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 913                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 914                 drv_data->cur_chip->ctl_reg);
 915
 916         dev_dbg(&drv_data->pdev->dev,
 917                 "the first transfer len is %d\n",
 918                 drv_data->cur_transfer->len);
 919
 920         /* Mark as busy and launch transfers */
 921         tasklet_schedule(&drv_data->pump_transfers);
 922
 923         drv_data->busy = 1;
 924         spin_unlock_irqrestore(&drv_data->lock, flags);
 925 }
 926
 927 /*
 928  * got a msg to transfer, queue it in drv_data->queue.
 929  * And kick off message pumper
 930  */
 931 static int transfer(struct spi_device *spi, struct spi_message *msg)
 932 {
 933         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 934         unsigned long flags;
 935
 936         spin_lock_irqsave(&drv_data->lock, flags);
 937
 938         if (drv_data->run == QUEUE_STOPPED) {
 939                 spin_unlock_irqrestore(&drv_data->lock, flags);
 940                 return -ESHUTDOWN;
 941         }
 942
 943         msg->actual_length = 0;
 944         msg->status = -EINPROGRESS;
 945         msg->state = START_STATE;
 946
 947         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 948         list_add_tail(&msg->queue, &drv_data->queue);
 949
 950         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 951                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 952
 953         spin_unlock_irqrestore(&drv_data->lock, flags);
 954
 955         return 0;
 956 }
 957
 958 /* first setup for new devices */
 959 static int setup(struct spi_device *spi)
 960 {
 961         struct bfin5xx_spi_chip *chip_info = NULL;
 962         struct chip_data *chip;
 963         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 964         u8 spi_flg;
 965
 966         /* Abort device setup if requested features are not supported */
 967         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
 968                 dev_err(&spi->dev, "requested mode not fully supported\n");
 969                 return -EINVAL;
 970         }
 971
 972         /* Zero (the default) here means 8 bits */
 973         if (!spi->bits_per_word)
 974                 spi->bits_per_word = 8;
 975
 976         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 977                 return -EINVAL;
 978
 979         /* Only alloc (or use chip_info) on first setup */
 980         chip = spi_get_ctldata(spi);
 981         if (chip == NULL) {
 982                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 983                 if (!chip)
 984                         return -ENOMEM;
 985
 986                 chip->enable_dma = 0;
 987                 chip_info = spi->controller_data;
 988         }
 989
 990         /* chip_info isn't always needed */
 991         if (chip_info) {
 992                 chip->enable_dma = chip_info->enable_dma != 0
 993                     && drv_data->master_info->enable_dma;
 994                 chip->ctl_reg = chip_info->ctl_reg;
 995                 chip->bits_per_word = chip_info->bits_per_word;
 996                 chip->cs_change_per_word = chip_info->cs_change_per_word;
 997                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
 998         }
 999
1000         /* translate common spi framework into our register */
1001         if (spi->mode & SPI_CPOL)
1002                 chip->ctl_reg |= CPOL;
1003         if (spi->mode & SPI_CPHA)
1004                 chip->ctl_reg |= CPHA;
1005         if (spi->mode & SPI_LSB_FIRST)
1006                 chip->ctl_reg |= LSBF;
1007         /* we dont support running in slave mode (yet?) */
1008         chip->ctl_reg |= MSTR;
1009
1010         /*
1011          * if any one SPI chip is registered and wants DMA, request the
1012          * DMA channel for it
1013          */
1014         if (chip->enable_dma && !dma_requested) {
1015                 /* register dma irq handler */
1016                 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1017                         dev_dbg(&spi->dev,
1018                                 "Unable to request BlackFin SPI DMA channel\n");
1019                         return -ENODEV;
1020                 }
1021                 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1022                     < 0) {
1023                         dev_dbg(&spi->dev, "Unable to set dma callback\n");
1024                         return -EPERM;
1025                 }
1026                 dma_disable_irq(CH_SPI);
1027                 dma_requested = 1;
1028         }
1029
1030         /*
1031          * Notice: for blackfin, the speed_hz is the value of register
1032          * SPI_BAUD, not the real baudrate
1033          */
1034         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1035         spi_flg = ~(1 << (spi->chip_select));
1036         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1037         chip->chip_select_num = spi->chip_select;
1038
1039         switch (chip->bits_per_word) {
1040         case 8:
1041                 chip->n_bytes = 1;
1042                 chip->width = CFG_SPI_WORDSIZE8;
1043                 chip->read = chip->cs_change_per_word ?
1044                         u8_cs_chg_reader : u8_reader;
1045                 chip->write = chip->cs_change_per_word ?
1046                         u8_cs_chg_writer : u8_writer;
1047                 chip->duplex = chip->cs_change_per_word ?
1048                         u8_cs_chg_duplex : u8_duplex;
1049                 break;
1050
1051         case 16:
1052                 chip->n_bytes = 2;
1053                 chip->width = CFG_SPI_WORDSIZE16;
1054                 chip->read = chip->cs_change_per_word ?
1055                         u16_cs_chg_reader : u16_reader;
1056                 chip->write = chip->cs_change_per_word ?
1057                         u16_cs_chg_writer : u16_writer;
1058                 chip->duplex = chip->cs_change_per_word ?
1059                         u16_cs_chg_duplex : u16_duplex;
1060                 break;
1061
1062         default:
1063                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1064                                 chip->bits_per_word);
1065                 kfree(chip);
1066                 return -ENODEV;
1067         }
1068
1069         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d,",
1070                         spi->modalias, chip->width, chip->enable_dma);
1071         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1072                         chip->ctl_reg, chip->flag);
1073
1074         spi_set_ctldata(spi, chip);
1075
1076         return 0;
1077 }
1078
1079 /*
1080  * callback for spi framework.
1081  * clean driver specific data
1082  */
1083 static void cleanup(struct spi_device *spi)
1084 {
1085         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1086
1087         kfree(chip);
1088 }
1089
1090 static inline int init_queue(struct driver_data *drv_data)
1091 {
1092         INIT_LIST_HEAD(&drv_data->queue);
1093         spin_lock_init(&drv_data->lock);
1094
1095         drv_data->run = QUEUE_STOPPED;
1096         drv_data->busy = 0;
1097
1098         /* init transfer tasklet */
1099         tasklet_init(&drv_data->pump_transfers,
1100                      pump_transfers, (unsigned long)drv_data);
1101
1102         /* init messages workqueue */
1103         INIT_WORK(&drv_data->pump_messages, pump_messages);
1104         drv_data->workqueue =
1105             create_singlethread_workqueue(drv_data->master->cdev.dev->bus_id);
1106         if (drv_data->workqueue == NULL)
1107                 return -EBUSY;
1108
1109         return 0;
1110 }
1111
1112 static inline int start_queue(struct driver_data *drv_data)
1113 {
1114         unsigned long flags;
1115
1116         spin_lock_irqsave(&drv_data->lock, flags);
1117
1118         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1119                 spin_unlock_irqrestore(&drv_data->lock, flags);
1120                 return -EBUSY;
1121         }
1122
1123         drv_data->run = QUEUE_RUNNING;
1124         drv_data->cur_msg = NULL;
1125         drv_data->cur_transfer = NULL;
1126         drv_data->cur_chip = NULL;
1127         spin_unlock_irqrestore(&drv_data->lock, flags);
1128
1129         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1130
1131         return 0;
1132 }
1133
1134 static inline int stop_queue(struct driver_data *drv_data)
1135 {
1136         unsigned long flags;
1137         unsigned limit = 500;
1138         int status = 0;
1139
1140         spin_lock_irqsave(&drv_data->lock, flags);
1141
1142         /*
1143          * This is a bit lame, but is optimized for the common execution path.
1144          * A wait_queue on the drv_data->busy could be used, but then the common
1145          * execution path (pump_messages) would be required to call wake_up or
1146          * friends on every SPI message. Do this instead
1147          */
1148         drv_data->run = QUEUE_STOPPED;
1149         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1150                 spin_unlock_irqrestore(&drv_data->lock, flags);
1151                 msleep(10);
1152                 spin_lock_irqsave(&drv_data->lock, flags);
1153         }
1154
1155         if (!list_empty(&drv_data->queue) || drv_data->busy)
1156                 status = -EBUSY;
1157
1158         spin_unlock_irqrestore(&drv_data->lock, flags);
1159
1160         return status;
1161 }
1162
1163 static inline int destroy_queue(struct driver_data *drv_data)
1164 {
1165         int status;
1166
1167         status = stop_queue(drv_data);
1168         if (status != 0)
1169                 return status;
1170
1171         destroy_workqueue(drv_data->workqueue);
1172
1173         return 0;
1174 }
1175
1176 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1177 {
1178         struct device *dev = &pdev->dev;
1179         struct bfin5xx_spi_master *platform_info;
1180         struct spi_master *master;
1181         struct driver_data *drv_data = 0;
1182         int status = 0;
1183
1184         platform_info = dev->platform_data;
1185
1186         /* Allocate master with space for drv_data */
1187         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1188         if (!master) {
1189                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1190                 return -ENOMEM;
1191         }
1192         drv_data = spi_master_get_devdata(master);
1193         drv_data->master = master;
1194         drv_data->master_info = platform_info;
1195         drv_data->pdev = pdev;
1196
1197         master->bus_num = pdev->id;
1198         master->num_chipselect = platform_info->num_chipselect;
1199         master->cleanup = cleanup;
1200         master->setup = setup;
1201         master->transfer = transfer;
1202
1203         /* Initial and start queue */
1204         status = init_queue(drv_data);
1205         if (status != 0) {
1206                 dev_err(&pdev->dev, "problem initializing queue\n");
1207                 goto out_error_queue_alloc;
1208         }
1209         status = start_queue(drv_data);
1210         if (status != 0) {
1211                 dev_err(&pdev->dev, "problem starting queue\n");
1212                 goto out_error_queue_alloc;
1213         }
1214
1215         /* Register with the SPI framework */
1216         platform_set_drvdata(pdev, drv_data);
1217         status = spi_register_master(master);
1218         if (status != 0) {
1219                 dev_err(&pdev->dev, "problem registering spi master\n");
1220                 goto out_error_queue_alloc;
1221         }
1222         dev_dbg(&pdev->dev, "controller probe successfully\n");
1223         return status;
1224
1225       out_error_queue_alloc:
1226         destroy_queue(drv_data);
1227         spi_master_put(master);
1228         return status;
1229 }
1230
1231 /* stop hardware and remove the driver */
1232 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1233 {
1234         struct driver_data *drv_data = platform_get_drvdata(pdev);
1235         int status = 0;
1236
1237         if (!drv_data)
1238                 return 0;
1239
1240         /* Remove the queue */
1241         status = destroy_queue(drv_data);
1242         if (status != 0)
1243                 return status;
1244
1245         /* Disable the SSP at the peripheral and SOC level */
1246         bfin_spi_disable(drv_data);
1247
1248         /* Release DMA */
1249         if (drv_data->master_info->enable_dma) {
1250                 if (dma_channel_active(CH_SPI))
1251                         free_dma(CH_SPI);
1252         }
1253
1254         /* Disconnect from the SPI framework */
1255         spi_unregister_master(drv_data->master);
1256
1257         /* Prevent double remove */
1258         platform_set_drvdata(pdev, NULL);
1259
1260         return 0;
1261 }
1262
1263 #ifdef CONFIG_PM
1264 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1265 {
1266         struct driver_data *drv_data = platform_get_drvdata(pdev);
1267         int status = 0;
1268
1269         status = stop_queue(drv_data);
1270         if (status != 0)
1271                 return status;
1272
1273         /* stop hardware */
1274         bfin_spi_disable(drv_data);
1275
1276         return 0;
1277 }
1278
1279 static int bfin5xx_spi_resume(struct platform_device *pdev)
1280 {
1281         struct driver_data *drv_data = platform_get_drvdata(pdev);
1282         int status = 0;
1283
1284         /* Enable the SPI interface */
1285         bfin_spi_enable(drv_data);
1286
1287         /* Start the queue running */
1288         status = start_queue(drv_data);
1289         if (status != 0) {
1290                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1291                 return status;
1292         }
1293
1294         return 0;
1295 }
1296 #else
1297 #define bfin5xx_spi_suspend NULL
1298 #define bfin5xx_spi_resume NULL
1299 #endif                          /* CONFIG_PM */
1300
1301 static struct platform_driver bfin5xx_spi_driver = {
1302         .driver         = {
1303                 .name   = "bfin-spi-master",
1304                 .owner  = THIS_MODULE,
1305         },
1306         .suspend        = bfin5xx_spi_suspend,
1307         .resume         = bfin5xx_spi_resume,
1308         .remove         = __devexit_p(bfin5xx_spi_remove),
1309 };
1310
1311 static int __init bfin5xx_spi_init(void)
1312 {
1313         return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1314 }
1315 module_init(bfin5xx_spi_init);
1316
1317 static void __exit bfin5xx_spi_exit(void)
1318 {
1319         platform_driver_unregister(&bfin5xx_spi_driver);
1320 }
1321 module_exit(bfin5xx_spi_exit);