Merge branch 'x86-stage-3-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2  * MPC8548 CDS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8548CDS";
16         compatible = "MPC8548CDS", "MPC85xxCDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23 /*
24                 ethernet2 = &enet2;
25                 ethernet3 = &enet3;
26 */
27                 serial0 = &serial0;
28                 serial1 = &serial1;
29                 pci0 = &pci0;
30                 pci1 = &pci1;
31                 pci2 = &pci2;
32         };
33
34         cpus {
35                 #address-cells = <1>;
36                 #size-cells = <0>;
37
38                 PowerPC,8548@0 {
39                         device_type = "cpu";
40                         reg = <0x0>;
41                         d-cache-line-size = <32>;       // 32 bytes
42                         i-cache-line-size = <32>;       // 32 bytes
43                         d-cache-size = <0x8000>;                // L1, 32K
44                         i-cache-size = <0x8000>;                // L1, 32K
45                         timebase-frequency = <0>;       //  33 MHz, from uboot
46                         bus-frequency = <0>;    // 166 MHz
47                         clock-frequency = <0>;  // 825 MHz, from uboot
48                         next-level-cache = <&L2>;
49                 };
50         };
51
52         memory {
53                 device_type = "memory";
54                 reg = <0x0 0x8000000>;  // 128M at 0x0
55         };
56
57         soc8548@e0000000 {
58                 #address-cells = <1>;
59                 #size-cells = <1>;
60                 device_type = "soc";
61                 compatible = "simple-bus";
62                 ranges = <0x0 0xe0000000 0x100000>;
63                 reg = <0xe0000000 0x1000>;      // CCSRBAR
64                 bus-frequency = <0>;
65
66                 memory-controller@2000 {
67                         compatible = "fsl,8548-memory-controller";
68                         reg = <0x2000 0x1000>;
69                         interrupt-parent = <&mpic>;
70                         interrupts = <18 2>;
71                 };
72
73                 L2: l2-cache-controller@20000 {
74                         compatible = "fsl,8548-l2-cache-controller";
75                         reg = <0x20000 0x1000>;
76                         cache-line-size = <32>; // 32 bytes
77                         cache-size = <0x80000>; // L2, 512K
78                         interrupt-parent = <&mpic>;
79                         interrupts = <16 2>;
80                 };
81
82                 i2c@3000 {
83                         #address-cells = <1>;
84                         #size-cells = <0>;
85                         cell-index = <0>;
86                         compatible = "fsl-i2c";
87                         reg = <0x3000 0x100>;
88                         interrupts = <43 2>;
89                         interrupt-parent = <&mpic>;
90                         dfsrr;
91                 };
92
93                 i2c@3100 {
94                         #address-cells = <1>;
95                         #size-cells = <0>;
96                         cell-index = <1>;
97                         compatible = "fsl-i2c";
98                         reg = <0x3100 0x100>;
99                         interrupts = <43 2>;
100                         interrupt-parent = <&mpic>;
101                         dfsrr;
102                 };
103
104                 dma@21300 {
105                         #address-cells = <1>;
106                         #size-cells = <1>;
107                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
108                         reg = <0x21300 0x4>;
109                         ranges = <0x0 0x21100 0x200>;
110                         cell-index = <0>;
111                         dma-channel@0 {
112                                 compatible = "fsl,mpc8548-dma-channel",
113                                                 "fsl,eloplus-dma-channel";
114                                 reg = <0x0 0x80>;
115                                 cell-index = <0>;
116                                 interrupt-parent = <&mpic>;
117                                 interrupts = <20 2>;
118                         };
119                         dma-channel@80 {
120                                 compatible = "fsl,mpc8548-dma-channel",
121                                                 "fsl,eloplus-dma-channel";
122                                 reg = <0x80 0x80>;
123                                 cell-index = <1>;
124                                 interrupt-parent = <&mpic>;
125                                 interrupts = <21 2>;
126                         };
127                         dma-channel@100 {
128                                 compatible = "fsl,mpc8548-dma-channel",
129                                                 "fsl,eloplus-dma-channel";
130                                 reg = <0x100 0x80>;
131                                 cell-index = <2>;
132                                 interrupt-parent = <&mpic>;
133                                 interrupts = <22 2>;
134                         };
135                         dma-channel@180 {
136                                 compatible = "fsl,mpc8548-dma-channel",
137                                                 "fsl,eloplus-dma-channel";
138                                 reg = <0x180 0x80>;
139                                 cell-index = <3>;
140                                 interrupt-parent = <&mpic>;
141                                 interrupts = <23 2>;
142                         };
143                 };
144
145                 enet0: ethernet@24000 {
146                         #address-cells = <1>;
147                         #size-cells = <1>;
148                         cell-index = <0>;
149                         device_type = "network";
150                         model = "eTSEC";
151                         compatible = "gianfar";
152                         reg = <0x24000 0x1000>;
153                         ranges = <0x0 0x24000 0x1000>;
154                         local-mac-address = [ 00 00 00 00 00 00 ];
155                         interrupts = <29 2 30 2 34 2>;
156                         interrupt-parent = <&mpic>;
157                         tbi-handle = <&tbi0>;
158                         phy-handle = <&phy0>;
159
160                         mdio@520 {
161                                 #address-cells = <1>;
162                                 #size-cells = <0>;
163                                 compatible = "fsl,gianfar-mdio";
164                                 reg = <0x520 0x20>;
165
166                                 phy0: ethernet-phy@0 {
167                                         interrupt-parent = <&mpic>;
168                                         interrupts = <5 1>;
169                                         reg = <0x0>;
170                                         device_type = "ethernet-phy";
171                                 };
172                                 phy1: ethernet-phy@1 {
173                                         interrupt-parent = <&mpic>;
174                                         interrupts = <5 1>;
175                                         reg = <0x1>;
176                                         device_type = "ethernet-phy";
177                                 };
178                                 phy2: ethernet-phy@2 {
179                                         interrupt-parent = <&mpic>;
180                                         interrupts = <5 1>;
181                                         reg = <0x2>;
182                                         device_type = "ethernet-phy";
183                                 };
184                                 phy3: ethernet-phy@3 {
185                                         interrupt-parent = <&mpic>;
186                                         interrupts = <5 1>;
187                                         reg = <0x3>;
188                                         device_type = "ethernet-phy";
189                                 };
190                                 tbi0: tbi-phy@11 {
191                                         reg = <0x11>;
192                                         device_type = "tbi-phy";
193                                 };
194                         };
195                 };
196
197                 enet1: ethernet@25000 {
198                         #address-cells = <1>;
199                         #size-cells = <1>;
200                         cell-index = <1>;
201                         device_type = "network";
202                         model = "eTSEC";
203                         compatible = "gianfar";
204                         reg = <0x25000 0x1000>;
205                         ranges = <0x0 0x25000 0x1000>;
206                         local-mac-address = [ 00 00 00 00 00 00 ];
207                         interrupts = <35 2 36 2 40 2>;
208                         interrupt-parent = <&mpic>;
209                         tbi-handle = <&tbi1>;
210                         phy-handle = <&phy1>;
211
212                         mdio@520 {
213                                 #address-cells = <1>;
214                                 #size-cells = <0>;
215                                 compatible = "fsl,gianfar-tbi";
216                                 reg = <0x520 0x20>;
217
218                                 tbi1: tbi-phy@11 {
219                                         reg = <0x11>;
220                                         device_type = "tbi-phy";
221                                 };
222                         };
223                 };
224
225 /* eTSEC 3/4 are currently broken
226                 enet2: ethernet@26000 {
227                         #address-cells = <1>;
228                         #size-cells = <1>;
229                         cell-index = <2>;
230                         device_type = "network";
231                         model = "eTSEC";
232                         compatible = "gianfar";
233                         reg = <0x26000 0x1000>;
234                         ranges = <0x0 0x26000 0x1000>;
235                         local-mac-address = [ 00 00 00 00 00 00 ];
236                         interrupts = <31 2 32 2 33 2>;
237                         interrupt-parent = <&mpic>;
238                         tbi-handle = <&tbi2>;
239                         phy-handle = <&phy2>;
240
241                         mdio@520 {
242                                 #address-cells = <1>;
243                                 #size-cells = <0>;
244                                 compatible = "fsl,gianfar-tbi";
245                                 reg = <0x520 0x20>;
246
247                                 tbi2: tbi-phy@11 {
248                                         reg = <0x11>;
249                                         device_type = "tbi-phy";
250                                 };
251                         };
252                 };
253
254                 enet3: ethernet@27000 {
255                         #address-cells = <1>;
256                         #size-cells = <1>;
257                         cell-index = <3>;
258                         device_type = "network";
259                         model = "eTSEC";
260                         compatible = "gianfar";
261                         reg = <0x27000 0x1000>;
262                         ranges = <0x0 0x27000 0x1000>;
263                         local-mac-address = [ 00 00 00 00 00 00 ];
264                         interrupts = <37 2 38 2 39 2>;
265                         interrupt-parent = <&mpic>;
266                         tbi-handle = <&tbi3>;
267                         phy-handle = <&phy3>;
268
269                         mdio@520 {
270                                 #address-cells = <1>;
271                                 #size-cells = <0>;
272                                 compatible = "fsl,gianfar-tbi";
273                                 reg = <0x520 0x20>;
274
275                                 tbi3: tbi-phy@11 {
276                                         reg = <0x11>;
277                                         device_type = "tbi-phy";
278                                 };
279                         };
280                 };
281  */
282
283                 serial0: serial@4500 {
284                         cell-index = <0>;
285                         device_type = "serial";
286                         compatible = "ns16550";
287                         reg = <0x4500 0x100>;   // reg base, size
288                         clock-frequency = <0>;  // should we fill in in uboot?
289                         interrupts = <42 2>;
290                         interrupt-parent = <&mpic>;
291                 };
292
293                 serial1: serial@4600 {
294                         cell-index = <1>;
295                         device_type = "serial";
296                         compatible = "ns16550";
297                         reg = <0x4600 0x100>;   // reg base, size
298                         clock-frequency = <0>;  // should we fill in in uboot?
299                         interrupts = <42 2>;
300                         interrupt-parent = <&mpic>;
301                 };
302
303                 global-utilities@e0000 {        //global utilities reg
304                         compatible = "fsl,mpc8548-guts";
305                         reg = <0xe0000 0x1000>;
306                         fsl,has-rstcr;
307                 };
308
309                 crypto@30000 {
310                         compatible = "fsl,sec2.1", "fsl,sec2.0";
311                         reg = <0x30000 0x10000>;
312                         interrupts = <45 2>;
313                         interrupt-parent = <&mpic>;
314                         fsl,num-channels = <4>;
315                         fsl,channel-fifo-len = <24>;
316                         fsl,exec-units-mask = <0xfe>;
317                         fsl,descriptor-types-mask = <0x12b0ebf>;
318                 };
319
320                 mpic: pic@40000 {
321                         interrupt-controller;
322                         #address-cells = <0>;
323                         #interrupt-cells = <2>;
324                         reg = <0x40000 0x40000>;
325                         compatible = "chrp,open-pic";
326                         device_type = "open-pic";
327                 };
328         };
329
330         pci0: pci@e0008000 {
331                 cell-index = <0>;
332                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
333                 interrupt-map = <
334                         /* IDSEL 0x4 (PCIX Slot 2) */
335                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
336                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
337                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
338                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
339
340                         /* IDSEL 0x5 (PCIX Slot 3) */
341                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
342                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
343                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
344                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
345
346                         /* IDSEL 0x6 (PCIX Slot 4) */
347                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
348                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
349                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
350                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
351
352                         /* IDSEL 0x8 (PCIX Slot 5) */
353                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
354                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
355                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
356                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
357
358                         /* IDSEL 0xC (Tsi310 bridge) */
359                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
360                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
361                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
362                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
363
364                         /* IDSEL 0x14 (Slot 2) */
365                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
366                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
367                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
368                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
369
370                         /* IDSEL 0x15 (Slot 3) */
371                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
372                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
373                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
374                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
375
376                         /* IDSEL 0x16 (Slot 4) */
377                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
378                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
379                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
380                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
381
382                         /* IDSEL 0x18 (Slot 5) */
383                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
384                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
385                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
386                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
387
388                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
389                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
390                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
391                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
392                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
393
394                 interrupt-parent = <&mpic>;
395                 interrupts = <24 2>;
396                 bus-range = <0 0>;
397                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
398                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
399                 clock-frequency = <66666666>;
400                 #interrupt-cells = <1>;
401                 #size-cells = <2>;
402                 #address-cells = <3>;
403                 reg = <0xe0008000 0x1000>;
404                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
405                 device_type = "pci";
406
407                 pci_bridge@1c {
408                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
409                         interrupt-map = <
410
411                                 /* IDSEL 0x00 (PrPMC Site) */
412                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
413                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
414                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
415                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
416
417                                 /* IDSEL 0x04 (VIA chip) */
418                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
419                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
420                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
421                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
422
423                                 /* IDSEL 0x05 (8139) */
424                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
425
426                                 /* IDSEL 0x06 (Slot 6) */
427                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
428                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
429                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
430                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
431
432                                 /* IDESL 0x07 (Slot 7) */
433                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
434                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
435                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
436                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
437
438                         reg = <0xe000 0x0 0x0 0x0 0x0>;
439                         #interrupt-cells = <1>;
440                         #size-cells = <2>;
441                         #address-cells = <3>;
442                         ranges = <0x2000000 0x0 0x80000000
443                                   0x2000000 0x0 0x80000000
444                                   0x0 0x20000000
445                                   0x1000000 0x0 0x0
446                                   0x1000000 0x0 0x0
447                                   0x0 0x80000>;
448                         clock-frequency = <33333333>;
449
450                         isa@4 {
451                                 device_type = "isa";
452                                 #interrupt-cells = <2>;
453                                 #size-cells = <1>;
454                                 #address-cells = <2>;
455                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
456                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
457                                 interrupt-parent = <&i8259>;
458
459                                 i8259: interrupt-controller@20 {
460                                         interrupt-controller;
461                                         device_type = "interrupt-controller";
462                                         reg = <0x1 0x20 0x2
463                                                0x1 0xa0 0x2
464                                                0x1 0x4d0 0x2>;
465                                         #address-cells = <0>;
466                                         #interrupt-cells = <2>;
467                                         compatible = "chrp,iic";
468                                         interrupts = <0 1>;
469                                         interrupt-parent = <&mpic>;
470                                 };
471
472                                 rtc@70 {
473                                         compatible = "pnpPNP,b00";
474                                         reg = <0x1 0x70 0x2>;
475                                 };
476                         };
477                 };
478         };
479
480         pci1: pci@e0009000 {
481                 cell-index = <1>;
482                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
483                 interrupt-map = <
484
485                         /* IDSEL 0x15 */
486                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
487                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
488                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
489                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
490
491                 interrupt-parent = <&mpic>;
492                 interrupts = <25 2>;
493                 bus-range = <0 0>;
494                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
495                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
496                 clock-frequency = <66666666>;
497                 #interrupt-cells = <1>;
498                 #size-cells = <2>;
499                 #address-cells = <3>;
500                 reg = <0xe0009000 0x1000>;
501                 compatible = "fsl,mpc8540-pci";
502                 device_type = "pci";
503         };
504
505         pci2: pcie@e000a000 {
506                 cell-index = <2>;
507                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508                 interrupt-map = <
509
510                         /* IDSEL 0x0 (PEX) */
511                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
512                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
513                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
514                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
515
516                 interrupt-parent = <&mpic>;
517                 interrupts = <26 2>;
518                 bus-range = <0 255>;
519                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
520                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
521                 clock-frequency = <33333333>;
522                 #interrupt-cells = <1>;
523                 #size-cells = <2>;
524                 #address-cells = <3>;
525                 reg = <0xe000a000 0x1000>;
526                 compatible = "fsl,mpc8548-pcie";
527                 device_type = "pci";
528                 pcie@0 {
529                         reg = <0x0 0x0 0x0 0x0 0x0>;
530                         #size-cells = <2>;
531                         #address-cells = <3>;
532                         device_type = "pci";
533                         ranges = <0x2000000 0x0 0xa0000000
534                                   0x2000000 0x0 0xa0000000
535                                   0x0 0x20000000
536
537                                   0x1000000 0x0 0x0
538                                   0x1000000 0x0 0x0
539                                   0x0 0x100000>;
540                 };
541         };
542 };