1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
5 * OMAP24XX Clock Management register bits
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 /* Bits shared between registers */
21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22 #define OMAP24XX_EN_CAM_SHIFT 31
23 #define OMAP24XX_EN_CAM (1 << 31)
24 #define OMAP24XX_EN_WDT4_SHIFT 29
25 #define OMAP24XX_EN_WDT4 (1 << 29)
26 #define OMAP2420_EN_WDT3_SHIFT 28
27 #define OMAP2420_EN_WDT3 (1 << 28)
28 #define OMAP24XX_EN_MSPRO_SHIFT 27
29 #define OMAP24XX_EN_MSPRO (1 << 27)
30 #define OMAP24XX_EN_FAC_SHIFT 25
31 #define OMAP24XX_EN_FAC (1 << 25)
32 #define OMAP2420_EN_EAC_SHIFT 24
33 #define OMAP2420_EN_EAC (1 << 24)
34 #define OMAP24XX_EN_HDQ_SHIFT 23
35 #define OMAP24XX_EN_HDQ (1 << 23)
36 #define OMAP2420_EN_I2C2_SHIFT 20
37 #define OMAP2420_EN_I2C2 (1 << 20)
38 #define OMAP2420_EN_I2C1_SHIFT 19
39 #define OMAP2420_EN_I2C1 (1 << 19)
41 /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
42 #define OMAP2430_EN_MCBSP5_SHIFT 5
43 #define OMAP2430_EN_MCBSP5 (1 << 5)
44 #define OMAP2430_EN_MCBSP4_SHIFT 4
45 #define OMAP2430_EN_MCBSP4 (1 << 4)
46 #define OMAP2430_EN_MCBSP3_SHIFT 3
47 #define OMAP2430_EN_MCBSP3 (1 << 3)
48 #define OMAP24XX_EN_SSI_SHIFT 1
49 #define OMAP24XX_EN_SSI (1 << 1)
51 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
52 #define OMAP24XX_EN_MPU_WDT_SHIFT 3
53 #define OMAP24XX_EN_MPU_WDT (1 << 3)
55 /* Bits specific to each register */
59 #define OMAP2430_ST_MPU (1 << 0)
62 #define OMAP24XX_CLKSEL_MPU_SHIFT 0
63 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
65 /* CM_CLKSTCTRL_MPU */
66 #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
67 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
69 /* CM_FCLKEN1_CORE specific bits*/
70 #define OMAP24XX_EN_TV_SHIFT 2
71 #define OMAP24XX_EN_TV (1 << 2)
72 #define OMAP24XX_EN_DSS2_SHIFT 1
73 #define OMAP24XX_EN_DSS2 (1 << 1)
74 #define OMAP24XX_EN_DSS1_SHIFT 0
75 #define OMAP24XX_EN_DSS1 (1 << 0)
77 /* CM_FCLKEN2_CORE specific bits */
78 #define OMAP2430_EN_I2CHS2_SHIFT 20
79 #define OMAP2430_EN_I2CHS2 (1 << 20)
80 #define OMAP2430_EN_I2CHS1_SHIFT 19
81 #define OMAP2430_EN_I2CHS1 (1 << 19)
82 #define OMAP2430_EN_MMCHSDB2_SHIFT 17
83 #define OMAP2430_EN_MMCHSDB2 (1 << 17)
84 #define OMAP2430_EN_MMCHSDB1_SHIFT 16
85 #define OMAP2430_EN_MMCHSDB1 (1 << 16)
87 /* CM_ICLKEN1_CORE specific bits */
88 #define OMAP24XX_EN_MAILBOXES_SHIFT 30
89 #define OMAP24XX_EN_MAILBOXES (1 << 30)
90 #define OMAP24XX_EN_DSS_SHIFT 0
91 #define OMAP24XX_EN_DSS (1 << 0)
93 /* CM_ICLKEN2_CORE specific bits */
97 #define OMAP2430_EN_SDRC_SHIFT 2
98 #define OMAP2430_EN_SDRC (1 << 2)
100 /* CM_ICLKEN4_CORE */
101 #define OMAP24XX_EN_PKA_SHIFT 4
102 #define OMAP24XX_EN_PKA (1 << 4)
103 #define OMAP24XX_EN_AES_SHIFT 3
104 #define OMAP24XX_EN_AES (1 << 3)
105 #define OMAP24XX_EN_RNG_SHIFT 2
106 #define OMAP24XX_EN_RNG (1 << 2)
107 #define OMAP24XX_EN_SHA_SHIFT 1
108 #define OMAP24XX_EN_SHA (1 << 1)
109 #define OMAP24XX_EN_DES_SHIFT 0
110 #define OMAP24XX_EN_DES (1 << 0)
112 /* CM_IDLEST1_CORE specific bits */
113 #define OMAP24XX_ST_MAILBOXES_SHIFT 30
114 #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
115 #define OMAP24XX_ST_WDT4_SHIFT 29
116 #define OMAP24XX_ST_WDT4_MASK (1 << 29)
117 #define OMAP2420_ST_WDT3_SHIFT 28
118 #define OMAP2420_ST_WDT3_MASK (1 << 28)
119 #define OMAP24XX_ST_MSPRO_SHIFT 27
120 #define OMAP24XX_ST_MSPRO_MASK (1 << 27)
121 #define OMAP24XX_ST_FAC_SHIFT 25
122 #define OMAP24XX_ST_FAC_MASK (1 << 25)
123 #define OMAP2420_ST_EAC_SHIFT 24
124 #define OMAP2420_ST_EAC_MASK (1 << 24)
125 #define OMAP24XX_ST_HDQ_SHIFT 23
126 #define OMAP24XX_ST_HDQ_MASK (1 << 23)
127 #define OMAP2420_ST_I2C2_SHIFT 20
128 #define OMAP2420_ST_I2C2_MASK (1 << 20)
129 #define OMAP2420_ST_I2C1_SHIFT 19
130 #define OMAP2420_ST_I2C1_MASK (1 << 19)
131 #define OMAP24XX_ST_MCBSP2_SHIFT 16
132 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
133 #define OMAP24XX_ST_MCBSP1_SHIFT 15
134 #define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
135 #define OMAP24XX_ST_DSS_SHIFT 0
136 #define OMAP24XX_ST_DSS_MASK (1 << 0)
138 /* CM_IDLEST2_CORE */
139 #define OMAP2430_ST_MCBSP5_SHIFT 5
140 #define OMAP2430_ST_MCBSP5_MASK (1 << 5)
141 #define OMAP2430_ST_MCBSP4_SHIFT 4
142 #define OMAP2430_ST_MCBSP4_MASK (1 << 4)
143 #define OMAP2430_ST_MCBSP3_SHIFT 3
144 #define OMAP2430_ST_MCBSP3_MASK (1 << 3)
145 #define OMAP24XX_ST_SSI_SHIFT 1
146 #define OMAP24XX_ST_SSI_MASK (1 << 1)
148 /* CM_IDLEST3_CORE */
150 #define OMAP2430_ST_SDRC_MASK (1 << 2)
152 /* CM_IDLEST4_CORE */
153 #define OMAP24XX_ST_PKA_SHIFT 4
154 #define OMAP24XX_ST_PKA_MASK (1 << 4)
155 #define OMAP24XX_ST_AES_SHIFT 3
156 #define OMAP24XX_ST_AES_MASK (1 << 3)
157 #define OMAP24XX_ST_RNG_SHIFT 2
158 #define OMAP24XX_ST_RNG_MASK (1 << 2)
159 #define OMAP24XX_ST_SHA_SHIFT 1
160 #define OMAP24XX_ST_SHA_MASK (1 << 1)
161 #define OMAP24XX_ST_DES_SHIFT 0
162 #define OMAP24XX_ST_DES_MASK (1 << 0)
164 /* CM_AUTOIDLE1_CORE */
165 #define OMAP24XX_AUTO_CAM (1 << 31)
166 #define OMAP24XX_AUTO_MAILBOXES (1 << 30)
167 #define OMAP24XX_AUTO_WDT4 (1 << 29)
168 #define OMAP2420_AUTO_WDT3 (1 << 28)
169 #define OMAP24XX_AUTO_MSPRO (1 << 27)
170 #define OMAP2420_AUTO_MMC (1 << 26)
171 #define OMAP24XX_AUTO_FAC (1 << 25)
172 #define OMAP2420_AUTO_EAC (1 << 24)
173 #define OMAP24XX_AUTO_HDQ (1 << 23)
174 #define OMAP24XX_AUTO_UART2 (1 << 22)
175 #define OMAP24XX_AUTO_UART1 (1 << 21)
176 #define OMAP24XX_AUTO_I2C2 (1 << 20)
177 #define OMAP24XX_AUTO_I2C1 (1 << 19)
178 #define OMAP24XX_AUTO_MCSPI2 (1 << 18)
179 #define OMAP24XX_AUTO_MCSPI1 (1 << 17)
180 #define OMAP24XX_AUTO_MCBSP2 (1 << 16)
181 #define OMAP24XX_AUTO_MCBSP1 (1 << 15)
182 #define OMAP24XX_AUTO_GPT12 (1 << 14)
183 #define OMAP24XX_AUTO_GPT11 (1 << 13)
184 #define OMAP24XX_AUTO_GPT10 (1 << 12)
185 #define OMAP24XX_AUTO_GPT9 (1 << 11)
186 #define OMAP24XX_AUTO_GPT8 (1 << 10)
187 #define OMAP24XX_AUTO_GPT7 (1 << 9)
188 #define OMAP24XX_AUTO_GPT6 (1 << 8)
189 #define OMAP24XX_AUTO_GPT5 (1 << 7)
190 #define OMAP24XX_AUTO_GPT4 (1 << 6)
191 #define OMAP24XX_AUTO_GPT3 (1 << 5)
192 #define OMAP24XX_AUTO_GPT2 (1 << 4)
193 #define OMAP2420_AUTO_VLYNQ (1 << 3)
194 #define OMAP24XX_AUTO_DSS (1 << 0)
196 /* CM_AUTOIDLE2_CORE */
197 #define OMAP2430_AUTO_MDM_INTC (1 << 11)
198 #define OMAP2430_AUTO_GPIO5 (1 << 10)
199 #define OMAP2430_AUTO_MCSPI3 (1 << 9)
200 #define OMAP2430_AUTO_MMCHS2 (1 << 8)
201 #define OMAP2430_AUTO_MMCHS1 (1 << 7)
202 #define OMAP2430_AUTO_USBHS (1 << 6)
203 #define OMAP2430_AUTO_MCBSP5 (1 << 5)
204 #define OMAP2430_AUTO_MCBSP4 (1 << 4)
205 #define OMAP2430_AUTO_MCBSP3 (1 << 3)
206 #define OMAP24XX_AUTO_UART3 (1 << 2)
207 #define OMAP24XX_AUTO_SSI (1 << 1)
208 #define OMAP24XX_AUTO_USB (1 << 0)
210 /* CM_AUTOIDLE3_CORE */
211 #define OMAP24XX_AUTO_SDRC (1 << 2)
212 #define OMAP24XX_AUTO_GPMC (1 << 1)
213 #define OMAP24XX_AUTO_SDMA (1 << 0)
215 /* CM_AUTOIDLE4_CORE */
216 #define OMAP24XX_AUTO_PKA (1 << 4)
217 #define OMAP24XX_AUTO_AES (1 << 3)
218 #define OMAP24XX_AUTO_RNG (1 << 2)
219 #define OMAP24XX_AUTO_SHA (1 << 1)
220 #define OMAP24XX_AUTO_DES (1 << 0)
222 /* CM_CLKSEL1_CORE */
223 #define OMAP24XX_CLKSEL_USB_SHIFT 25
224 #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
225 #define OMAP24XX_CLKSEL_SSI_SHIFT 20
226 #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
227 #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
228 #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
229 #define OMAP24XX_CLKSEL_DSS2_SHIFT 13
230 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
231 #define OMAP24XX_CLKSEL_DSS1_SHIFT 8
232 #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
233 #define OMAP24XX_CLKSEL_L4_SHIFT 5
234 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
235 #define OMAP24XX_CLKSEL_L3_SHIFT 0
236 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
238 /* CM_CLKSEL2_CORE */
239 #define OMAP24XX_CLKSEL_GPT12_SHIFT 22
240 #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
241 #define OMAP24XX_CLKSEL_GPT11_SHIFT 20
242 #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
243 #define OMAP24XX_CLKSEL_GPT10_SHIFT 18
244 #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
245 #define OMAP24XX_CLKSEL_GPT9_SHIFT 16
246 #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
247 #define OMAP24XX_CLKSEL_GPT8_SHIFT 14
248 #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
249 #define OMAP24XX_CLKSEL_GPT7_SHIFT 12
250 #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
251 #define OMAP24XX_CLKSEL_GPT6_SHIFT 10
252 #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
253 #define OMAP24XX_CLKSEL_GPT5_SHIFT 8
254 #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
255 #define OMAP24XX_CLKSEL_GPT4_SHIFT 6
256 #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
257 #define OMAP24XX_CLKSEL_GPT3_SHIFT 4
258 #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
259 #define OMAP24XX_CLKSEL_GPT2_SHIFT 2
260 #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
262 /* CM_CLKSTCTRL_CORE */
263 #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
264 #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
265 #define OMAP24XX_AUTOSTATE_L4_SHIFT 1
266 #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
267 #define OMAP24XX_AUTOSTATE_L3_SHIFT 0
268 #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
271 #define OMAP24XX_EN_3D_SHIFT 2
272 #define OMAP24XX_EN_3D (1 << 2)
273 #define OMAP24XX_EN_2D_SHIFT 1
274 #define OMAP24XX_EN_2D (1 << 1)
276 /* CM_ICLKEN_GFX specific bits */
278 /* CM_IDLEST_GFX specific bits */
280 /* CM_CLKSEL_GFX specific bits */
282 /* CM_CLKSTCTRL_GFX */
283 #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
284 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
286 /* CM_FCLKEN_WKUP specific bits */
288 /* CM_ICLKEN_WKUP specific bits */
289 #define OMAP2430_EN_ICR_SHIFT 6
290 #define OMAP2430_EN_ICR (1 << 6)
291 #define OMAP24XX_EN_OMAPCTRL_SHIFT 5
292 #define OMAP24XX_EN_OMAPCTRL (1 << 5)
293 #define OMAP24XX_EN_WDT1_SHIFT 4
294 #define OMAP24XX_EN_WDT1 (1 << 4)
295 #define OMAP24XX_EN_32KSYNC_SHIFT 1
296 #define OMAP24XX_EN_32KSYNC (1 << 1)
298 /* CM_IDLEST_WKUP specific bits */
299 #define OMAP2430_ST_ICR_SHIFT 6
300 #define OMAP2430_ST_ICR_MASK (1 << 6)
301 #define OMAP24XX_ST_OMAPCTRL_SHIFT 5
302 #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
303 #define OMAP24XX_ST_WDT1_SHIFT 4
304 #define OMAP24XX_ST_WDT1_MASK (1 << 4)
305 #define OMAP24XX_ST_MPU_WDT_SHIFT 3
306 #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
307 #define OMAP24XX_ST_32KSYNC_SHIFT 1
308 #define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
310 /* CM_AUTOIDLE_WKUP */
311 #define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
312 #define OMAP24XX_AUTO_WDT1 (1 << 4)
313 #define OMAP24XX_AUTO_MPU_WDT (1 << 3)
314 #define OMAP24XX_AUTO_GPIOS (1 << 2)
315 #define OMAP24XX_AUTO_32KSYNC (1 << 1)
316 #define OMAP24XX_AUTO_GPT1 (1 << 0)
319 #define OMAP24XX_CLKSEL_GPT1_SHIFT 0
320 #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
323 #define OMAP24XX_EN_54M_PLL_SHIFT 6
324 #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
325 #define OMAP24XX_EN_96M_PLL_SHIFT 2
326 #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
327 #define OMAP24XX_EN_DPLL_SHIFT 0
328 #define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
330 /* CM_IDLEST_CKGEN */
331 #define OMAP24XX_ST_54M_APLL (1 << 9)
332 #define OMAP24XX_ST_96M_APLL (1 << 8)
333 #define OMAP24XX_ST_54M_CLK (1 << 6)
334 #define OMAP24XX_ST_12M_CLK (1 << 5)
335 #define OMAP24XX_ST_48M_CLK (1 << 4)
336 #define OMAP24XX_ST_96M_CLK (1 << 2)
337 #define OMAP24XX_ST_CORE_CLK_SHIFT 0
338 #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
340 /* CM_AUTOIDLE_PLL */
341 #define OMAP24XX_AUTO_54M_SHIFT 6
342 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
343 #define OMAP24XX_AUTO_96M_SHIFT 2
344 #define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
345 #define OMAP24XX_AUTO_DPLL_SHIFT 0
346 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
349 #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
350 #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
351 #define OMAP24XX_APLLS_CLKIN_SHIFT 23
352 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
353 #define OMAP24XX_DPLL_MULT_SHIFT 12
354 #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
355 #define OMAP24XX_DPLL_DIV_SHIFT 8
356 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
357 #define OMAP24XX_54M_SOURCE_SHIFT 5
358 #define OMAP24XX_54M_SOURCE (1 << 5)
359 #define OMAP2430_96M_SOURCE_SHIFT 4
360 #define OMAP2430_96M_SOURCE (1 << 4)
361 #define OMAP24XX_48M_SOURCE_SHIFT 3
362 #define OMAP24XX_48M_SOURCE (1 << 3)
363 #define OMAP2430_ALTCLK_SOURCE_SHIFT 0
364 #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
367 #define OMAP24XX_CORE_CLK_SRC_SHIFT 0
368 #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
371 #define OMAP2420_EN_IVA_COP_SHIFT 10
372 #define OMAP2420_EN_IVA_COP (1 << 10)
373 #define OMAP2420_EN_IVA_MPU_SHIFT 8
374 #define OMAP2420_EN_IVA_MPU (1 << 8)
375 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
376 #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
379 #define OMAP2420_EN_DSP_IPI_SHIFT 1
380 #define OMAP2420_EN_DSP_IPI (1 << 1)
383 #define OMAP2420_ST_IVA (1 << 8)
384 #define OMAP2420_ST_IPI (1 << 1)
385 #define OMAP24XX_ST_DSP (1 << 0)
387 /* CM_AUTOIDLE_DSP */
388 #define OMAP2420_AUTO_DSP_IPI (1 << 1)
391 #define OMAP2420_SYNC_IVA (1 << 13)
392 #define OMAP2420_CLKSEL_IVA_SHIFT 8
393 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
394 #define OMAP24XX_SYNC_DSP (1 << 7)
395 #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
396 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
397 #define OMAP24XX_CLKSEL_DSP_SHIFT 0
398 #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
400 /* CM_CLKSTCTRL_DSP */
401 #define OMAP2420_AUTOSTATE_IVA_SHIFT 8
402 #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
403 #define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
404 #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
408 #define OMAP2430_EN_OSC_SHIFT 1
409 #define OMAP2430_EN_OSC (1 << 1)
413 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
414 #define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
416 /* CM_IDLEST_MDM specific bits */
419 /* CM_AUTOIDLE_MDM */
421 #define OMAP2430_AUTO_OSC (1 << 1)
422 #define OMAP2430_AUTO_MDM (1 << 0)
426 #define OMAP2430_SYNC_MDM (1 << 4)
427 #define OMAP2430_CLKSEL_MDM_SHIFT 0
428 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
430 /* CM_CLKSTCTRL_MDM */
432 #define OMAP2430_AUTOSTATE_MDM_SHIFT 0
433 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
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