2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
109 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119 /* constants for mapping table */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
128 PIIX_AHCI_DEVICE = 6,
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 enum piix_controller_ids {
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
147 ich8m_apple_sata_ahci, /* locks up on second port enable */
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
154 const u16 port_enable;
158 struct piix_host_priv {
163 static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
165 static void piix_pata_error_handler(struct ata_port *ap);
166 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
167 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static int ich_pata_cable_detect(struct ata_port *ap);
170 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
171 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
172 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
173 static void piix_sidpr_error_handler(struct ata_port *ap);
175 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176 static int piix_pci_device_resume(struct pci_dev *pdev);
179 static unsigned int in_module_init = 1;
181 static const struct pci_device_id piix_pci_tbl[] = {
182 /* Intel PIIX3 for the 430HX etc */
183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel ICH (i810, i815, i840) UDMA 66*/
196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
197 /* Intel ICH0 : UDMA 33*/
198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3 (E7500/1) UDMA 100 */
206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH6 (and 6) (i915) UDMA 100 */
217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH7/7-R (i945, i975) UDMA 100*/
219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH8 Mobile PATA Controller */
222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
224 /* NOTE: The following PCI ids must be kept in sync with the
225 * list in drivers/pci/quirks.c.
229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 6300ESB pretending RAID */
235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 82801FB/FW (ICH6/ICH6W) */
237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FR/FRW (ICH6R/ICH6RW) */
239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
241 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
248 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* Mobile SATA Controller IDE (ICH8M) */
253 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (ICH9M) */
263 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
268 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
270 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
279 { } /* terminate list */
282 static struct pci_driver piix_pci_driver = {
284 .id_table = piix_pci_tbl,
285 .probe = piix_init_one,
286 .remove = ata_pci_remove_one,
288 .suspend = piix_pci_device_suspend,
289 .resume = piix_pci_device_resume,
293 static struct scsi_host_template piix_sht = {
294 ATA_BMDMA_SHT(DRV_NAME),
297 static struct ata_port_operations piix_pata_ops = {
298 .inherits = &ata_bmdma_port_ops,
299 .cable_detect = ata_cable_40wire,
300 .set_piomode = piix_set_piomode,
301 .set_dmamode = piix_set_dmamode,
302 .error_handler = piix_pata_error_handler,
305 static struct ata_port_operations piix_vmw_ops = {
306 .inherits = &piix_pata_ops,
307 .bmdma_status = piix_vmw_bmdma_status,
310 static struct ata_port_operations ich_pata_ops = {
311 .inherits = &piix_pata_ops,
312 .cable_detect = ich_pata_cable_detect,
313 .set_dmamode = ich_set_dmamode,
316 static struct ata_port_operations piix_sata_ops = {
317 .inherits = &ata_bmdma_port_ops,
320 static struct ata_port_operations piix_sidpr_sata_ops = {
321 .inherits = &piix_sata_ops,
322 .scr_read = piix_sidpr_scr_read,
323 .scr_write = piix_sidpr_scr_write,
324 .error_handler = piix_sidpr_error_handler,
327 static const struct piix_map_db ich5_map_db = {
331 /* PM PS SM SS MAP */
332 { P0, NA, P1, NA }, /* 000b */
333 { P1, NA, P0, NA }, /* 001b */
336 { P0, P1, IDE, IDE }, /* 100b */
337 { P1, P0, IDE, IDE }, /* 101b */
338 { IDE, IDE, P0, P1 }, /* 110b */
339 { IDE, IDE, P1, P0 }, /* 111b */
343 static const struct piix_map_db ich6_map_db = {
347 /* PM PS SM SS MAP */
348 { P0, P2, P1, P3 }, /* 00b */
349 { IDE, IDE, P1, P3 }, /* 01b */
350 { P0, P2, IDE, IDE }, /* 10b */
355 static const struct piix_map_db ich6m_map_db = {
359 /* Map 01b isn't specified in the doc but some notebooks use
360 * it anyway. MAP 01b have been spotted on both ICH6M and
364 /* PM PS SM SS MAP */
365 { P0, P2, NA, NA }, /* 00b */
366 { IDE, IDE, P1, P3 }, /* 01b */
367 { P0, P2, IDE, IDE }, /* 10b */
372 static const struct piix_map_db ich8_map_db = {
376 /* PM PS SM SS MAP */
377 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
379 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
384 static const struct piix_map_db ich8_2port_map_db = {
388 /* PM PS SM SS MAP */
389 { P0, NA, P1, NA }, /* 00b */
390 { RV, RV, RV, RV }, /* 01b */
391 { RV, RV, RV, RV }, /* 10b */
396 static const struct piix_map_db ich8m_apple_map_db = {
400 /* PM PS SM SS MAP */
401 { P0, NA, NA, NA }, /* 00b */
403 { P0, P2, IDE, IDE }, /* 10b */
408 static const struct piix_map_db tolapai_map_db = {
412 /* PM PS SM SS MAP */
413 { P0, NA, P1, NA }, /* 00b */
414 { RV, RV, RV, RV }, /* 01b */
415 { RV, RV, RV, RV }, /* 10b */
420 static const struct piix_map_db *piix_map_db_table[] = {
421 [ich5_sata] = &ich5_map_db,
422 [ich6_sata] = &ich6_map_db,
423 [ich6_sata_ahci] = &ich6_map_db,
424 [ich6m_sata_ahci] = &ich6m_map_db,
425 [ich8_sata_ahci] = &ich8_map_db,
426 [ich8_2port_sata] = &ich8_2port_map_db,
427 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
428 [tolapai_sata_ahci] = &tolapai_map_db,
431 static struct ata_port_info piix_port_info[] = {
432 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
434 .flags = PIIX_PATA_FLAGS,
435 .pio_mask = 0x1f, /* pio0-4 */
436 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
437 .port_ops = &piix_pata_ops,
440 [piix_pata_33] = /* PIIX4 at 33MHz */
442 .flags = PIIX_PATA_FLAGS,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
445 .udma_mask = ATA_UDMA_MASK_40C,
446 .port_ops = &piix_pata_ops,
449 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
451 .flags = PIIX_PATA_FLAGS,
452 .pio_mask = 0x1f, /* pio 0-4 */
453 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
454 .udma_mask = ATA_UDMA2, /* UDMA33 */
455 .port_ops = &ich_pata_ops,
458 [ich_pata_66] = /* ICH controllers up to 66MHz */
460 .flags = PIIX_PATA_FLAGS,
461 .pio_mask = 0x1f, /* pio 0-4 */
462 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
463 .udma_mask = ATA_UDMA4,
464 .port_ops = &ich_pata_ops,
469 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
470 .pio_mask = 0x1f, /* pio0-4 */
471 .mwdma_mask = 0x06, /* mwdma1-2 */
472 .udma_mask = ATA_UDMA5, /* udma0-5 */
473 .port_ops = &ich_pata_ops,
478 .flags = PIIX_SATA_FLAGS,
479 .pio_mask = 0x1f, /* pio0-4 */
480 .mwdma_mask = 0x07, /* mwdma0-2 */
481 .udma_mask = ATA_UDMA6,
482 .port_ops = &piix_sata_ops,
487 .flags = PIIX_SATA_FLAGS,
488 .pio_mask = 0x1f, /* pio0-4 */
489 .mwdma_mask = 0x07, /* mwdma0-2 */
490 .udma_mask = ATA_UDMA6,
491 .port_ops = &piix_sata_ops,
496 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
497 .pio_mask = 0x1f, /* pio0-4 */
498 .mwdma_mask = 0x07, /* mwdma0-2 */
499 .udma_mask = ATA_UDMA6,
500 .port_ops = &piix_sata_ops,
505 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
506 .pio_mask = 0x1f, /* pio0-4 */
507 .mwdma_mask = 0x07, /* mwdma0-2 */
508 .udma_mask = ATA_UDMA6,
509 .port_ops = &piix_sata_ops,
514 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
516 .pio_mask = 0x1f, /* pio0-4 */
517 .mwdma_mask = 0x07, /* mwdma0-2 */
518 .udma_mask = ATA_UDMA6,
519 .port_ops = &piix_sata_ops,
524 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
526 .pio_mask = 0x1f, /* pio0-4 */
527 .mwdma_mask = 0x07, /* mwdma0-2 */
528 .udma_mask = ATA_UDMA6,
529 .port_ops = &piix_sata_ops,
532 [tolapai_sata_ahci] =
534 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
535 .pio_mask = 0x1f, /* pio0-4 */
536 .mwdma_mask = 0x07, /* mwdma0-2 */
537 .udma_mask = ATA_UDMA6,
538 .port_ops = &piix_sata_ops,
541 [ich8m_apple_sata_ahci] =
543 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
545 .pio_mask = 0x1f, /* pio0-4 */
546 .mwdma_mask = 0x07, /* mwdma0-2 */
547 .udma_mask = ATA_UDMA6,
548 .port_ops = &piix_sata_ops,
553 .flags = PIIX_PATA_FLAGS,
554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
556 .udma_mask = ATA_UDMA_MASK_40C,
557 .port_ops = &piix_vmw_ops,
562 static struct pci_bits piix_enable_bits[] = {
563 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
564 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
567 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
568 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
569 MODULE_LICENSE("GPL");
570 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
571 MODULE_VERSION(DRV_VERSION);
580 * List of laptops that use short cables rather than 80 wire
583 static const struct ich_laptop ich_laptop[] = {
584 /* devid, subvendor, subdev */
585 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
586 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
587 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
588 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
589 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
590 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
596 * ich_pata_cable_detect - Probe host controller cable detect info
597 * @ap: Port for which cable detect info is desired
599 * Read 80c cable indicator from ATA PCI device's PCI config
600 * register. This register is normally set by firmware (BIOS).
603 * None (inherited from caller).
606 static int ich_pata_cable_detect(struct ata_port *ap)
608 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
609 const struct ich_laptop *lap = &ich_laptop[0];
612 /* Check for specials - Acer Aspire 5602WLMi */
613 while (lap->device) {
614 if (lap->device == pdev->device &&
615 lap->subvendor == pdev->subsystem_vendor &&
616 lap->subdevice == pdev->subsystem_device)
617 return ATA_CBL_PATA40_SHORT;
622 /* check BIOS cable detect results */
623 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
624 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
625 if ((tmp & mask) == 0)
626 return ATA_CBL_PATA40;
627 return ATA_CBL_PATA80;
631 * piix_pata_prereset - prereset for PATA host controller
633 * @deadline: deadline jiffies for the operation
636 * None (inherited from caller).
638 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
640 struct ata_port *ap = link->ap;
641 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
643 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
645 return ata_std_prereset(link, deadline);
648 static void piix_pata_error_handler(struct ata_port *ap)
650 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
655 * piix_set_piomode - Initialize host controller PATA PIO timings
656 * @ap: Port whose timings we are configuring
659 * Set PIO mode for device, in host controller PCI config space.
662 * None (inherited from caller).
665 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
667 unsigned int pio = adev->pio_mode - XFER_PIO_0;
668 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669 unsigned int is_slave = (adev->devno != 0);
670 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
671 unsigned int slave_port = 0x44;
678 * See Intel Document 298600-004 for the timing programing rules
679 * for ICH controllers.
682 static const /* ISP RTC */
683 u8 timings[][2] = { { 0, 0 },
690 control |= 1; /* TIME1 enable */
691 if (ata_pio_need_iordy(adev))
692 control |= 2; /* IE enable */
694 /* Intel specifies that the PPE functionality is for disk only */
695 if (adev->class == ATA_DEV_ATA)
696 control |= 4; /* PPE enable */
698 /* PIO configuration clears DTE unconditionally. It will be
699 * programmed in set_dmamode which is guaranteed to be called
700 * after set_piomode if any DMA mode is available.
702 pci_read_config_word(dev, master_port, &master_data);
704 /* clear TIME1|IE1|PPE1|DTE1 */
705 master_data &= 0xff0f;
706 /* Enable SITRE (separate slave timing register) */
707 master_data |= 0x4000;
708 /* enable PPE1, IE1 and TIME1 as needed */
709 master_data |= (control << 4);
710 pci_read_config_byte(dev, slave_port, &slave_data);
711 slave_data &= (ap->port_no ? 0x0f : 0xf0);
712 /* Load the timing nibble for this slave */
713 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
714 << (ap->port_no ? 4 : 0);
716 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
717 master_data &= 0xccf0;
718 /* Enable PPE, IE and TIME as appropriate */
719 master_data |= control;
720 /* load ISP and RCT */
722 (timings[pio][0] << 12) |
723 (timings[pio][1] << 8);
725 pci_write_config_word(dev, master_port, master_data);
727 pci_write_config_byte(dev, slave_port, slave_data);
729 /* Ensure the UDMA bit is off - it will be turned back on if
733 pci_read_config_byte(dev, 0x48, &udma_enable);
734 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
735 pci_write_config_byte(dev, 0x48, udma_enable);
740 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
741 * @ap: Port whose timings we are configuring
742 * @adev: Drive in question
743 * @udma: udma mode, 0 - 6
744 * @isich: set if the chip is an ICH device
746 * Set UDMA mode for device, in host controller PCI config space.
749 * None (inherited from caller).
752 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
754 struct pci_dev *dev = to_pci_dev(ap->host->dev);
755 u8 master_port = ap->port_no ? 0x42 : 0x40;
757 u8 speed = adev->dma_mode;
758 int devid = adev->devno + 2 * ap->port_no;
761 static const /* ISP RTC */
762 u8 timings[][2] = { { 0, 0 },
768 pci_read_config_word(dev, master_port, &master_data);
770 pci_read_config_byte(dev, 0x48, &udma_enable);
772 if (speed >= XFER_UDMA_0) {
773 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
776 int u_clock, u_speed;
779 * UDMA is handled by a combination of clock switching and
780 * selection of dividers
782 * Handy rule: Odd modes are UDMATIMx 01, even are 02
783 * except UDMA0 which is 00
785 u_speed = min(2 - (udma & 1), udma);
787 u_clock = 0x1000; /* 100Mhz */
789 u_clock = 1; /* 66Mhz */
791 u_clock = 0; /* 33Mhz */
793 udma_enable |= (1 << devid);
795 /* Load the CT/RP selection */
796 pci_read_config_word(dev, 0x4A, &udma_timing);
797 udma_timing &= ~(3 << (4 * devid));
798 udma_timing |= u_speed << (4 * devid);
799 pci_write_config_word(dev, 0x4A, udma_timing);
802 /* Select a 33/66/100Mhz clock */
803 pci_read_config_word(dev, 0x54, &ideconf);
804 ideconf &= ~(0x1001 << devid);
805 ideconf |= u_clock << devid;
806 /* For ICH or later we should set bit 10 for better
807 performance (WR_PingPong_En) */
808 pci_write_config_word(dev, 0x54, ideconf);
812 * MWDMA is driven by the PIO timings. We must also enable
813 * IORDY unconditionally along with TIME1. PPE has already
814 * been set when the PIO timing was set.
816 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
817 unsigned int control;
819 const unsigned int needed_pio[3] = {
820 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
822 int pio = needed_pio[mwdma] - XFER_PIO_0;
824 control = 3; /* IORDY|TIME1 */
826 /* If the drive MWDMA is faster than it can do PIO then
827 we must force PIO into PIO0 */
829 if (adev->pio_mode < needed_pio[mwdma])
830 /* Enable DMA timing only */
831 control |= 8; /* PIO cycles in PIO0 */
833 if (adev->devno) { /* Slave */
834 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
835 master_data |= control << 4;
836 pci_read_config_byte(dev, 0x44, &slave_data);
837 slave_data &= (ap->port_no ? 0x0f : 0xf0);
838 /* Load the matching timing */
839 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
840 pci_write_config_byte(dev, 0x44, slave_data);
841 } else { /* Master */
842 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
843 and master timing bits */
844 master_data |= control;
846 (timings[pio][0] << 12) |
847 (timings[pio][1] << 8);
851 udma_enable &= ~(1 << devid);
852 pci_write_config_word(dev, master_port, master_data);
855 /* Don't scribble on 0x48 if the controller does not support UDMA */
857 pci_write_config_byte(dev, 0x48, udma_enable);
861 * piix_set_dmamode - Initialize host controller PATA DMA timings
862 * @ap: Port whose timings we are configuring
865 * Set MW/UDMA mode for device, in host controller PCI config space.
868 * None (inherited from caller).
871 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
873 do_pata_set_dmamode(ap, adev, 0);
877 * ich_set_dmamode - Initialize host controller PATA DMA timings
878 * @ap: Port whose timings we are configuring
881 * Set MW/UDMA mode for device, in host controller PCI config space.
884 * None (inherited from caller).
887 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
889 do_pata_set_dmamode(ap, adev, 1);
893 * Serial ATA Index/Data Pair Superset Registers access
895 * Beginning from ICH8, there's a sane way to access SCRs using index
896 * and data register pair located at BAR5. This creates an
897 * interesting problem of mapping two SCRs to one port.
899 * Although they have separate SCRs, the master and slave aren't
900 * independent enough to be treated as separate links - e.g. softreset
901 * resets both. Also, there's no protocol defined for hard resetting
902 * singled device sharing the virtual port (no defined way to acquire
903 * device signature). This is worked around by merging the SCR values
904 * into one sensible value and requesting follow-up SRST after
907 * SCR merging is perfomed in nibbles which is the unit contents in
908 * SCRs are organized. If two values are equal, the value is used.
909 * When they differ, merge table which lists precedence of possible
910 * values is consulted and the first match or the last entry when
911 * nothing matches is used. When there's no merge table for the
912 * specific nibble, value from the first port is used.
914 static const int piix_sidx_map[] = {
920 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
922 struct ata_port *ap = dev->link->ap;
923 struct piix_host_priv *hpriv = ap->host->private_data;
925 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
926 hpriv->sidpr + PIIX_SIDPR_IDX);
929 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
931 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
933 piix_sidpr_sel(dev, reg);
934 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
937 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
939 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
941 piix_sidpr_sel(dev, reg);
942 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
945 static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
950 for (i = 0, mi = 0; i < 32 / 4; i++) {
951 u8 c0 = (val0 >> (i * 4)) & 0xf;
952 u8 c1 = (val1 >> (i * 4)) & 0xf;
956 /* if no merge preference, assume the first value */
962 /* if two values equal, use it */
966 /* choose the first match or the last from the merge table */
968 if (c0 == *cur || c1 == *cur)
976 val |= merged << (i * 4);
982 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
984 const int * const sstatus_merge_tbl[] = {
985 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
986 /* SPD */ (const int []){ 2, 1, 0, -1 },
987 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
990 const int * const scontrol_merge_tbl[] = {
991 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
992 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
993 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
998 if (reg >= ARRAY_SIZE(piix_sidx_map))
1001 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
1002 *val = piix_sidpr_read(&ap->link.device[0], reg);
1006 v0 = piix_sidpr_read(&ap->link.device[0], reg);
1007 v1 = piix_sidpr_read(&ap->link.device[1], reg);
1011 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1017 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1024 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1026 if (reg >= ARRAY_SIZE(piix_sidx_map))
1029 piix_sidpr_write(&ap->link.device[0], reg, val);
1031 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1032 piix_sidpr_write(&ap->link.device[1], reg, val);
1037 static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class,
1038 unsigned long deadline)
1040 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1044 rc = sata_link_hardreset(link, timing, deadline);
1046 ata_link_printk(link, KERN_ERR,
1047 "COMRESET failed (errno=%d)\n", rc);
1051 /* TODO: phy layer with polling, timeouts, etc. */
1052 if (ata_link_offline(link)) {
1053 *class = ATA_DEV_NONE;
1060 static void piix_sidpr_error_handler(struct ata_port *ap)
1062 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1063 piix_sidpr_hardreset, ata_std_postreset);
1067 static int piix_broken_suspend(void)
1069 static const struct dmi_system_id sysids[] = {
1071 .ident = "TECRA M3",
1073 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1074 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1078 .ident = "TECRA M3",
1080 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1081 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1085 .ident = "TECRA M4",
1087 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1088 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1092 .ident = "TECRA M5",
1094 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1095 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1099 .ident = "TECRA M6",
1101 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1102 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1106 .ident = "TECRA M7",
1108 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1109 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1113 .ident = "TECRA A8",
1115 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1120 .ident = "Satellite R20",
1122 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1123 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1127 .ident = "Satellite R25",
1129 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1130 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1134 .ident = "Satellite U200",
1136 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1137 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1141 .ident = "Satellite U200",
1143 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1144 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1148 .ident = "Satellite Pro U200",
1150 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1151 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1155 .ident = "Satellite U205",
1157 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1158 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1162 .ident = "SATELLITE U205",
1164 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1169 .ident = "Portege M500",
1171 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1172 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1176 { } /* terminate list */
1178 static const char *oemstrs[] = {
1183 if (dmi_check_system(sysids))
1186 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1187 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1193 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1195 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1196 unsigned long flags;
1199 rc = ata_host_suspend(host, mesg);
1203 /* Some braindamaged ACPI suspend implementations expect the
1204 * controller to be awake on entry; otherwise, it burns cpu
1205 * cycles and power trying to do something to the sleeping
1208 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1209 pci_save_state(pdev);
1211 /* mark its power state as "unknown", since we don't
1212 * know if e.g. the BIOS will change its device state
1215 if (pdev->current_state == PCI_D0)
1216 pdev->current_state = PCI_UNKNOWN;
1218 /* tell resume that it's waking up from broken suspend */
1219 spin_lock_irqsave(&host->lock, flags);
1220 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1221 spin_unlock_irqrestore(&host->lock, flags);
1223 ata_pci_device_do_suspend(pdev, mesg);
1228 static int piix_pci_device_resume(struct pci_dev *pdev)
1230 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1231 unsigned long flags;
1234 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1235 spin_lock_irqsave(&host->lock, flags);
1236 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1237 spin_unlock_irqrestore(&host->lock, flags);
1239 pci_set_power_state(pdev, PCI_D0);
1240 pci_restore_state(pdev);
1242 /* PCI device wasn't disabled during suspend. Use
1243 * pci_reenable_device() to avoid affecting the enable
1246 rc = pci_reenable_device(pdev);
1248 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1249 "device after resume (%d)\n", rc);
1251 rc = ata_pci_device_do_resume(pdev);
1254 ata_host_resume(host);
1260 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1262 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1265 #define AHCI_PCI_BAR 5
1266 #define AHCI_GLOBAL_CTL 0x04
1267 #define AHCI_ENABLE (1 << 31)
1268 static int piix_disable_ahci(struct pci_dev *pdev)
1274 /* BUG: pci_enable_device has not yet been called. This
1275 * works because this device is usually set up by BIOS.
1278 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1279 !pci_resource_len(pdev, AHCI_PCI_BAR))
1282 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1286 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1287 if (tmp & AHCI_ENABLE) {
1288 tmp &= ~AHCI_ENABLE;
1289 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1291 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1292 if (tmp & AHCI_ENABLE)
1296 pci_iounmap(pdev, mmio);
1301 * piix_check_450nx_errata - Check for problem 450NX setup
1302 * @ata_dev: the PCI device to check
1304 * Check for the present of 450NX errata #19 and errata #25. If
1305 * they are found return an error code so we can turn off DMA
1308 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1310 struct pci_dev *pdev = NULL;
1312 int no_piix_dma = 0;
1314 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1315 /* Look for 450NX PXB. Check for problem configurations
1316 A PCI quirk checks bit 6 already */
1317 pci_read_config_word(pdev, 0x41, &cfg);
1318 /* Only on the original revision: IDE DMA can hang */
1319 if (pdev->revision == 0x00)
1321 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1322 else if (cfg & (1<<14) && pdev->revision < 5)
1326 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1327 if (no_piix_dma == 2)
1328 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1332 static void __devinit piix_init_pcs(struct ata_host *host,
1333 const struct piix_map_db *map_db)
1335 struct pci_dev *pdev = to_pci_dev(host->dev);
1338 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1340 new_pcs = pcs | map_db->port_enable;
1342 if (new_pcs != pcs) {
1343 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1344 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1349 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1350 struct ata_port_info *pinfo,
1351 const struct piix_map_db *map_db)
1354 int i, invalid_map = 0;
1357 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1359 map = map_db->map[map_value & map_db->mask];
1361 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1362 for (i = 0; i < 4; i++) {
1374 WARN_ON((i & 1) || map[i + 1] != IDE);
1375 pinfo[i / 2] = piix_port_info[ich_pata_100];
1381 printk(" P%d", map[i]);
1383 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1390 dev_printk(KERN_ERR, &pdev->dev,
1391 "invalid MAP value %u\n", map_value);
1396 static void __devinit piix_init_sidpr(struct ata_host *host)
1398 struct pci_dev *pdev = to_pci_dev(host->dev);
1399 struct piix_host_priv *hpriv = host->private_data;
1402 /* check for availability */
1403 for (i = 0; i < 4; i++)
1404 if (hpriv->map[i] == IDE)
1407 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1410 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1411 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1414 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1417 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1418 host->ports[0]->ops = &piix_sidpr_sata_ops;
1419 host->ports[1]->ops = &piix_sidpr_sata_ops;
1422 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1424 static const struct dmi_system_id sysids[] = {
1426 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1427 * isn't used to boot the system which
1428 * disables the channel.
1432 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1433 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1437 { } /* terminate list */
1441 if (!dmi_check_system(sysids))
1444 /* The datasheet says that bit 18 is NOOP but certain systems
1445 * seem to use it to disable a channel. Clear the bit on the
1448 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1449 if (iocfg & (1 << 18)) {
1450 dev_printk(KERN_INFO, &pdev->dev,
1451 "applying IOCFG bit18 quirk\n");
1452 iocfg &= ~(1 << 18);
1453 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1458 * piix_init_one - Register PIIX ATA PCI device with kernel services
1459 * @pdev: PCI device to register
1460 * @ent: Entry in piix_pci_tbl matching with @pdev
1462 * Called from kernel PCI layer. We probe for combined mode (sigh),
1463 * and then hand over control to libata, for it to do the rest.
1466 * Inherited from PCI layer (may sleep).
1469 * Zero on success, or -ERRNO value.
1472 static int __devinit piix_init_one(struct pci_dev *pdev,
1473 const struct pci_device_id *ent)
1475 static int printed_version;
1476 struct device *dev = &pdev->dev;
1477 struct ata_port_info port_info[2];
1478 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1479 unsigned long port_flags;
1480 struct ata_host *host;
1481 struct piix_host_priv *hpriv;
1484 if (!printed_version++)
1485 dev_printk(KERN_DEBUG, &pdev->dev,
1486 "version " DRV_VERSION "\n");
1488 /* no hotplugging support (FIXME) */
1489 if (!in_module_init)
1492 port_info[0] = piix_port_info[ent->driver_data];
1493 port_info[1] = piix_port_info[ent->driver_data];
1495 port_flags = port_info[0].flags;
1497 /* enable device and prepare host */
1498 rc = pcim_enable_device(pdev);
1502 /* SATA map init can change port_info, do it before prepping host */
1503 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1507 if (port_flags & ATA_FLAG_SATA)
1508 hpriv->map = piix_init_sata_map(pdev, port_info,
1509 piix_map_db_table[ent->driver_data]);
1511 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
1514 host->private_data = hpriv;
1516 /* initialize controller */
1517 if (port_flags & PIIX_FLAG_AHCI) {
1519 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1520 if (tmp == PIIX_AHCI_DEVICE) {
1521 rc = piix_disable_ahci(pdev);
1527 if (port_flags & ATA_FLAG_SATA) {
1528 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1529 piix_init_sidpr(host);
1532 /* apply IOCFG bit18 quirk */
1533 piix_iocfg_bit18_quirk(pdev);
1535 /* On ICH5, some BIOSen disable the interrupt using the
1536 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1537 * On ICH6, this bit has the same effect, but only when
1538 * MSI is disabled (and it is disabled, as we don't use
1539 * message-signalled interrupts currently).
1541 if (port_flags & PIIX_FLAG_CHECKINTR)
1544 if (piix_check_450nx_errata(pdev)) {
1545 /* This writes into the master table but it does not
1546 really matter for this errata as we will apply it to
1547 all the PIIX devices on the board */
1548 host->ports[0]->mwdma_mask = 0;
1549 host->ports[0]->udma_mask = 0;
1550 host->ports[1]->mwdma_mask = 0;
1551 host->ports[1]->udma_mask = 0;
1554 pci_set_master(pdev);
1555 return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht);
1558 static int __init piix_init(void)
1562 DPRINTK("pci_register_driver\n");
1563 rc = pci_register_driver(&piix_pci_driver);
1573 static void __exit piix_exit(void)
1575 pci_unregister_driver(&piix_pci_driver);
1578 module_init(piix_init);
1579 module_exit(piix_exit);