Merge branch 'for-linus' of git://git.monstr.eu/linux-2.6-microblaze
[linux-2.6] / drivers / edac / amd64_edac_inj.c
1 #include "amd64_edac.h"
2
3 /*
4  * store error injection section value which refers to one of 4 16-byte sections
5  * within a 64-byte cacheline
6  *
7  * range: 0..3
8  */
9 static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
10                                           const char *data, size_t count)
11 {
12         struct amd64_pvt *pvt = mci->pvt_info;
13         unsigned long value;
14         int ret = 0;
15
16         ret = strict_strtoul(data, 10, &value);
17         if (ret != -EINVAL) {
18                 pvt->injection.section = (u32) value;
19                 return count;
20         }
21         return ret;
22 }
23
24 /*
25  * store error injection word value which refers to one of 9 16-bit word of the
26  * 16-byte (128-bit + ECC bits) section
27  *
28  * range: 0..8
29  */
30 static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
31                                         const char *data, size_t count)
32 {
33         struct amd64_pvt *pvt = mci->pvt_info;
34         unsigned long value;
35         int ret = 0;
36
37         ret = strict_strtoul(data, 10, &value);
38         if (ret != -EINVAL) {
39
40                 value = (value <= 8) ? value : 0;
41                 pvt->injection.word = (u32) value;
42
43                 return count;
44         }
45         return ret;
46 }
47
48 /*
49  * store 16 bit error injection vector which enables injecting errors to the
50  * corresponding bit within the error injection word above. When used during a
51  * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
52  */
53 static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
54                                              const char *data, size_t count)
55 {
56         struct amd64_pvt *pvt = mci->pvt_info;
57         unsigned long value;
58         int ret = 0;
59
60         ret = strict_strtoul(data, 16, &value);
61         if (ret != -EINVAL) {
62
63                 pvt->injection.bit_map = (u32) value & 0xFFFF;
64
65                 return count;
66         }
67         return ret;
68 }
69
70 /*
71  * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
72  * fields needed by the injection registers and read the NB Array Data Port.
73  */
74 static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
75                                         const char *data, size_t count)
76 {
77         struct amd64_pvt *pvt = mci->pvt_info;
78         unsigned long value;
79         u32 section, word_bits;
80         int ret = 0;
81
82         ret = strict_strtoul(data, 10, &value);
83         if (ret != -EINVAL) {
84
85                 /* Form value to choose 16-byte section of cacheline */
86                 section = F10_NB_ARRAY_DRAM_ECC |
87                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
88                 pci_write_config_dword(pvt->misc_f3_ctl,
89                                         F10_NB_ARRAY_ADDR, section);
90
91                 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
92                                                 pvt->injection.bit_map);
93
94                 /* Issue 'word' and 'bit' along with the READ request */
95                 pci_write_config_dword(pvt->misc_f3_ctl,
96                                         F10_NB_ARRAY_DATA, word_bits);
97
98                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
99
100                 return count;
101         }
102         return ret;
103 }
104
105 /*
106  * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
107  * fields needed by the injection registers.
108  */
109 static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
110                                         const char *data, size_t count)
111 {
112         struct amd64_pvt *pvt = mci->pvt_info;
113         unsigned long value;
114         u32 section, word_bits;
115         int ret = 0;
116
117         ret = strict_strtoul(data, 10, &value);
118         if (ret != -EINVAL) {
119
120                 /* Form value to choose 16-byte section of cacheline */
121                 section = F10_NB_ARRAY_DRAM_ECC |
122                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
123                 pci_write_config_dword(pvt->misc_f3_ctl,
124                                         F10_NB_ARRAY_ADDR, section);
125
126                 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
127                                                 pvt->injection.bit_map);
128
129                 /* Issue 'word' and 'bit' along with the READ request */
130                 pci_write_config_dword(pvt->misc_f3_ctl,
131                                         F10_NB_ARRAY_DATA, word_bits);
132
133                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
134
135                 return count;
136         }
137         return ret;
138 }
139
140 /*
141  * update NUM_INJ_ATTRS in case you add new members
142  */
143 struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
144
145         {
146                 .attr = {
147                         .name = "inject_section",
148                         .mode = (S_IRUGO | S_IWUSR)
149                 },
150                 .show = NULL,
151                 .store = amd64_inject_section_store,
152         },
153         {
154                 .attr = {
155                         .name = "inject_word",
156                         .mode = (S_IRUGO | S_IWUSR)
157                 },
158                 .show = NULL,
159                 .store = amd64_inject_word_store,
160         },
161         {
162                 .attr = {
163                         .name = "inject_ecc_vector",
164                         .mode = (S_IRUGO | S_IWUSR)
165                 },
166                 .show = NULL,
167                 .store = amd64_inject_ecc_vector_store,
168         },
169         {
170                 .attr = {
171                         .name = "inject_write",
172                         .mode = (S_IRUGO | S_IWUSR)
173                 },
174                 .show = NULL,
175                 .store = amd64_inject_write_store,
176         },
177         {
178                 .attr = {
179                         .name = "inject_read",
180                         .mode = (S_IRUGO | S_IWUSR)
181                 },
182                 .show = NULL,
183                 .store = amd64_inject_read_store,
184         },
185 };