Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / arch / powerpc / platforms / iseries / pci.c
1 /*
2  * Copyright (C) 2001 Allan Trautman, IBM Corporation
3  *
4  * iSeries specific routines for PCI.
5  *
6  * Based on code from pci.c and iSeries_pci.c 32bit
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21  */
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
29
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/prom.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/iommu.h>
36 #include <asm/abs_addr.h>
37 #include <asm/firmware.h>
38
39 #include <asm/iseries/hv_call_xm.h>
40 #include <asm/iseries/mf.h>
41 #include <asm/iseries/iommu.h>
42
43 #include <asm/ppc-pci.h>
44
45 #include "irq.h"
46 #include "pci.h"
47 #include "call_pci.h"
48
49 /*
50  * Forward declares of prototypes.
51  */
52 static struct device_node *find_Device_Node(int bus, int devfn);
53
54 static int Pci_Retry_Max = 3;   /* Only retry 3 times  */
55 static int Pci_Error_Flag = 1;  /* Set Retry Error on. */
56
57 static struct pci_ops iSeries_pci_ops;
58
59 /*
60  * Table defines
61  * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
62  */
63 #define IOMM_TABLE_MAX_ENTRIES  1024
64 #define IOMM_TABLE_ENTRY_SIZE   0x0000000000400000UL
65 #define BASE_IO_MEMORY          0xE000000000000000UL
66
67 static unsigned long max_io_memory = BASE_IO_MEMORY;
68 static long current_iomm_table_entry;
69
70 /*
71  * Lookup Tables.
72  */
73 static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
74 static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
75
76 static const char pci_io_text[] = "iSeries PCI I/O";
77 static DEFINE_SPINLOCK(iomm_table_lock);
78
79 /*
80  * iomm_table_allocate_entry
81  *
82  * Adds pci_dev entry in address translation table
83  *
84  * - Allocates the number of entries required in table base on BAR
85  *   size.
86  * - Allocates starting at BASE_IO_MEMORY and increases.
87  * - The size is round up to be a multiple of entry size.
88  * - CurrentIndex is incremented to keep track of the last entry.
89  * - Builds the resource entry for allocated BARs.
90  */
91 static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
92 {
93         struct resource *bar_res = &dev->resource[bar_num];
94         long bar_size = pci_resource_len(dev, bar_num);
95
96         /*
97          * No space to allocate, quick exit, skip Allocation.
98          */
99         if (bar_size == 0)
100                 return;
101         /*
102          * Set Resource values.
103          */
104         spin_lock(&iomm_table_lock);
105         bar_res->name = pci_io_text;
106         bar_res->start = BASE_IO_MEMORY +
107                 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
108         bar_res->end = bar_res->start + bar_size - 1;
109         /*
110          * Allocate the number of table entries needed for BAR.
111          */
112         while (bar_size > 0 ) {
113                 iomm_table[current_iomm_table_entry] = dev->sysdata;
114                 iobar_table[current_iomm_table_entry] = bar_num;
115                 bar_size -= IOMM_TABLE_ENTRY_SIZE;
116                 ++current_iomm_table_entry;
117         }
118         max_io_memory = BASE_IO_MEMORY +
119                 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
120         spin_unlock(&iomm_table_lock);
121 }
122
123 /*
124  * allocate_device_bars
125  *
126  * - Allocates ALL pci_dev BAR's and updates the resources with the
127  *   BAR value.  BARS with zero length will have the resources
128  *   The HvCallPci_getBarParms is used to get the size of the BAR
129  *   space.  It calls iomm_table_allocate_entry to allocate
130  *   each entry.
131  * - Loops through The Bar resources(0 - 5) including the ROM
132  *   is resource(6).
133  */
134 static void allocate_device_bars(struct pci_dev *dev)
135 {
136         int bar_num;
137
138         for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
139                 iomm_table_allocate_entry(dev, bar_num);
140 }
141
142 /*
143  * Log error information to system console.
144  * Filter out the device not there errors.
145  * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
146  * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
147  * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
148  */
149 static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
150                 int AgentId, int HvRc)
151 {
152         if (HvRc == 0x0302)
153                 return;
154         printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
155                Error_Text, Bus, SubBus, AgentId, HvRc);
156 }
157
158 /*
159  * iSeries_pcibios_init
160  *
161  * Description:
162  *   This function checks for all possible system PCI host bridges that connect
163  *   PCI buses.  The system hypervisor is queried as to the guest partition
164  *   ownership status.  A pci_controller is built for any bus which is partially
165  *   owned or fully owned by this guest partition.
166  */
167 void iSeries_pcibios_init(void)
168 {
169         struct pci_controller *phb;
170         struct device_node *root = of_find_node_by_path("/");
171         struct device_node *node = NULL;
172
173         if (root == NULL) {
174                 printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
175                                 "of device tree\n");
176                 return;
177         }
178         while ((node = of_get_next_child(root, node)) != NULL) {
179                 HvBusNumber bus;
180                 const u32 *busp;
181
182                 if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
183                         continue;
184
185                 busp = get_property(node, "bus-range", NULL);
186                 if (busp == NULL)
187                         continue;
188                 bus = *busp;
189                 printk("bus %d appears to exist\n", bus);
190                 phb = pcibios_alloc_controller(node);
191                 if (phb == NULL)
192                         continue;
193
194                 phb->pci_mem_offset = phb->local_number = bus;
195                 phb->first_busno = bus;
196                 phb->last_busno = bus;
197                 phb->ops = &iSeries_pci_ops;
198         }
199
200         of_node_put(root);
201
202         pci_devs_phb_init();
203 }
204
205 /*
206  * iSeries_pci_final_fixup(void)
207  */
208 void __init iSeries_pci_final_fixup(void)
209 {
210         struct pci_dev *pdev = NULL;
211         struct device_node *node;
212         int DeviceCount = 0;
213
214         /* Fix up at the device node and pci_dev relationship */
215         mf_display_src(0xC9000100);
216
217         printk("pcibios_final_fixup\n");
218         for_each_pci_dev(pdev) {
219                 node = find_Device_Node(pdev->bus->number, pdev->devfn);
220                 printk("pci dev %p (%x.%x), node %p\n", pdev,
221                        pdev->bus->number, pdev->devfn, node);
222
223                 if (node != NULL) {
224                         struct pci_dn *pdn = PCI_DN(node);
225                         const u32 *agent;
226
227                         agent = get_property(node, "linux,agent-id", NULL);
228                         if ((pdn != NULL) && (agent != NULL)) {
229                                 u8 irq = iSeries_allocate_IRQ(pdn->busno, 0,
230                                                 pdn->bussubno);
231                                 int err;
232
233                                 err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno,
234                                                 *agent, irq);
235                                 if (err)
236                                         pci_Log_Error("Connect Bus Unit",
237                                                 pdn->busno, pdn->bussubno, *agent, err);
238                                 else {
239                                         err = HvCallPci_configStore8(pdn->busno, pdn->bussubno,
240                                                         *agent,
241                                                         PCI_INTERRUPT_LINE,
242                                                         irq);
243                                         if (err)
244                                                 pci_Log_Error("PciCfgStore Irq Failed!",
245                                                         pdn->busno, pdn->bussubno, *agent, err);
246                                 }
247                                 if (!err)
248                                         pdev->irq = irq;
249                         }
250
251                         ++DeviceCount;
252                         pdev->sysdata = (void *)node;
253                         PCI_DN(node)->pcidev = pdev;
254                         allocate_device_bars(pdev);
255                         iSeries_Device_Information(pdev, DeviceCount);
256                         iommu_devnode_init_iSeries(node);
257                 } else
258                         printk("PCI: Device Tree not found for 0x%016lX\n",
259                                         (unsigned long)pdev);
260         }
261         iSeries_activate_IRQs();
262         mf_display_src(0xC9000200);
263 }
264
265 void pcibios_fixup_bus(struct pci_bus *PciBus)
266 {
267 }
268
269 void pcibios_fixup_resources(struct pci_dev *pdev)
270 {
271 }
272
273 /*
274  * Look down the chain to find the matching Device Device
275  */
276 static struct device_node *find_Device_Node(int bus, int devfn)
277 {
278         struct device_node *node;
279
280         for (node = NULL; (node = of_find_all_nodes(node)); ) {
281                 struct pci_dn *pdn = PCI_DN(node);
282
283                 if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
284                         return node;
285         }
286         return NULL;
287 }
288
289 #if 0
290 /*
291  * Returns the device node for the passed pci_dev
292  * Sanity Check Node PciDev to passed pci_dev
293  * If none is found, returns a NULL which the client must handle.
294  */
295 static struct device_node *get_Device_Node(struct pci_dev *pdev)
296 {
297         struct device_node *node;
298
299         node = pdev->sysdata;
300         if (node == NULL || PCI_DN(node)->pcidev != pdev)
301                 node = find_Device_Node(pdev->bus->number, pdev->devfn);
302         return node;
303 }
304 #endif
305
306 /*
307  * Config space read and write functions.
308  * For now at least, we look for the device node for the bus and devfn
309  * that we are asked to access.  It may be possible to translate the devfn
310  * to a subbus and deviceid more directly.
311  */
312 static u64 hv_cfg_read_func[4]  = {
313         HvCallPciConfigLoad8, HvCallPciConfigLoad16,
314         HvCallPciConfigLoad32, HvCallPciConfigLoad32
315 };
316
317 static u64 hv_cfg_write_func[4] = {
318         HvCallPciConfigStore8, HvCallPciConfigStore16,
319         HvCallPciConfigStore32, HvCallPciConfigStore32
320 };
321
322 /*
323  * Read PCI config space
324  */
325 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
326                 int offset, int size, u32 *val)
327 {
328         struct device_node *node = find_Device_Node(bus->number, devfn);
329         u64 fn;
330         struct HvCallPci_LoadReturn ret;
331
332         if (node == NULL)
333                 return PCIBIOS_DEVICE_NOT_FOUND;
334         if (offset > 255) {
335                 *val = ~0;
336                 return PCIBIOS_BAD_REGISTER_NUMBER;
337         }
338
339         fn = hv_cfg_read_func[(size - 1) & 3];
340         HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
341
342         if (ret.rc != 0) {
343                 *val = ~0;
344                 return PCIBIOS_DEVICE_NOT_FOUND;        /* or something */
345         }
346
347         *val = ret.value;
348         return 0;
349 }
350
351 /*
352  * Write PCI config space
353  */
354
355 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
356                 int offset, int size, u32 val)
357 {
358         struct device_node *node = find_Device_Node(bus->number, devfn);
359         u64 fn;
360         u64 ret;
361
362         if (node == NULL)
363                 return PCIBIOS_DEVICE_NOT_FOUND;
364         if (offset > 255)
365                 return PCIBIOS_BAD_REGISTER_NUMBER;
366
367         fn = hv_cfg_write_func[(size - 1) & 3];
368         ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
369
370         if (ret != 0)
371                 return PCIBIOS_DEVICE_NOT_FOUND;
372
373         return 0;
374 }
375
376 static struct pci_ops iSeries_pci_ops = {
377         .read = iSeries_pci_read_config,
378         .write = iSeries_pci_write_config
379 };
380
381 /*
382  * Check Return Code
383  * -> On Failure, print and log information.
384  *    Increment Retry Count, if exceeds max, panic partition.
385  *
386  * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
387  * PCI: Device 23.90 ReadL Retry( 1)
388  * PCI: Device 23.90 ReadL Retry Successful(1)
389  */
390 static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
391                 int *retry, u64 ret)
392 {
393         if (ret != 0)  {
394                 struct pci_dn *pdn = PCI_DN(DevNode);
395
396                 (*retry)++;
397                 printk("PCI: %s: Device 0x%04X:%02X  I/O Error(%2d): 0x%04X\n",
398                                 TextHdr, pdn->busno, pdn->devfn,
399                                 *retry, (int)ret);
400                 /*
401                  * Bump the retry and check for retry count exceeded.
402                  * If, Exceeded, panic the system.
403                  */
404                 if (((*retry) > Pci_Retry_Max) &&
405                                 (Pci_Error_Flag > 0)) {
406                         mf_display_src(0xB6000103);
407                         panic_timeout = 0;
408                         panic("PCI: Hardware I/O Error, SRC B6000103, "
409                                         "Automatic Reboot Disabled.\n");
410                 }
411                 return -1;      /* Retry Try */
412         }
413         return 0;
414 }
415
416 /*
417  * Translate the I/O Address into a device node, bar, and bar offset.
418  * Note: Make sure the passed variable end up on the stack to avoid
419  * the exposure of being device global.
420  */
421 static inline struct device_node *xlate_iomm_address(
422                 const volatile void __iomem *IoAddress,
423                 u64 *dsaptr, u64 *BarOffsetPtr)
424 {
425         unsigned long OrigIoAddr;
426         unsigned long BaseIoAddr;
427         unsigned long TableIndex;
428         struct device_node *DevNode;
429
430         OrigIoAddr = (unsigned long __force)IoAddress;
431         if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
432                 return NULL;
433         BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
434         TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
435         DevNode = iomm_table[TableIndex];
436
437         if (DevNode != NULL) {
438                 int barnum = iobar_table[TableIndex];
439                 *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24);
440                 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
441         } else
442                 panic("PCI: Invalid PCI IoAddress detected!\n");
443         return DevNode;
444 }
445
446 /*
447  * Read MM I/O Instructions for the iSeries
448  * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
449  * else, data is returned in big Endian format.
450  *
451  * iSeries_Read_Byte = Read Byte  ( 8 bit)
452  * iSeries_Read_Word = Read Word  (16 bit)
453  * iSeries_Read_Long = Read Long  (32 bit)
454  */
455 static u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
456 {
457         u64 BarOffset;
458         u64 dsa;
459         int retry = 0;
460         struct HvCallPci_LoadReturn ret;
461         struct device_node *DevNode =
462                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
463
464         if (DevNode == NULL) {
465                 static unsigned long last_jiffies;
466                 static int num_printed;
467
468                 if ((jiffies - last_jiffies) > 60 * HZ) {
469                         last_jiffies = jiffies;
470                         num_printed = 0;
471                 }
472                 if (num_printed++ < 10)
473                         printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
474                 return 0xff;
475         }
476         do {
477                 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
478         } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
479
480         return (u8)ret.value;
481 }
482
483 static u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
484 {
485         u64 BarOffset;
486         u64 dsa;
487         int retry = 0;
488         struct HvCallPci_LoadReturn ret;
489         struct device_node *DevNode =
490                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
491
492         if (DevNode == NULL) {
493                 static unsigned long last_jiffies;
494                 static int num_printed;
495
496                 if ((jiffies - last_jiffies) > 60 * HZ) {
497                         last_jiffies = jiffies;
498                         num_printed = 0;
499                 }
500                 if (num_printed++ < 10)
501                         printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
502                 return 0xffff;
503         }
504         do {
505                 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
506                                 BarOffset, 0);
507         } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
508
509         return swab16((u16)ret.value);
510 }
511
512 static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
513 {
514         u64 BarOffset;
515         u64 dsa;
516         int retry = 0;
517         struct HvCallPci_LoadReturn ret;
518         struct device_node *DevNode =
519                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
520
521         if (DevNode == NULL) {
522                 static unsigned long last_jiffies;
523                 static int num_printed;
524
525                 if ((jiffies - last_jiffies) > 60 * HZ) {
526                         last_jiffies = jiffies;
527                         num_printed = 0;
528                 }
529                 if (num_printed++ < 10)
530                         printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
531                 return 0xffffffff;
532         }
533         do {
534                 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
535                                 BarOffset, 0);
536         } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
537
538         return swab32((u32)ret.value);
539 }
540
541 /*
542  * Write MM I/O Instructions for the iSeries
543  *
544  * iSeries_Write_Byte = Write Byte (8 bit)
545  * iSeries_Write_Word = Write Word(16 bit)
546  * iSeries_Write_Long = Write Long(32 bit)
547  */
548 static void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
549 {
550         u64 BarOffset;
551         u64 dsa;
552         int retry = 0;
553         u64 rc;
554         struct device_node *DevNode =
555                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
556
557         if (DevNode == NULL) {
558                 static unsigned long last_jiffies;
559                 static int num_printed;
560
561                 if ((jiffies - last_jiffies) > 60 * HZ) {
562                         last_jiffies = jiffies;
563                         num_printed = 0;
564                 }
565                 if (num_printed++ < 10)
566                         printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
567                 return;
568         }
569         do {
570                 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
571         } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
572 }
573
574 static void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
575 {
576         u64 BarOffset;
577         u64 dsa;
578         int retry = 0;
579         u64 rc;
580         struct device_node *DevNode =
581                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
582
583         if (DevNode == NULL) {
584                 static unsigned long last_jiffies;
585                 static int num_printed;
586
587                 if ((jiffies - last_jiffies) > 60 * HZ) {
588                         last_jiffies = jiffies;
589                         num_printed = 0;
590                 }
591                 if (num_printed++ < 10)
592                         printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
593                 return;
594         }
595         do {
596                 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
597         } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
598 }
599
600 static void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
601 {
602         u64 BarOffset;
603         u64 dsa;
604         int retry = 0;
605         u64 rc;
606         struct device_node *DevNode =
607                 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
608
609         if (DevNode == NULL) {
610                 static unsigned long last_jiffies;
611                 static int num_printed;
612
613                 if ((jiffies - last_jiffies) > 60 * HZ) {
614                         last_jiffies = jiffies;
615                         num_printed = 0;
616                 }
617                 if (num_printed++ < 10)
618                         printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
619                 return;
620         }
621         do {
622                 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
623         } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
624 }
625
626 extern unsigned char __raw_readb(const volatile void __iomem *addr)
627 {
628         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
629
630         return *(volatile unsigned char __force *)addr;
631 }
632 EXPORT_SYMBOL(__raw_readb);
633
634 extern unsigned short __raw_readw(const volatile void __iomem *addr)
635 {
636         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
637
638         return *(volatile unsigned short __force *)addr;
639 }
640 EXPORT_SYMBOL(__raw_readw);
641
642 extern unsigned int __raw_readl(const volatile void __iomem *addr)
643 {
644         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
645
646         return *(volatile unsigned int __force *)addr;
647 }
648 EXPORT_SYMBOL(__raw_readl);
649
650 extern unsigned long __raw_readq(const volatile void __iomem *addr)
651 {
652         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
653
654         return *(volatile unsigned long __force *)addr;
655 }
656 EXPORT_SYMBOL(__raw_readq);
657
658 extern void __raw_writeb(unsigned char v, volatile void __iomem *addr)
659 {
660         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
661
662         *(volatile unsigned char __force *)addr = v;
663 }
664 EXPORT_SYMBOL(__raw_writeb);
665
666 extern void __raw_writew(unsigned short v, volatile void __iomem *addr)
667 {
668         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
669
670         *(volatile unsigned short __force *)addr = v;
671 }
672 EXPORT_SYMBOL(__raw_writew);
673
674 extern void __raw_writel(unsigned int v, volatile void __iomem *addr)
675 {
676         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
677
678         *(volatile unsigned int __force *)addr = v;
679 }
680 EXPORT_SYMBOL(__raw_writel);
681
682 extern void __raw_writeq(unsigned long v, volatile void __iomem *addr)
683 {
684         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
685
686         *(volatile unsigned long __force *)addr = v;
687 }
688 EXPORT_SYMBOL(__raw_writeq);
689
690 int in_8(const volatile unsigned char __iomem *addr)
691 {
692         if (firmware_has_feature(FW_FEATURE_ISERIES))
693                 return iSeries_Read_Byte(addr);
694         return __in_8(addr);
695 }
696 EXPORT_SYMBOL(in_8);
697
698 void out_8(volatile unsigned char __iomem *addr, int val)
699 {
700         if (firmware_has_feature(FW_FEATURE_ISERIES))
701                 iSeries_Write_Byte(val, addr);
702         else
703                 __out_8(addr, val);
704 }
705 EXPORT_SYMBOL(out_8);
706
707 int in_le16(const volatile unsigned short __iomem *addr)
708 {
709         if (firmware_has_feature(FW_FEATURE_ISERIES))
710                 return iSeries_Read_Word(addr);
711         return __in_le16(addr);
712 }
713 EXPORT_SYMBOL(in_le16);
714
715 int in_be16(const volatile unsigned short __iomem *addr)
716 {
717         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
718
719         return __in_be16(addr);
720 }
721 EXPORT_SYMBOL(in_be16);
722
723 void out_le16(volatile unsigned short __iomem *addr, int val)
724 {
725         if (firmware_has_feature(FW_FEATURE_ISERIES))
726                 iSeries_Write_Word(val, addr);
727         else
728                 __out_le16(addr, val);
729 }
730 EXPORT_SYMBOL(out_le16);
731
732 void out_be16(volatile unsigned short __iomem *addr, int val)
733 {
734         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
735
736         __out_be16(addr, val);
737 }
738 EXPORT_SYMBOL(out_be16);
739
740 unsigned in_le32(const volatile unsigned __iomem *addr)
741 {
742         if (firmware_has_feature(FW_FEATURE_ISERIES))
743                 return iSeries_Read_Long(addr);
744         return __in_le32(addr);
745 }
746 EXPORT_SYMBOL(in_le32);
747
748 unsigned in_be32(const volatile unsigned __iomem *addr)
749 {
750         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
751
752         return __in_be32(addr);
753 }
754 EXPORT_SYMBOL(in_be32);
755
756 void out_le32(volatile unsigned __iomem *addr, int val)
757 {
758         if (firmware_has_feature(FW_FEATURE_ISERIES))
759                 iSeries_Write_Long(val, addr);
760         else
761                 __out_le32(addr, val);
762 }
763 EXPORT_SYMBOL(out_le32);
764
765 void out_be32(volatile unsigned __iomem *addr, int val)
766 {
767         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
768
769         __out_be32(addr, val);
770 }
771 EXPORT_SYMBOL(out_be32);
772
773 unsigned long in_le64(const volatile unsigned long __iomem *addr)
774 {
775         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
776
777         return __in_le64(addr);
778 }
779 EXPORT_SYMBOL(in_le64);
780
781 unsigned long in_be64(const volatile unsigned long __iomem *addr)
782 {
783         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
784
785         return __in_be64(addr);
786 }
787 EXPORT_SYMBOL(in_be64);
788
789 void out_le64(volatile unsigned long __iomem *addr, unsigned long val)
790 {
791         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
792
793         __out_le64(addr, val);
794 }
795 EXPORT_SYMBOL(out_le64);
796
797 void out_be64(volatile unsigned long __iomem *addr, unsigned long val)
798 {
799         BUG_ON(firmware_has_feature(FW_FEATURE_ISERIES));
800
801         __out_be64(addr, val);
802 }
803 EXPORT_SYMBOL(out_be64);
804
805 void memset_io(volatile void __iomem *addr, int c, unsigned long n)
806 {
807         if (firmware_has_feature(FW_FEATURE_ISERIES)) {
808                 volatile char __iomem *d = addr;
809
810                 while (n-- > 0) {
811                         iSeries_Write_Byte(c, d++);
812                 }
813         } else
814                 eeh_memset_io(addr, c, n);
815 }
816 EXPORT_SYMBOL(memset_io);
817
818 void memcpy_fromio(void *dest, const volatile void __iomem *src,
819                                  unsigned long n)
820 {
821         if (firmware_has_feature(FW_FEATURE_ISERIES)) {
822                 char *d = dest;
823                 const volatile char __iomem *s = src;
824
825                 while (n-- > 0) {
826                         *d++ = iSeries_Read_Byte(s++);
827                 }
828         } else
829                 eeh_memcpy_fromio(dest, src, n);
830 }
831 EXPORT_SYMBOL(memcpy_fromio);
832
833 void memcpy_toio(volatile void __iomem *dest, const void *src, unsigned long n)
834 {
835         if (firmware_has_feature(FW_FEATURE_ISERIES)) {
836                 const char *s = src;
837                 volatile char __iomem *d = dest;
838
839                 while (n-- > 0) {
840                         iSeries_Write_Byte(*s++, d++);
841                 }
842         } else
843                 eeh_memcpy_toio(dest, src, n);
844 }
845 EXPORT_SYMBOL(memcpy_toio);