2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <asm/bitops.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /*-------------------------------------------------------------------------
47 * Omap2 specific clock functions
48 *-------------------------------------------------------------------------*/
51 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
52 * @clk: OMAP clock struct ptr to use
54 * Given a pointer to a source-selectable struct clk, read the hardware
55 * register and determine what its parent is currently set to. Update the
56 * clk->parent field with the appropriate clk ptr.
58 void omap2_init_clksel_parent(struct clk *clk)
60 const struct clksel *clks;
61 const struct clksel_rate *clkr;
67 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
68 r >>= __ffs(clk->clksel_mask);
70 for (clks = clk->clksel; clks->parent && !found; clks++) {
71 for (clkr = clks->rates; clkr->div && !found; clkr++) {
72 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
73 if (clk->parent != clks->parent) {
74 pr_debug("clock: inited %s parent "
76 clk->name, clks->parent->name,
78 clk->parent->name : "NULL"));
79 clk->parent = clks->parent;
87 printk(KERN_ERR "clock: init parent: could not find "
88 "regval %0x for clock %s\n", r, clk->name);
93 /* Returns the DPLL rate */
94 u32 omap2_get_dpll_rate(struct clk *clk)
97 u32 dpll_mult, dpll_div, dpll;
98 const struct dpll_data *dd;
101 /* REVISIT: What do we return on error? */
105 dpll = __raw_readl(dd->mult_div1_reg);
106 dpll_mult = dpll & dd->mult_mask;
107 dpll_mult >>= __ffs(dd->mult_mask);
108 dpll_div = dpll & dd->div1_mask;
109 dpll_div >>= __ffs(dd->div1_mask);
111 dpll_clk = (long long)clk->parent->rate * dpll_mult;
112 do_div(dpll_clk, dpll_div + 1);
116 dpll = __raw_readl(dd->div2_reg);
117 dpll_div = dpll & dd->div2_mask;
118 dpll_div >>= __ffs(dd->div2_mask);
119 do_div(dpll_clk, dpll_div + 1);
126 * Used for clocks that have the same value as the parent clock,
127 * divided by some factor
129 void omap2_fixed_divisor_recalc(struct clk *clk)
131 WARN_ON(!clk->fixed_div);
133 clk->rate = clk->parent->rate / clk->fixed_div;
135 if (clk->flags & RATE_PROPAGATES)
140 * omap2_wait_clock_ready - wait for clock to enable
141 * @reg: physical address of clock IDLEST register
142 * @mask: value to mask against to determine if the clock is active
143 * @name: name of the clock (for printk)
145 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
146 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
148 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
154 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
155 * 34xx reverses this, just to keep us on our toes
157 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
159 } else if (cpu_mask & RATE_IN_343X) {
164 while (((__raw_readl(reg) & mask) != ena) &&
165 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
169 if (i < MAX_CLOCK_ENABLE_WAIT)
170 pr_debug("Clock %s stable after %d loops\n", name, i);
172 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
173 name, MAX_CLOCK_ENABLE_WAIT);
176 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
181 * Note: We don't need special code here for INVERT_ENABLE
182 * for the time being since INVERT_ENABLE only applies to clocks enabled by
185 static void omap2_clk_wait_ready(struct clk *clk)
187 void __iomem *reg, *other_reg, *st_reg;
191 * REVISIT: This code is pretty ugly. It would be nice to generalize
192 * it and pull it into struct clk itself somehow.
194 reg = clk->enable_reg;
195 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
196 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
197 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
198 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
199 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
200 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
204 /* REVISIT: What are the appropriate exclusions for 34XX? */
205 /* No check for DSS or cam clocks */
206 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
207 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
208 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
209 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
213 /* REVISIT: What are the appropriate exclusions for 34XX? */
214 /* OMAP3: ignore DSS-mod clocks */
215 if (cpu_is_omap34xx() &&
216 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
219 /* Check if both functional and interface clocks
221 bit = 1 << clk->enable_bit;
222 if (!(__raw_readl(other_reg) & bit))
224 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
226 omap2_wait_clock_ready(st_reg, bit, clk->name);
229 /* Enables clock without considering parent dependencies or use count
230 * REVISIT: Maybe change this to use clk->enable like on omap1?
232 int _omap2_clk_enable(struct clk *clk)
236 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
240 return clk->enable(clk);
242 if (unlikely(clk->enable_reg == 0)) {
243 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
245 return 0; /* REVISIT: -EINVAL */
248 regval32 = __raw_readl(clk->enable_reg);
249 if (clk->flags & INVERT_ENABLE)
250 regval32 &= ~(1 << clk->enable_bit);
252 regval32 |= (1 << clk->enable_bit);
253 __raw_writel(regval32, clk->enable_reg);
256 omap2_clk_wait_ready(clk);
261 /* Disables clock without considering parent dependencies or use count */
262 void _omap2_clk_disable(struct clk *clk)
266 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
274 if (clk->enable_reg == 0) {
276 * 'Independent' here refers to a clock which is not
277 * controlled by its parent.
279 printk(KERN_ERR "clock: clk_disable called on independent "
280 "clock %s which has no enable_reg\n", clk->name);
284 regval32 = __raw_readl(clk->enable_reg);
285 if (clk->flags & INVERT_ENABLE)
286 regval32 |= (1 << clk->enable_bit);
288 regval32 &= ~(1 << clk->enable_bit);
289 __raw_writel(regval32, clk->enable_reg);
293 void omap2_clk_disable(struct clk *clk)
295 if (clk->usecount > 0 && !(--clk->usecount)) {
296 _omap2_clk_disable(clk);
297 if (likely((u32)clk->parent))
298 omap2_clk_disable(clk->parent);
302 int omap2_clk_enable(struct clk *clk)
306 if (clk->usecount++ == 0) {
307 if (likely((u32)clk->parent))
308 ret = omap2_clk_enable(clk->parent);
310 if (unlikely(ret != 0)) {
315 ret = _omap2_clk_enable(clk);
317 if (unlikely(ret != 0) && clk->parent) {
318 omap2_clk_disable(clk->parent);
327 * Used for clocks that are part of CLKSEL_xyz governed clocks.
328 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
330 void omap2_clksel_recalc(struct clk *clk)
334 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
336 div = omap2_clksel_get_divisor(clk);
340 if (unlikely(clk->rate == clk->parent->rate / div))
342 clk->rate = clk->parent->rate / div;
344 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
346 if (unlikely(clk->flags & RATE_PROPAGATES))
351 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
352 * @clk: OMAP struct clk ptr to inspect
353 * @src_clk: OMAP struct clk ptr of the parent clk to search for
355 * Scan the struct clksel array associated with the clock to find
356 * the element associated with the supplied parent clock address.
357 * Returns a pointer to the struct clksel on success or NULL on error.
359 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
362 const struct clksel *clks;
367 for (clks = clk->clksel; clks->parent; clks++) {
368 if (clks->parent == src_clk)
369 break; /* Found the requested parent */
373 printk(KERN_ERR "clock: Could not find parent clock %s in "
374 "clksel array of clock %s\n", src_clk->name,
383 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
384 * @clk: OMAP struct clk to use
385 * @target_rate: desired clock rate
386 * @new_div: ptr to where we should store the divisor
388 * Finds 'best' divider value in an array based on the source and target
389 * rates. The divider array must be sorted with smallest divider first.
390 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
391 * they are only settable as part of virtual_prcm set.
393 * Returns the rounded clock rate or returns 0xffffffff on error.
395 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
398 unsigned long test_rate;
399 const struct clksel *clks;
400 const struct clksel_rate *clkr;
403 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
404 clk->name, target_rate);
408 clks = omap2_get_clksel_by_parent(clk, clk->parent);
412 for (clkr = clks->rates; clkr->div; clkr++) {
413 if (!(clkr->flags & cpu_mask))
417 if (clkr->div <= last_div)
418 printk(KERN_ERR "clock: clksel_rate table not sorted "
419 "for clock %s", clk->name);
421 last_div = clkr->div;
423 test_rate = clk->parent->rate / clkr->div;
425 if (test_rate <= target_rate)
426 break; /* found it */
430 printk(KERN_ERR "clock: Could not find divisor for target "
431 "rate %ld for clock %s parent %s\n", target_rate,
432 clk->name, clk->parent->name);
436 *new_div = clkr->div;
438 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
439 (clk->parent->rate / clkr->div));
441 return (clk->parent->rate / clkr->div);
445 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
446 * @clk: OMAP struct clk to use
447 * @target_rate: desired clock rate
449 * Compatibility wrapper for OMAP clock framework
450 * Finds best target rate based on the source clock and possible dividers.
451 * rates. The divider array must be sorted with smallest divider first.
452 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
453 * they are only settable as part of virtual_prcm set.
455 * Returns the rounded clock rate or returns 0xffffffff on error.
457 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
461 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
465 /* Given a clock and a rate apply a clock specific rounding function */
466 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
468 if (clk->round_rate != 0)
469 return clk->round_rate(clk, rate);
471 if (clk->flags & RATE_FIXED)
472 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
473 "on fixed-rate clock %s\n", clk->name);
479 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
480 * @clk: OMAP struct clk to use
481 * @field_val: register field value to find
483 * Given a struct clk of a rate-selectable clksel clock, and a register field
484 * value to search for, find the corresponding clock divisor. The register
485 * field value should be pre-masked and shifted down so the LSB is at bit 0
486 * before calling. Returns 0 on error
488 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
490 const struct clksel *clks;
491 const struct clksel_rate *clkr;
493 clks = omap2_get_clksel_by_parent(clk, clk->parent);
497 for (clkr = clks->rates; clkr->div; clkr++) {
498 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
503 printk(KERN_ERR "clock: Could not find fieldval %d for "
504 "clock %s parent %s\n", field_val, clk->name,
513 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
514 * @clk: OMAP struct clk to use
515 * @div: integer divisor to search for
517 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
518 * find the corresponding register field value. The return register value is
519 * the value before left-shifting. Returns 0xffffffff on error
521 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
523 const struct clksel *clks;
524 const struct clksel_rate *clkr;
526 /* should never happen */
529 clks = omap2_get_clksel_by_parent(clk, clk->parent);
533 for (clkr = clks->rates; clkr->div; clkr++) {
534 if ((clkr->flags & cpu_mask) && (clkr->div == div))
539 printk(KERN_ERR "clock: Could not find divisor %d for "
540 "clock %s parent %s\n", div, clk->name,
549 * omap2_get_clksel - find clksel register addr & field mask for a clk
550 * @clk: struct clk to use
551 * @field_mask: ptr to u32 to store the register field mask
553 * Returns the address of the clksel register upon success or NULL on error.
555 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
557 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
560 *field_mask = clk->clksel_mask;
562 return clk->clksel_reg;
566 * omap2_clksel_get_divisor - get current divider applied to parent clock.
567 * @clk: OMAP struct clk to use.
569 * Returns the integer divisor upon success or 0 on error.
571 u32 omap2_clksel_get_divisor(struct clk *clk)
573 u32 field_mask, field_val;
574 void __iomem *div_addr;
576 div_addr = omap2_get_clksel(clk, &field_mask);
580 field_val = __raw_readl(div_addr) & field_mask;
581 field_val >>= __ffs(field_mask);
583 return omap2_clksel_to_divisor(clk, field_val);
586 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
588 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
589 void __iomem *div_addr;
591 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
592 if (validrate != rate)
595 div_addr = omap2_get_clksel(clk, &field_mask);
599 field_val = omap2_divisor_to_clksel(clk, new_div);
603 reg_val = __raw_readl(div_addr);
604 reg_val &= ~field_mask;
605 reg_val |= (field_val << __ffs(field_mask));
606 __raw_writel(reg_val, div_addr);
609 clk->rate = clk->parent->rate / new_div;
611 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
612 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
620 /* Set the clock rate for a clock source */
621 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
625 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
627 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
628 rate table mechanism, driven by mpu_speed */
629 if (clk->flags & CONFIG_PARTICIPANT)
632 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
633 if (clk->set_rate != 0)
634 ret = clk->set_rate(clk, rate);
636 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
643 * Converts encoded control register address into a full address
644 * On error, *src_addr will be returned as 0.
646 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
647 struct clk *src_clk, u32 *field_mask,
648 struct clk *clk, u32 *parent_div)
650 const struct clksel *clks;
651 const struct clksel_rate *clkr;
656 clks = omap2_get_clksel_by_parent(clk, src_clk);
660 for (clkr = clks->rates; clkr->div; clkr++) {
661 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
662 break; /* Found the default rate for this platform */
666 printk(KERN_ERR "clock: Could not find default rate for "
667 "clock %s parent %s\n", clk->name,
668 src_clk->parent->name);
672 /* Should never happen. Add a clksel mask to the struct clk. */
673 WARN_ON(clk->clksel_mask == 0);
675 *field_mask = clk->clksel_mask;
676 *src_addr = clk->clksel_reg;
677 *parent_div = clkr->div;
682 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
684 void __iomem *src_addr;
685 u32 field_val, field_mask, reg_val, parent_div;
687 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
693 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
694 &field_mask, clk, &parent_div);
698 if (clk->usecount > 0)
699 _omap2_clk_disable(clk);
701 /* Set new source value (previous dividers if any in effect) */
702 reg_val = __raw_readl(src_addr) & ~field_mask;
703 reg_val |= (field_val << __ffs(field_mask));
704 __raw_writel(reg_val, src_addr);
707 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
708 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
712 if (clk->usecount > 0)
713 _omap2_clk_enable(clk);
715 clk->parent = new_parent;
717 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
718 clk->rate = new_parent->rate;
721 clk->rate /= parent_div;
723 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
724 clk->name, clk->parent->name, clk->rate);
726 if (unlikely(clk->flags & RATE_PROPAGATES))
732 /*-------------------------------------------------------------------------
733 * Omap2 clock reset and init functions
734 *-------------------------------------------------------------------------*/
736 #ifdef CONFIG_OMAP_RESET_CLOCKS
737 void omap2_clk_disable_unused(struct clk *clk)
741 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
743 regval32 = __raw_readl(clk->enable_reg);
744 if ((regval32 & (1 << clk->enable_bit)) == v)
747 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
748 _omap2_clk_disable(clk);