1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
17 #define s2BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19 #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
33 #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34 #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
35 #define S2IO_BIT_RESET 1
36 #define S2IO_BIT_SET 2
37 #define CHECKBIT(value, nbit) (value & (1 << nbit))
39 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
40 #define MAX_FLICKER_TIME 60000 /* 60 Secs */
42 /* Maximum outstanding splits to be configured into xena. */
44 XENA_ONE_SPLIT_TRANSACTION = 0,
45 XENA_TWO_SPLIT_TRANSACTION = 1,
46 XENA_THREE_SPLIT_TRANSACTION = 2,
47 XENA_FOUR_SPLIT_TRANSACTION = 3,
48 XENA_EIGHT_SPLIT_TRANSACTION = 4,
49 XENA_TWELVE_SPLIT_TRANSACTION = 5,
50 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
51 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
53 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
55 /* OS concerned variables and constants */
56 #define WATCH_DOG_TIMEOUT 15*HZ
58 #define ALIGN_SIZE 127
59 #define PCIX_COMMAND_REGISTER 0x62
62 * Debug related variables.
64 /* different debug levels. */
71 /* Global variable that defines the present debug level of the driver. */
72 static int debug_level = ERR_DBG;
74 /* DEBUG message print. */
75 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
77 #ifndef DMA_ERROR_CODE
78 #define DMA_ERROR_CODE (~(dma_addr_t)0x0)
81 /* Protocol assist features of the NIC */
82 #define L3_CKSUM_OK 0xFFFF
83 #define L4_CKSUM_OK 0xFFFF
84 #define S2IO_JUMBO_SIZE 9600
86 /* Driver statistics maintained by driver */
88 unsigned long long single_ecc_errs;
89 unsigned long long double_ecc_errs;
90 unsigned long long parity_err_cnt;
91 unsigned long long serious_err_cnt;
92 unsigned long long soft_reset_cnt;
93 unsigned long long fifo_full_cnt;
94 unsigned long long ring_full_cnt[8];
96 unsigned long long clubbed_frms_cnt;
97 unsigned long long sending_both;
98 unsigned long long outof_sequence_pkts;
99 unsigned long long flush_max_pkts;
100 unsigned long long sum_avg_pkts_aggregated;
101 unsigned long long num_aggregations;
102 /* Other statistics */
103 unsigned long long mem_alloc_fail_cnt;
104 unsigned long long pci_map_fail_cnt;
105 unsigned long long watchdog_timer_cnt;
106 unsigned long long mem_allocated;
107 unsigned long long mem_freed;
108 unsigned long long link_up_cnt;
109 unsigned long long link_down_cnt;
110 unsigned long long link_up_time;
111 unsigned long long link_down_time;
113 /* Transfer Code statistics */
114 unsigned long long tx_buf_abort_cnt;
115 unsigned long long tx_desc_abort_cnt;
116 unsigned long long tx_parity_err_cnt;
117 unsigned long long tx_link_loss_cnt;
118 unsigned long long tx_list_proc_err_cnt;
120 unsigned long long rx_parity_err_cnt;
121 unsigned long long rx_abort_cnt;
122 unsigned long long rx_parity_abort_cnt;
123 unsigned long long rx_rda_fail_cnt;
124 unsigned long long rx_unkn_prot_cnt;
125 unsigned long long rx_fcs_err_cnt;
126 unsigned long long rx_buf_size_err_cnt;
127 unsigned long long rx_rxd_corrupt_cnt;
128 unsigned long long rx_unkn_err_cnt;
130 /* Error/alarm statistics*/
131 unsigned long long tda_err_cnt;
132 unsigned long long pfc_err_cnt;
133 unsigned long long pcc_err_cnt;
134 unsigned long long tti_err_cnt;
135 unsigned long long lso_err_cnt;
136 unsigned long long tpa_err_cnt;
137 unsigned long long sm_err_cnt;
138 unsigned long long mac_tmac_err_cnt;
139 unsigned long long mac_rmac_err_cnt;
140 unsigned long long xgxs_txgxs_err_cnt;
141 unsigned long long xgxs_rxgxs_err_cnt;
142 unsigned long long rc_err_cnt;
143 unsigned long long prc_pcix_err_cnt;
144 unsigned long long rpa_err_cnt;
145 unsigned long long rda_err_cnt;
146 unsigned long long rti_err_cnt;
147 unsigned long long mc_err_cnt;
151 /* Xpak releated alarm and warnings */
153 u64 alarm_transceiver_temp_high;
154 u64 alarm_transceiver_temp_low;
155 u64 alarm_laser_bias_current_high;
156 u64 alarm_laser_bias_current_low;
157 u64 alarm_laser_output_power_high;
158 u64 alarm_laser_output_power_low;
159 u64 warn_transceiver_temp_high;
160 u64 warn_transceiver_temp_low;
161 u64 warn_laser_bias_current_high;
162 u64 warn_laser_bias_current_low;
163 u64 warn_laser_output_power_high;
164 u64 warn_laser_output_power_low;
166 u32 xpak_timer_count;
170 /* The statistics block of Xena */
172 /* Tx MAC statistics counters. */
173 __le32 tmac_data_octets;
175 __le64 tmac_drop_frms;
176 __le32 tmac_bcst_frms;
177 __le32 tmac_mcst_frms;
178 __le64 tmac_pause_ctrl_frms;
179 __le32 tmac_ucst_frms;
180 __le32 tmac_ttl_octets;
181 __le32 tmac_any_err_frms;
182 __le32 tmac_nucst_frms;
183 __le64 tmac_ttl_less_fb_octets;
184 __le64 tmac_vld_ip_octets;
193 /* Rx MAC Statistics counters. */
194 __le32 rmac_data_octets;
195 __le32 rmac_vld_frms;
196 __le64 rmac_fcs_err_frms;
197 __le64 rmac_drop_frms;
198 __le32 rmac_vld_bcst_frms;
199 __le32 rmac_vld_mcst_frms;
200 __le32 rmac_out_rng_len_err_frms;
201 __le32 rmac_in_rng_len_err_frms;
202 __le64 rmac_long_frms;
203 __le64 rmac_pause_ctrl_frms;
204 __le64 rmac_unsup_ctrl_frms;
205 __le32 rmac_accepted_ucst_frms;
206 __le32 rmac_ttl_octets;
207 __le32 rmac_discarded_frms;
208 __le32 rmac_accepted_nucst_frms;
210 __le32 rmac_drop_events;
211 __le64 rmac_ttl_less_fb_octets;
212 __le64 rmac_ttl_frms;
214 __le32 rmac_usized_frms;
216 __le32 rmac_frag_frms;
217 __le32 rmac_osized_frms;
219 __le32 rmac_jabber_frms;
220 __le64 rmac_ttl_64_frms;
221 __le64 rmac_ttl_65_127_frms;
223 __le64 rmac_ttl_128_255_frms;
224 __le64 rmac_ttl_256_511_frms;
226 __le64 rmac_ttl_512_1023_frms;
227 __le64 rmac_ttl_1024_1518_frms;
230 __le64 rmac_ip_octets;
232 __le32 rmac_hdr_err_ip;
236 __le32 rmac_err_drp_udp;
238 __le64 rmac_xgmii_err_sym;
256 __le32 rmac_pause_cnt;
257 __le64 rmac_xgmii_data_err_cnt;
258 __le64 rmac_xgmii_ctrl_err_cnt;
260 __le32 rmac_accepted_ip;
262 /* PCI/PCI-X Read transaction statistics. */
263 __le32 new_rd_req_cnt;
266 __le32 new_rd_req_rtry_cnt;
268 /* PCI/PCI-X Write/Read transaction statistics. */
270 __le32 wr_rtry_rd_ack_cnt;
271 __le32 new_wr_req_rtry_cnt;
272 __le32 new_wr_req_cnt;
276 /* PCI/PCI-X Write / DMA Transaction statistics. */
278 __le32 rd_rtry_wr_ack_cnt;
286 /* Tx MAC statistics overflow counters. */
287 __le32 tmac_data_octets_oflow;
288 __le32 tmac_frms_oflow;
289 __le32 tmac_bcst_frms_oflow;
290 __le32 tmac_mcst_frms_oflow;
291 __le32 tmac_ucst_frms_oflow;
292 __le32 tmac_ttl_octets_oflow;
293 __le32 tmac_any_err_frms_oflow;
294 __le32 tmac_nucst_frms_oflow;
295 __le64 tmac_vlan_frms;
296 __le32 tmac_drop_ip_oflow;
297 __le32 tmac_vld_ip_oflow;
298 __le32 tmac_rst_tcp_oflow;
299 __le32 tmac_icmp_oflow;
300 __le32 tpa_unknown_protocol;
301 __le32 tmac_udp_oflow;
303 __le32 tpa_parse_failure;
305 /* Rx MAC Statistics overflow counters. */
306 __le32 rmac_data_octets_oflow;
307 __le32 rmac_vld_frms_oflow;
308 __le32 rmac_vld_bcst_frms_oflow;
309 __le32 rmac_vld_mcst_frms_oflow;
310 __le32 rmac_accepted_ucst_frms_oflow;
311 __le32 rmac_ttl_octets_oflow;
312 __le32 rmac_discarded_frms_oflow;
313 __le32 rmac_accepted_nucst_frms_oflow;
314 __le32 rmac_usized_frms_oflow;
315 __le32 rmac_drop_events_oflow;
316 __le32 rmac_frag_frms_oflow;
317 __le32 rmac_osized_frms_oflow;
318 __le32 rmac_ip_oflow;
319 __le32 rmac_jabber_frms_oflow;
320 __le32 rmac_icmp_oflow;
321 __le32 rmac_drop_ip_oflow;
322 __le32 rmac_err_drp_udp_oflow;
323 __le32 rmac_udp_oflow;
325 __le32 rmac_pause_cnt_oflow;
326 __le64 rmac_ttl_1519_4095_frms;
327 __le64 rmac_ttl_4096_8191_frms;
328 __le64 rmac_ttl_8192_max_frms;
329 __le64 rmac_ttl_gt_max_frms;
330 __le64 rmac_osized_alt_frms;
331 __le64 rmac_jabber_alt_frms;
332 __le64 rmac_gt_max_alt_frms;
333 __le64 rmac_vlan_frms;
334 __le32 rmac_len_discard;
335 __le32 rmac_fcs_discard;
336 __le32 rmac_pf_discard;
337 __le32 rmac_da_discard;
338 __le32 rmac_red_discard;
339 __le32 rmac_rts_discard;
341 __le32 rmac_ingm_full_discard;
343 __le32 rmac_accepted_ip_oflow;
345 __le32 link_fault_cnt;
347 struct swStat sw_stat;
348 struct xpakStat xpak_stat;
351 /* Default value for 'vlan_strip_tag' configuration parameter */
352 #define NO_STRIP_IN_PROMISC 2
355 * Structures representing different init time configuration
356 * parameters of the NIC.
359 #define MAX_TX_FIFOS 8
360 #define MAX_RX_RINGS 8
362 #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
363 #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
364 #define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
365 #define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
367 /* FIFO mappings for all possible number of fifos configured */
368 static int fifo_map[][MAX_TX_FIFOS] = {
369 {0, 0, 0, 0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 1, 1, 1, 1},
371 {0, 0, 0, 1, 1, 1, 2, 2},
372 {0, 0, 1, 1, 2, 2, 3, 3},
373 {0, 0, 1, 1, 2, 2, 3, 4},
374 {0, 0, 1, 1, 2, 3, 4, 5},
375 {0, 0, 1, 2, 3, 4, 5, 6},
376 {0, 1, 2, 3, 4, 5, 6, 7},
379 /* Maintains Per FIFO related information. */
380 struct tx_fifo_config {
381 #define MAX_AVAILABLE_TXDS 8192
382 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
383 /* Priority definition */
384 #define TX_FIFO_PRI_0 0 /*Highest */
385 #define TX_FIFO_PRI_1 1
386 #define TX_FIFO_PRI_2 2
387 #define TX_FIFO_PRI_3 3
388 #define TX_FIFO_PRI_4 4
389 #define TX_FIFO_PRI_5 5
390 #define TX_FIFO_PRI_6 6
391 #define TX_FIFO_PRI_7 7 /*lowest */
392 u8 fifo_priority; /* specifies pointer level for FIFO */
393 /* user should not set twos fifos with same pri */
395 #define NO_SNOOP_TXD 0x01
396 #define NO_SNOOP_TXD_BUFFER 0x02
400 /* Maintains per Ring related information */
401 struct rx_ring_config {
402 u32 num_rxd; /*No of RxDs per Rx Ring */
403 #define RX_RING_PRI_0 0 /* highest */
404 #define RX_RING_PRI_1 1
405 #define RX_RING_PRI_2 2
406 #define RX_RING_PRI_3 3
407 #define RX_RING_PRI_4 4
408 #define RX_RING_PRI_5 5
409 #define RX_RING_PRI_6 6
410 #define RX_RING_PRI_7 7 /* lowest */
412 u8 ring_priority; /*Specifies service priority of ring */
413 /* OSM should not set any two rings with same priority */
414 u8 ring_org; /*Organization of ring */
415 #define RING_ORG_BUFF1 0x01
416 #define RX_RING_ORG_BUFF3 0x03
417 #define RX_RING_ORG_BUFF5 0x05
420 #define NO_SNOOP_RXD 0x01
421 #define NO_SNOOP_RXD_BUFFER 0x02
424 /* This structure provides contains values of the tunable parameters
427 struct config_param {
429 u32 tx_fifo_num; /*Number of Tx FIFOs */
431 u8 fifo_mapping[MAX_TX_FIFOS];
432 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
433 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
440 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
443 u32 rx_ring_num; /*Number of receive rings */
444 #define MAX_RX_BLOCKS_PER_RING 150
446 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
448 #define HEADER_ETHERNET_II_802_3_SIZE 14
449 #define HEADER_802_2_SIZE 3
450 #define HEADER_SNAP_SIZE 5
451 #define HEADER_VLAN_SIZE 4
454 #define MAX_PYLD 1500
455 #define MAX_MTU (MAX_PYLD+18)
456 #define MAX_MTU_VLAN (MAX_PYLD+22)
457 #define MAX_PYLD_JUMBO 9600
458 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
459 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
463 /* Structure representing MAC Addrs */
465 u8 mac_addr[ETH_ALEN];
468 /* Structure that represent every FIFO element in the BAR1
471 struct TxFIFO_element {
475 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
476 #define TX_FIFO_FIRST_LIST s2BIT(14)
477 #define TX_FIFO_LAST_LIST s2BIT(15)
478 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
479 #define TX_FIFO_SPECIAL_FUNC s2BIT(23)
480 #define TX_FIFO_DS_NO_SNOOP s2BIT(31)
481 #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
484 /* Tx descriptor structure */
488 #define TXD_LIST_OWN_XENA s2BIT(7)
489 #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
490 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
491 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
492 #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
493 #define TXD_GATHER_CODE_FIRST s2BIT(22)
494 #define TXD_GATHER_CODE_LAST s2BIT(23)
495 #define TXD_TCP_LSO_EN s2BIT(30)
496 #define TXD_UDP_COF_EN s2BIT(31)
497 #define TXD_UFO_EN s2BIT(31) | s2BIT(30)
498 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
499 #define TXD_UFO_MSS(val) vBIT(val,34,14)
500 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
503 #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
504 #define TXD_TX_CKO_IPV4_EN s2BIT(5)
505 #define TXD_TX_CKO_TCP_EN s2BIT(6)
506 #define TXD_TX_CKO_UDP_EN s2BIT(7)
507 #define TXD_VLAN_ENABLE s2BIT(15)
508 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
509 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
510 #define TXD_INT_TYPE_PER_LIST s2BIT(47)
511 #define TXD_INT_TYPE_UTILZ s2BIT(46)
512 #define TXD_SET_MARKER vBIT(0x6,0,4)
515 u64 Host_Control; /* reserved for host */
518 /* Structure to hold the phy and virt addr of every TxDL. */
519 struct list_info_hold {
520 dma_addr_t list_phy_addr;
521 void *list_virt_addr;
524 /* Rx descriptor structure for 1 buffer mode */
526 u64 Host_Control; /* reserved for host */
528 #define RXD_OWN_XENA s2BIT(7)
529 #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
530 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
531 #define RXD_FRAME_PROTO_IPV4 s2BIT(27)
532 #define RXD_FRAME_PROTO_IPV6 s2BIT(28)
533 #define RXD_FRAME_IP_FRAG s2BIT(29)
534 #define RXD_FRAME_PROTO_TCP s2BIT(30)
535 #define RXD_FRAME_PROTO_UDP s2BIT(31)
536 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
537 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
538 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
541 #define THE_RXD_MARK 0x3
542 #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
543 #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
545 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
546 #define SET_VLAN_TAG(val) vBIT(val,48,16)
547 #define SET_NUM_TAG(val) vBIT(val,16,32)
551 /* Rx descriptor structure for 1 buffer mode */
555 #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
556 #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
557 #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
558 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
561 /* Rx descriptor structure for 3 or 2 buffer mode */
566 #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
567 #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
568 #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
569 #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
570 #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
571 #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
572 #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
573 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
574 #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
575 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
576 #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
577 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
587 /* Structure that represents the Rx descriptor block which contains
588 * 128 Rx descriptors.
591 #define MAX_RXDS_PER_BLOCK_1 127
592 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
595 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
596 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
598 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
599 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
600 * the upper 32 bits should
604 #define SIZE_OF_BLOCK 4096
606 #define RXD_MODE_1 0 /* One Buffer mode */
607 #define RXD_MODE_3B 1 /* Two Buffer mode */
609 /* Structure to hold virtual addresses of Buf0 and Buf1 in
618 /* Structure which stores all the MAC control parameters */
620 /* This structure stores the offset of the RxD in the ring
621 * from which the Rx Interrupt processor can start picking
622 * up the RxDs for processing.
624 struct rx_curr_get_info {
630 struct rx_curr_put_info {
636 /* This structure stores the offset of the TxDl in the FIFO
637 * from which the Tx Interrupt processor can start picking
638 * up the TxDLs for send complete interrupt processing.
640 struct tx_curr_get_info {
645 struct tx_curr_put_info {
655 /* Structure that holds the Phy and virt addresses of the Blocks */
656 struct rx_block_info {
657 void *block_virt_addr;
658 dma_addr_t block_dma_addr;
659 struct rxd_info *rxds;
662 /* Ring specific structure */
664 /* The ring number */
668 * Place holders for the virtual and physical addresses of
671 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
676 * Put pointer info which indictes which RxD has to be replenished
679 struct rx_curr_put_info rx_curr_put_info;
682 * Get pointer info which indictes which is the last RxD that was
683 * processed by the driver.
685 struct rx_curr_get_info rx_curr_get_info;
687 /* Index to the absolute position of the put pointer of Rx ring */
690 /* Buffer Address store. */
692 struct s2io_nic *nic;
695 /* Fifo specific structure */
700 /* Maximum TxDs per TxDL */
703 /* Place holder of all the TX List's Phy and Virt addresses. */
704 struct list_info_hold *list_info;
707 * Current offset within the tx FIFO where driver would write
710 struct tx_curr_put_info tx_curr_put_info;
713 * Current offset within tx FIFO from where the driver would start freeing
716 struct tx_curr_get_info tx_curr_get_info;
718 struct s2io_nic *nic;
721 /* Information related to the Tx and Rx FIFOs and Rings of Xena
722 * is maintained in this structure.
726 /* logical pointer of start of each Tx FIFO */
727 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
729 /* Fifo specific structure */
730 struct fifo_info fifos[MAX_TX_FIFOS];
732 /* Save virtual address of TxD page with zero DMA addr(if any) */
733 void *zerodma_virt_addr;
736 /* Ring specific structure */
737 struct ring_info rings[MAX_RX_RINGS];
740 u16 mc_pause_threshold_q0q3;
741 u16 mc_pause_threshold_q4q7;
743 void *stats_mem; /* orignal pointer to allocated mem */
744 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
746 struct stat_block *stats_info; /* Logical address of the stat block */
749 /* structure representing the user defined MAC addresses */
755 /* Default Tunable parameters of the NIC. */
756 #define DEFAULT_FIFO_0_LEN 4096
757 #define DEFAULT_FIFO_1_7_LEN 512
758 #define SMALL_BLK_CNT 30
759 #define LARGE_BLK_CNT 100
762 * Structure to keep track of the MSI-X vectors and the corresponding
763 * argument registered against each vector
765 #define MAX_REQUESTED_MSI_X 17
766 struct s2io_msix_entry
773 #define MSIX_FIFO_TYPE 1
774 #define MSIX_RING_TYPE 2
777 #define MSIX_REGISTERED_SUCCESS 0xAA
780 struct msix_info_st {
785 /* Data structure to represent a LRO session */
787 struct sk_buff *parent;
788 struct sk_buff *last_frag;
804 /* These flags represent the devices temporary state */
805 enum s2io_device_state_t
807 __S2IO_STATE_LINK_TASK=0,
811 /* Structure representing one instance of the NIC */
815 * Count of packets to be processed in a given iteration, it will be indicated
816 * by the quota field of the device structure when NAPI is enabled.
819 struct net_device *dev;
820 struct napi_struct napi;
821 struct mac_info mac_control;
822 struct config_param config;
823 struct pci_dev *pdev;
826 #define MAX_MAC_SUPPORTED 16
827 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
829 struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
831 struct net_device_stats stats;
833 int device_enabled_once;
836 struct tasklet_struct task;
837 volatile unsigned long tasklet_status;
839 /* Timer that handles I/O errors/exceptions */
840 struct timer_list alarm_timer;
842 /* Space to back up the PCI config space */
843 u32 config_space[256 / sizeof(u32)];
845 atomic_t rx_bufs_left[MAX_RX_RINGS];
853 #define MAX_ADDRS_SUPPORTED 64
856 struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
862 /* Id timer, used to blink NIC to physically identify NIC. */
863 struct timer_list id_timer;
865 /* Restart timer, used to restart NIC if the device is stuck and
866 * a schedule task that will set the correct Link state once the
867 * NIC's PHY has stabilized after a state change.
869 struct work_struct rst_timer_task;
870 struct work_struct set_link_task;
872 /* Flag that can be used to turn on or turn off the Rx checksum
877 /* after blink, the adapter must be restored with original
882 /* Last known link state. */
888 unsigned long long start_time;
889 struct vlan_group *vlgrp;
890 #define MSIX_FLG 0xA5
891 struct msix_entry *entries;
893 wait_queue_head_t msi_wait;
894 struct s2io_msix_entry *s2io_entries;
895 char desc[MAX_REQUESTED_MSI_X][25];
897 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
899 struct msix_info_st msix_info[0x3f];
901 #define XFRAME_I_DEVICE 1
902 #define XFRAME_II_DEVICE 2
905 #define MAX_LRO_SESSIONS 32
906 struct lro lro0_n[MAX_LRO_SESSIONS];
907 unsigned long clubbed_frms_cnt;
908 unsigned long sending_both;
910 u16 lro_max_aggr_per_sess;
911 volatile unsigned long state;
913 u64 general_int_mask;
915 #define VPD_STRING_LEN 80
916 u8 product_name[VPD_STRING_LEN];
917 u8 serial_num[VPD_STRING_LEN];
920 #define RESET_ERROR 1;
923 /* OS related system calls */
925 static inline u64 readq(void __iomem *addr)
928 ret = readl(addr + 4);
937 static inline void writeq(u64 val, void __iomem *addr)
939 writel((u32) (val), addr);
940 writel((u32) (val >> 32), (addr + 4));
945 * Some registers have to be written in a particular order to
946 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
947 * is used to perform such ordered writes. Defines UF (Upper First)
948 * and LF (Lower First) will be used to specify the required write order.
952 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
957 writel((u32) (val), addr);
959 writel((u32) (val >> 32), (addr + 4));
960 ret = readl(addr + 4);
962 writel((u32) (val >> 32), (addr + 4));
963 ret = readl(addr + 4);
964 writel((u32) (val), addr);
969 /* Interrupt related values of Xena */
971 #define ENABLE_INTRS 1
972 #define DISABLE_INTRS 2
974 /* Highest level interrupt blocks */
975 #define TX_PIC_INTR (0x0001<<0)
976 #define TX_DMA_INTR (0x0001<<1)
977 #define TX_MAC_INTR (0x0001<<2)
978 #define TX_XGXS_INTR (0x0001<<3)
979 #define TX_TRAFFIC_INTR (0x0001<<4)
980 #define RX_PIC_INTR (0x0001<<5)
981 #define RX_DMA_INTR (0x0001<<6)
982 #define RX_MAC_INTR (0x0001<<7)
983 #define RX_XGXS_INTR (0x0001<<8)
984 #define RX_TRAFFIC_INTR (0x0001<<9)
985 #define MC_INTR (0x0001<<10)
986 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
998 /* Interrupt masks for the general interrupt mask register */
999 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1001 #define TXPIC_INT_M s2BIT(0)
1002 #define TXDMA_INT_M s2BIT(1)
1003 #define TXMAC_INT_M s2BIT(2)
1004 #define TXXGXS_INT_M s2BIT(3)
1005 #define TXTRAFFIC_INT_M s2BIT(8)
1006 #define PIC_RX_INT_M s2BIT(32)
1007 #define RXDMA_INT_M s2BIT(33)
1008 #define RXMAC_INT_M s2BIT(34)
1009 #define MC_INT_M s2BIT(35)
1010 #define RXXGXS_INT_M s2BIT(36)
1011 #define RXTRAFFIC_INT_M s2BIT(40)
1013 /* PIC level Interrupts TODO*/
1015 /* DMA level Inressupts */
1016 #define TXDMA_PFC_INT_M s2BIT(0)
1017 #define TXDMA_PCC_INT_M s2BIT(2)
1019 /* PFC block interrupts */
1020 #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1022 /* PCC block interrupts. */
1023 #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1024 PCC_FB_ECC Error. */
1026 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1028 * Prototype declaration.
1030 static int __devinit s2io_init_nic(struct pci_dev *pdev,
1031 const struct pci_device_id *pre);
1032 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1033 static int init_shared_mem(struct s2io_nic *sp);
1034 static void free_shared_mem(struct s2io_nic *sp);
1035 static int init_nic(struct s2io_nic *nic);
1036 static void rx_intr_handler(struct ring_info *ring_data);
1037 static void tx_intr_handler(struct fifo_info *fifo_data);
1038 static void s2io_handle_errors(void * dev_id);
1040 static int s2io_starter(void);
1041 static void s2io_closer(void);
1042 static void s2io_tx_watchdog(struct net_device *dev);
1043 static void s2io_tasklet(unsigned long dev_addr);
1044 static void s2io_set_multicast(struct net_device *dev);
1045 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1046 static void s2io_link(struct s2io_nic * sp, int link);
1047 static void s2io_reset(struct s2io_nic * sp);
1048 static int s2io_poll(struct napi_struct *napi, int budget);
1049 static void s2io_init_pci(struct s2io_nic * sp);
1050 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
1051 static void s2io_alarm_handle(unsigned long data);
1053 s2io_msix_ring_handle(int irq, void *dev_id);
1055 s2io_msix_fifo_handle(int irq, void *dev_id);
1056 static irqreturn_t s2io_isr(int irq, void *dev_id);
1057 static int verify_xena_quiescence(struct s2io_nic *sp);
1058 static const struct ethtool_ops netdev_ethtool_ops;
1059 static void s2io_set_link(struct work_struct *work);
1060 static int s2io_set_swapper(struct s2io_nic * sp);
1061 static void s2io_card_down(struct s2io_nic *nic);
1062 static int s2io_card_up(struct s2io_nic *nic);
1063 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1065 static int s2io_add_isr(struct s2io_nic * sp);
1066 static void s2io_rem_isr(struct s2io_nic * sp);
1068 static void restore_xmsi_data(struct s2io_nic *nic);
1071 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1072 struct RxD_t *rxdp, struct s2io_nic *sp);
1073 static void clear_lro_session(struct lro *lro);
1074 static void queue_rx_frame(struct sk_buff *skb);
1075 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1076 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1077 struct sk_buff *skb, u32 tcp_len);
1078 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1080 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1081 pci_channel_state_t state);
1082 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1083 static void s2io_io_resume(struct pci_dev *pdev);
1085 #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1086 #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1087 #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1089 #define S2IO_PARM_INT(X, def_val) \
1090 static unsigned int X = def_val;\
1091 module_param(X , uint, 0);
1093 #endif /* _S2IO_H */