2 * IPIC private definitions and structure.
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2005 Freescale Semiconductor, Inc
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
18 #define NR_IPIC_INTS 128
21 #define IPIC_IRQ_EXT0 48
22 #define IPIC_IRQ_EXT1 17
23 #define IPIC_IRQ_EXT7 23
25 /* Default Priority Registers */
26 #define IPIC_SIPRR_A_DEFAULT 0x05309770
27 #define IPIC_SIPRR_D_DEFAULT 0x05309770
28 #define IPIC_SMPRR_A_DEFAULT 0x05309770
29 #define IPIC_SMPRR_B_DEFAULT 0x05309770
31 /* System Global Interrupt Configuration Register */
32 #define SICFR_IPSA 0x00010000
33 #define SICFR_IPSD 0x00080000
34 #define SICFR_MPSA 0x00200000
35 #define SICFR_MPSB 0x00400000
37 /* System External Interrupt Mask Register */
38 #define SEMSR_SIRQ0 0x00008000
40 /* System Error Control Register */
41 #define SERCR_MCPR 0x00000001
44 volatile u32 __iomem *regs;
46 /* The remapper for this IPIC */
47 struct irq_host *irqhost;
49 /* The "linux" controller struct */
50 struct irq_chip hc_irq;
52 /* The device node of the interrupt controller */
53 struct device_node *of_node;
57 u8 pend; /* pending register offset from base */
58 u8 mask; /* mask register offset from base */
59 u8 prio; /* priority register offset from base */
60 u8 force; /* force register offset from base */
61 u8 bit; /* register bit position (as per doc)
62 bit mask = 1 << (31 - bit) */
63 u8 prio_mask; /* priority mask value */
66 #endif /* __IPIC_H__ */