Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 #define MAX_NOPID ((u32)~0)
35
36 /**
37  * Interrupts that are always left unmasked.
38  *
39  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
40  * we leave them always unmasked in IMR and then control enabling them through
41  * PIPESTAT alone.
42  */
43 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
44                                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |  \
45                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
46
47 /** Interrupts that we mask and unmask at runtime. */
48 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
49
50 /** These are all of the interrupts used by the driver */
51 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
52                                     I915_INTERRUPT_ENABLE_VAR)
53
54 void
55 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
56 {
57         if ((dev_priv->irq_mask_reg & mask) != 0) {
58                 dev_priv->irq_mask_reg &= ~mask;
59                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
60                 (void) I915_READ(IMR);
61         }
62 }
63
64 static inline void
65 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
66 {
67         if ((dev_priv->irq_mask_reg & mask) != mask) {
68                 dev_priv->irq_mask_reg |= mask;
69                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
70                 (void) I915_READ(IMR);
71         }
72 }
73
74 static inline u32
75 i915_pipestat(int pipe)
76 {
77         if (pipe == 0)
78                 return PIPEASTAT;
79         if (pipe == 1)
80                 return PIPEBSTAT;
81         BUG_ON(1);
82 }
83
84 void
85 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
86 {
87         if ((dev_priv->pipestat[pipe] & mask) != mask) {
88                 u32 reg = i915_pipestat(pipe);
89
90                 dev_priv->pipestat[pipe] |= mask;
91                 /* Enable the interrupt, clear any pending status */
92                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
93                 (void) I915_READ(reg);
94         }
95 }
96
97 void
98 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
99 {
100         if ((dev_priv->pipestat[pipe] & mask) != 0) {
101                 u32 reg = i915_pipestat(pipe);
102
103                 dev_priv->pipestat[pipe] &= ~mask;
104                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
105                 (void) I915_READ(reg);
106         }
107 }
108
109 /**
110  * i915_pipe_enabled - check if a pipe is enabled
111  * @dev: DRM device
112  * @pipe: pipe to check
113  *
114  * Reading certain registers when the pipe is disabled can hang the chip.
115  * Use this routine to make sure the PLL is running and the pipe is active
116  * before reading such registers if unsure.
117  */
118 static int
119 i915_pipe_enabled(struct drm_device *dev, int pipe)
120 {
121         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
122         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
123
124         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
125                 return 1;
126
127         return 0;
128 }
129
130 /* Called from drm generic code, passed a 'crtc', which
131  * we use as a pipe index
132  */
133 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
134 {
135         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
136         unsigned long high_frame;
137         unsigned long low_frame;
138         u32 high1, high2, low, count;
139
140         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
141         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
142
143         if (!i915_pipe_enabled(dev, pipe)) {
144                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
145                 return 0;
146         }
147
148         /*
149          * High & low register fields aren't synchronized, so make sure
150          * we get a low value that's stable across two reads of the high
151          * register.
152          */
153         do {
154                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
155                          PIPE_FRAME_HIGH_SHIFT);
156                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
157                         PIPE_FRAME_LOW_SHIFT);
158                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
159                          PIPE_FRAME_HIGH_SHIFT);
160         } while (high1 != high2);
161
162         count = (high1 << 8) | low;
163
164         return count;
165 }
166
167 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
168 {
169         struct drm_device *dev = (struct drm_device *) arg;
170         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171         u32 iir, new_iir;
172         u32 pipea_stats, pipeb_stats;
173         u32 vblank_status;
174         u32 vblank_enable;
175         int vblank = 0;
176         unsigned long irqflags;
177         int irq_received;
178         int ret = IRQ_NONE;
179
180         atomic_inc(&dev_priv->irq_received);
181
182         iir = I915_READ(IIR);
183
184         if (IS_I965G(dev)) {
185                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
186                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
187         } else {
188                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
189                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
190         }
191
192         for (;;) {
193                 irq_received = iir != 0;
194
195                 /* Can't rely on pipestat interrupt bit in iir as it might
196                  * have been cleared after the pipestat interrupt was received.
197                  * It doesn't set the bit in iir again, but it still produces
198                  * interrupts (for non-MSI).
199                  */
200                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
201                 pipea_stats = I915_READ(PIPEASTAT);
202                 pipeb_stats = I915_READ(PIPEBSTAT);
203                 /*
204                  * Clear the PIPE(A|B)STAT regs before the IIR
205                  */
206                 if (pipea_stats & 0x8000ffff) {
207                         I915_WRITE(PIPEASTAT, pipea_stats);
208                         irq_received = 1;
209                 }
210
211                 if (pipeb_stats & 0x8000ffff) {
212                         I915_WRITE(PIPEBSTAT, pipeb_stats);
213                         irq_received = 1;
214                 }
215                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
216
217                 if (!irq_received)
218                         break;
219
220                 ret = IRQ_HANDLED;
221
222                 I915_WRITE(IIR, iir);
223                 new_iir = I915_READ(IIR); /* Flush posted writes */
224
225                 if (dev_priv->sarea_priv)
226                         dev_priv->sarea_priv->last_dispatch =
227                                 READ_BREADCRUMB(dev_priv);
228
229                 if (iir & I915_USER_INTERRUPT) {
230                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
231                         DRM_WAKEUP(&dev_priv->irq_queue);
232                 }
233
234                 if (pipea_stats & vblank_status) {
235                         vblank++;
236                         drm_handle_vblank(dev, 0);
237                 }
238
239                 if (pipeb_stats & vblank_status) {
240                         vblank++;
241                         drm_handle_vblank(dev, 1);
242                 }
243
244                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
245                     (iir & I915_ASLE_INTERRUPT))
246                         opregion_asle_intr(dev);
247
248                 /* With MSI, interrupts are only generated when iir
249                  * transitions from zero to nonzero.  If another bit got
250                  * set while we were handling the existing iir bits, then
251                  * we would never get another interrupt.
252                  *
253                  * This is fine on non-MSI as well, as if we hit this path
254                  * we avoid exiting the interrupt handler only to generate
255                  * another one.
256                  *
257                  * Note that for MSI this could cause a stray interrupt report
258                  * if an interrupt landed in the time between writing IIR and
259                  * the posting read.  This should be rare enough to never
260                  * trigger the 99% of 100,000 interrupts test for disabling
261                  * stray interrupts.
262                  */
263                 iir = new_iir;
264         }
265
266         return ret;
267 }
268
269 static int i915_emit_irq(struct drm_device * dev)
270 {
271         drm_i915_private_t *dev_priv = dev->dev_private;
272         RING_LOCALS;
273
274         i915_kernel_lost_context(dev);
275
276         DRM_DEBUG("\n");
277
278         dev_priv->counter++;
279         if (dev_priv->counter > 0x7FFFFFFFUL)
280                 dev_priv->counter = 1;
281         if (dev_priv->sarea_priv)
282                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
283
284         BEGIN_LP_RING(4);
285         OUT_RING(MI_STORE_DWORD_INDEX);
286         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
287         OUT_RING(dev_priv->counter);
288         OUT_RING(MI_USER_INTERRUPT);
289         ADVANCE_LP_RING();
290
291         return dev_priv->counter;
292 }
293
294 void i915_user_irq_get(struct drm_device *dev)
295 {
296         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
297         unsigned long irqflags;
298
299         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
300         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
301                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
302         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
303 }
304
305 void i915_user_irq_put(struct drm_device *dev)
306 {
307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
308         unsigned long irqflags;
309
310         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
311         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
312         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
313                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
314         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
315 }
316
317 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
318 {
319         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
320         int ret = 0;
321
322         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
323                   READ_BREADCRUMB(dev_priv));
324
325         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
326                 if (dev_priv->sarea_priv) {
327                         dev_priv->sarea_priv->last_dispatch =
328                                 READ_BREADCRUMB(dev_priv);
329                 }
330                 return 0;
331         }
332
333         if (dev_priv->sarea_priv)
334                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
335
336         i915_user_irq_get(dev);
337         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
338                     READ_BREADCRUMB(dev_priv) >= irq_nr);
339         i915_user_irq_put(dev);
340
341         if (ret == -EBUSY) {
342                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
343                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
344         }
345
346         if (dev_priv->sarea_priv)
347                 dev_priv->sarea_priv->last_dispatch =
348                         READ_BREADCRUMB(dev_priv);
349
350         return ret;
351 }
352
353 /* Needs the lock as it touches the ring.
354  */
355 int i915_irq_emit(struct drm_device *dev, void *data,
356                          struct drm_file *file_priv)
357 {
358         drm_i915_private_t *dev_priv = dev->dev_private;
359         drm_i915_irq_emit_t *emit = data;
360         int result;
361
362         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
363
364         if (!dev_priv) {
365                 DRM_ERROR("called with no initialization\n");
366                 return -EINVAL;
367         }
368         mutex_lock(&dev->struct_mutex);
369         result = i915_emit_irq(dev);
370         mutex_unlock(&dev->struct_mutex);
371
372         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
373                 DRM_ERROR("copy_to_user\n");
374                 return -EFAULT;
375         }
376
377         return 0;
378 }
379
380 /* Doesn't need the hardware lock.
381  */
382 int i915_irq_wait(struct drm_device *dev, void *data,
383                          struct drm_file *file_priv)
384 {
385         drm_i915_private_t *dev_priv = dev->dev_private;
386         drm_i915_irq_wait_t *irqwait = data;
387
388         if (!dev_priv) {
389                 DRM_ERROR("called with no initialization\n");
390                 return -EINVAL;
391         }
392
393         return i915_wait_irq(dev, irqwait->irq_seq);
394 }
395
396 /* Called from drm generic code, passed 'crtc' which
397  * we use as a pipe index
398  */
399 int i915_enable_vblank(struct drm_device *dev, int pipe)
400 {
401         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
402         unsigned long irqflags;
403
404         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
405         if (IS_I965G(dev))
406                 i915_enable_pipestat(dev_priv, pipe,
407                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
408         else
409                 i915_enable_pipestat(dev_priv, pipe,
410                                      PIPE_VBLANK_INTERRUPT_ENABLE);
411         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
412         return 0;
413 }
414
415 /* Called from drm generic code, passed 'crtc' which
416  * we use as a pipe index
417  */
418 void i915_disable_vblank(struct drm_device *dev, int pipe)
419 {
420         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
421         unsigned long irqflags;
422
423         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
424         i915_disable_pipestat(dev_priv, pipe,
425                               PIPE_VBLANK_INTERRUPT_ENABLE |
426                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
427         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
428 }
429
430 /* Set the vblank monitor pipe
431  */
432 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
433                          struct drm_file *file_priv)
434 {
435         drm_i915_private_t *dev_priv = dev->dev_private;
436
437         if (!dev_priv) {
438                 DRM_ERROR("called with no initialization\n");
439                 return -EINVAL;
440         }
441
442         return 0;
443 }
444
445 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
446                          struct drm_file *file_priv)
447 {
448         drm_i915_private_t *dev_priv = dev->dev_private;
449         drm_i915_vblank_pipe_t *pipe = data;
450
451         if (!dev_priv) {
452                 DRM_ERROR("called with no initialization\n");
453                 return -EINVAL;
454         }
455
456         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
457
458         return 0;
459 }
460
461 /**
462  * Schedule buffer swap at given vertical blank.
463  */
464 int i915_vblank_swap(struct drm_device *dev, void *data,
465                      struct drm_file *file_priv)
466 {
467         /* The delayed swap mechanism was fundamentally racy, and has been
468          * removed.  The model was that the client requested a delayed flip/swap
469          * from the kernel, then waited for vblank before continuing to perform
470          * rendering.  The problem was that the kernel might wake the client
471          * up before it dispatched the vblank swap (since the lock has to be
472          * held while touching the ringbuffer), in which case the client would
473          * clear and start the next frame before the swap occurred, and
474          * flicker would occur in addition to likely missing the vblank.
475          *
476          * In the absence of this ioctl, userland falls back to a correct path
477          * of waiting for a vblank, then dispatching the swap on its own.
478          * Context switching to userland and back is plenty fast enough for
479          * meeting the requirements of vblank swapping.
480          */
481         return -EINVAL;
482 }
483
484 /* drm_dma.h hooks
485 */
486 void i915_driver_irq_preinstall(struct drm_device * dev)
487 {
488         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
489
490         I915_WRITE(HWSTAM, 0xeffe);
491         I915_WRITE(PIPEASTAT, 0);
492         I915_WRITE(PIPEBSTAT, 0);
493         I915_WRITE(IMR, 0xffffffff);
494         I915_WRITE(IER, 0x0);
495         (void) I915_READ(IER);
496 }
497
498 int i915_driver_irq_postinstall(struct drm_device *dev)
499 {
500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
501
502         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
503
504         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
505
506         /* Unmask the interrupts that we always want on. */
507         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
508
509         dev_priv->pipestat[0] = 0;
510         dev_priv->pipestat[1] = 0;
511
512         /* Disable pipe interrupt enables, clear pending pipe status */
513         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
514         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
515         /* Clear pending interrupt status */
516         I915_WRITE(IIR, I915_READ(IIR));
517
518         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
519         I915_WRITE(IMR, dev_priv->irq_mask_reg);
520         (void) I915_READ(IER);
521
522         opregion_enable_asle(dev);
523         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
524
525         return 0;
526 }
527
528 void i915_driver_irq_uninstall(struct drm_device * dev)
529 {
530         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
531
532         if (!dev_priv)
533                 return;
534
535         dev_priv->vblank_pipe = 0;
536
537         I915_WRITE(HWSTAM, 0xffffffff);
538         I915_WRITE(PIPEASTAT, 0);
539         I915_WRITE(PIPEBSTAT, 0);
540         I915_WRITE(IMR, 0xffffffff);
541         I915_WRITE(IER, 0x0);
542
543         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
544         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
545         I915_WRITE(IIR, I915_READ(IIR));
546 }