2 * sbus.c: UltraSparc SBUS controller support.
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
7 #include <linux/kernel.h>
8 #include <linux/types.h>
10 #include <linux/spinlock.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
19 #include <asm/cache.h>
23 #include <asm/starfire.h>
25 #include "iommu_common.h"
27 #define MAP_BASE ((u32)0xc0000000)
29 /* Offsets from iommu_regs */
30 #define SYSIO_IOMMUREG_BASE 0x2400UL
31 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
32 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
33 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
34 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
35 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
36 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
37 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
38 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
40 #define IOMMU_DRAM_VALID (1UL << 30UL)
42 /* Offsets from strbuf_regs */
43 #define SYSIO_STRBUFREG_BASE 0x2800UL
44 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
45 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
46 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
47 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
48 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
49 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
50 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
52 #define STRBUF_TAG_VALID 0x02UL
54 /* Enable 64-bit DVMA mode for the given device. */
55 void sbus_set_sbus64(struct device *dev, int bursts)
57 struct iommu *iommu = dev->archdata.iommu;
58 struct of_device *op = to_of_device(dev);
59 const struct linux_prom_registers *regs;
60 unsigned long cfg_reg;
64 regs = of_get_property(op->node, "reg", NULL);
66 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
70 slot = regs->which_io;
72 cfg_reg = iommu->write_complete_reg;
100 val = upa_readq(cfg_reg);
101 if (val & (1UL << 14UL)) {
102 /* Extended transfer mode already enabled. */
106 val |= (1UL << 14UL);
108 if (bursts & DMA_BURST8)
110 if (bursts & DMA_BURST16)
112 if (bursts & DMA_BURST32)
114 if (bursts & DMA_BURST64)
116 upa_writeq(val, cfg_reg);
119 /* INO number to IMAP register offset for SYSIO external IRQ's.
120 * This should conform to both Sunfire/Wildfire server and Fusion
123 #define SYSIO_IMAP_SLOT0 0x2c00UL
124 #define SYSIO_IMAP_SLOT1 0x2c08UL
125 #define SYSIO_IMAP_SLOT2 0x2c10UL
126 #define SYSIO_IMAP_SLOT3 0x2c18UL
127 #define SYSIO_IMAP_SCSI 0x3000UL
128 #define SYSIO_IMAP_ETH 0x3008UL
129 #define SYSIO_IMAP_BPP 0x3010UL
130 #define SYSIO_IMAP_AUDIO 0x3018UL
131 #define SYSIO_IMAP_PFAIL 0x3020UL
132 #define SYSIO_IMAP_KMS 0x3028UL
133 #define SYSIO_IMAP_FLPY 0x3030UL
134 #define SYSIO_IMAP_SHW 0x3038UL
135 #define SYSIO_IMAP_KBD 0x3040UL
136 #define SYSIO_IMAP_MS 0x3048UL
137 #define SYSIO_IMAP_SER 0x3050UL
138 #define SYSIO_IMAP_TIM0 0x3060UL
139 #define SYSIO_IMAP_TIM1 0x3068UL
140 #define SYSIO_IMAP_UE 0x3070UL
141 #define SYSIO_IMAP_CE 0x3078UL
142 #define SYSIO_IMAP_SBERR 0x3080UL
143 #define SYSIO_IMAP_PMGMT 0x3088UL
144 #define SYSIO_IMAP_GFX 0x3090UL
145 #define SYSIO_IMAP_EUPA 0x3098UL
147 #define bogon ((unsigned long) -1)
148 static unsigned long sysio_irq_offsets[] = {
149 /* SBUS Slot 0 --> 3, level 1 --> 7 */
150 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
151 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
152 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
153 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
154 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
155 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
156 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
157 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
159 /* Onboard devices (not relevant/used on SunFire). */
188 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
190 /* Convert Interrupt Mapping register pointer to associated
191 * Interrupt Clear register pointer, SYSIO specific version.
193 #define SYSIO_ICLR_UNUSED0 0x3400UL
194 #define SYSIO_ICLR_SLOT0 0x3408UL
195 #define SYSIO_ICLR_SLOT1 0x3448UL
196 #define SYSIO_ICLR_SLOT2 0x3488UL
197 #define SYSIO_ICLR_SLOT3 0x34c8UL
198 static unsigned long sysio_imap_to_iclr(unsigned long imap)
200 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
204 static unsigned int sbus_build_irq(struct of_device *op, unsigned int ino)
206 struct iommu *iommu = op->dev.archdata.iommu;
207 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
208 unsigned long imap, iclr;
211 imap = sysio_irq_offsets[ino];
212 if (imap == ((unsigned long)-1)) {
213 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
219 /* SYSIO inconsistency. For external SLOTS, we have to select
220 * the right ICLR register based upon the lower SBUS irq level
224 iclr = sysio_imap_to_iclr(imap);
226 int sbus_slot = (ino & 0x18)>>3;
228 sbus_level = ino & 0x7;
232 iclr = reg_base + SYSIO_ICLR_SLOT0;
235 iclr = reg_base + SYSIO_ICLR_SLOT1;
238 iclr = reg_base + SYSIO_ICLR_SLOT2;
242 iclr = reg_base + SYSIO_ICLR_SLOT3;
246 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
248 return build_irq(sbus_level, iclr, imap);
251 /* Error interrupt handling. */
252 #define SYSIO_UE_AFSR 0x0030UL
253 #define SYSIO_UE_AFAR 0x0038UL
254 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
255 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
256 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
257 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
258 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
259 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
260 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
261 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
262 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
263 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
264 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
265 static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
267 struct of_device *op = dev_id;
268 struct iommu *iommu = op->dev.archdata.iommu;
269 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
270 unsigned long afsr_reg, afar_reg;
271 unsigned long afsr, afar, error_bits;
272 int reported, portid;
274 afsr_reg = reg_base + SYSIO_UE_AFSR;
275 afar_reg = reg_base + SYSIO_UE_AFAR;
277 /* Latch error status. */
278 afsr = upa_readq(afsr_reg);
279 afar = upa_readq(afar_reg);
281 /* Clear primary/secondary error status bits. */
283 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
284 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
285 upa_writeq(error_bits, afsr_reg);
287 portid = of_getintprop_default(op->node, "portid", -1);
290 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
292 (((error_bits & SYSIO_UEAFSR_PPIO) ?
294 ((error_bits & SYSIO_UEAFSR_PDRD) ?
296 ((error_bits & SYSIO_UEAFSR_PDWR) ?
297 "DVMA Write" : "???")))));
298 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
300 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
301 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
302 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
303 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
304 printk("SYSIO[%x]: Secondary UE errors [", portid);
306 if (afsr & SYSIO_UEAFSR_SPIO) {
310 if (afsr & SYSIO_UEAFSR_SDRD) {
312 printk("(DVMA Read)");
314 if (afsr & SYSIO_UEAFSR_SDWR) {
316 printk("(DVMA Write)");
325 #define SYSIO_CE_AFSR 0x0040UL
326 #define SYSIO_CE_AFAR 0x0048UL
327 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
328 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
329 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
330 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
331 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
332 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
333 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
334 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
335 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
336 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
337 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
338 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
339 static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
341 struct of_device *op = dev_id;
342 struct iommu *iommu = op->dev.archdata.iommu;
343 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
344 unsigned long afsr_reg, afar_reg;
345 unsigned long afsr, afar, error_bits;
346 int reported, portid;
348 afsr_reg = reg_base + SYSIO_CE_AFSR;
349 afar_reg = reg_base + SYSIO_CE_AFAR;
351 /* Latch error status. */
352 afsr = upa_readq(afsr_reg);
353 afar = upa_readq(afar_reg);
355 /* Clear primary/secondary error status bits. */
357 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
358 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
359 upa_writeq(error_bits, afsr_reg);
361 portid = of_getintprop_default(op->node, "portid", -1);
363 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
365 (((error_bits & SYSIO_CEAFSR_PPIO) ?
367 ((error_bits & SYSIO_CEAFSR_PDRD) ?
369 ((error_bits & SYSIO_CEAFSR_PDWR) ?
370 "DVMA Write" : "???")))));
372 /* XXX Use syndrome and afar to print out module string just like
373 * XXX UDB CE trap handler does... -DaveM
375 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
377 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
378 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
379 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
380 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
381 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
383 printk("SYSIO[%x]: Secondary CE errors [", portid);
385 if (afsr & SYSIO_CEAFSR_SPIO) {
389 if (afsr & SYSIO_CEAFSR_SDRD) {
391 printk("(DVMA Read)");
393 if (afsr & SYSIO_CEAFSR_SDWR) {
395 printk("(DVMA Write)");
404 #define SYSIO_SBUS_AFSR 0x2010UL
405 #define SYSIO_SBUS_AFAR 0x2018UL
406 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
407 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
408 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
409 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
410 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
411 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
412 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
413 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
414 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
415 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
416 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
417 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
418 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
420 struct of_device *op = dev_id;
421 struct iommu *iommu = op->dev.archdata.iommu;
422 unsigned long afsr_reg, afar_reg, reg_base;
423 unsigned long afsr, afar, error_bits;
424 int reported, portid;
426 reg_base = iommu->write_complete_reg - 0x2000UL;
427 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
428 afar_reg = reg_base + SYSIO_SBUS_AFAR;
430 afsr = upa_readq(afsr_reg);
431 afar = upa_readq(afar_reg);
433 /* Clear primary/secondary error status bits. */
435 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
436 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
437 upa_writeq(error_bits, afsr_reg);
439 portid = of_getintprop_default(op->node, "portid", -1);
442 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
444 (((error_bits & SYSIO_SBAFSR_PLE) ?
446 ((error_bits & SYSIO_SBAFSR_PTO) ?
448 ((error_bits & SYSIO_SBAFSR_PBERR) ?
449 "Error Ack" : "???")))),
450 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
451 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
453 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
454 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
455 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
456 printk("SYSIO[%x]: Secondary SBUS errors [", portid);
458 if (afsr & SYSIO_SBAFSR_SLE) {
460 printk("(Late PIO Error)");
462 if (afsr & SYSIO_SBAFSR_STO) {
464 printk("(Time Out)");
466 if (afsr & SYSIO_SBAFSR_SBERR) {
468 printk("(Error Ack)");
474 /* XXX check iommu/strbuf for further error status XXX */
479 #define ECC_CONTROL 0x0020UL
480 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
481 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
482 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
484 #define SYSIO_UE_INO 0x34
485 #define SYSIO_CE_INO 0x35
486 #define SYSIO_SBUSERR_INO 0x36
488 static void __init sysio_register_error_handlers(struct of_device *op)
490 struct iommu *iommu = op->dev.archdata.iommu;
491 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
496 portid = of_getintprop_default(op->node, "portid", -1);
498 irq = sbus_build_irq(op, SYSIO_UE_INO);
499 if (request_irq(irq, sysio_ue_handler, 0,
500 "SYSIO_UE", op) < 0) {
501 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
506 irq = sbus_build_irq(op, SYSIO_CE_INO);
507 if (request_irq(irq, sysio_ce_handler, 0,
508 "SYSIO_CE", op) < 0) {
509 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
514 irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
515 if (request_irq(irq, sysio_sbus_error_handler, 0,
516 "SYSIO_SBERR", op) < 0) {
517 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
522 /* Now turn the error interrupts on and also enable ECC checking. */
523 upa_writeq((SYSIO_ECNTRL_ECCEN |
526 reg_base + ECC_CONTROL);
528 control = upa_readq(iommu->write_complete_reg);
529 control |= 0x100UL; /* SBUS Error Interrupt Enable */
530 upa_writeq(control, iommu->write_complete_reg);
533 /* Boot time initialization. */
534 static void __init sbus_iommu_init(struct of_device *op)
536 const struct linux_prom64_registers *pr;
537 struct device_node *dp = op->node;
539 struct strbuf *strbuf;
540 unsigned long regs, reg_base;
544 pr = of_get_property(dp, "reg", NULL);
546 prom_printf("sbus_iommu_init: Cannot map SYSIO "
547 "control registers.\n");
550 regs = pr->phys_addr;
552 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
554 goto fatal_memory_error;
555 strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
557 goto fatal_memory_error;
559 op->dev.archdata.iommu = iommu;
560 op->dev.archdata.stc = strbuf;
561 op->dev.archdata.numa_node = -1;
563 reg_base = regs + SYSIO_IOMMUREG_BASE;
564 iommu->iommu_control = reg_base + IOMMU_CONTROL;
565 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
566 iommu->iommu_flush = reg_base + IOMMU_FLUSH;
567 iommu->iommu_tags = iommu->iommu_control +
568 (IOMMU_TAGDIAG - IOMMU_CONTROL);
570 reg_base = regs + SYSIO_STRBUFREG_BASE;
571 strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
572 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
573 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
575 strbuf->strbuf_enabled = 1;
577 strbuf->strbuf_flushflag = (volatile unsigned long *)
578 ((((unsigned long)&strbuf->__flushflag_buf[0])
581 strbuf->strbuf_flushflag_pa = (unsigned long)
582 __pa(strbuf->strbuf_flushflag);
584 /* The SYSIO SBUS control register is used for dummy reads
585 * in order to ensure write completion.
587 iommu->write_complete_reg = regs + 0x2000UL;
589 portid = of_getintprop_default(op->node, "portid", -1);
590 printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
593 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
594 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
595 goto fatal_memory_error;
597 control = upa_readq(iommu->iommu_control);
598 control = ((7UL << 16UL) |
602 upa_writeq(control, iommu->iommu_control);
604 /* Clean out any cruft in the IOMMU using
605 * diagnostic accesses.
607 for (i = 0; i < 16; i++) {
608 unsigned long dram, tag;
610 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
611 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
613 dram += (unsigned long)i * 8UL;
614 tag += (unsigned long)i * 8UL;
618 upa_readq(iommu->write_complete_reg);
620 /* Give the TSB to SYSIO. */
621 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
623 /* Setup streaming buffer, DE=1 SB_EN=1 */
624 control = (1UL << 1UL) | (1UL << 0UL);
625 upa_writeq(control, strbuf->strbuf_control);
627 /* Clear out the tags using diagnostics. */
628 for (i = 0; i < 16; i++) {
629 unsigned long ptag, ltag;
631 ptag = strbuf->strbuf_control +
632 (STRBUF_PTAGDIAG - STRBUF_CONTROL);
633 ltag = strbuf->strbuf_control +
634 (STRBUF_LTAGDIAG - STRBUF_CONTROL);
635 ptag += (unsigned long)i * 8UL;
636 ltag += (unsigned long)i * 8UL;
638 upa_writeq(0UL, ptag);
639 upa_writeq(0UL, ltag);
642 /* Enable DVMA arbitration for all devices/slots. */
643 control = upa_readq(iommu->write_complete_reg);
645 upa_writeq(control, iommu->write_complete_reg);
647 /* Now some Xfire specific grot... */
648 if (this_is_starfire)
649 starfire_hookup(portid);
651 sysio_register_error_handlers(op);
655 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
658 static int __init sbus_init(void)
660 extern void firetruck_init(void);
661 struct device_node *dp;
663 for_each_node_by_name(dp, "sbus") {
664 struct of_device *op = of_find_device_by_node(dp);
667 of_propagate_archdata(op);
675 subsys_initcall(sbus_init);