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   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/hardware.h>
  31 #include <asm/dma.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE         0x01
  47 #define OMAP_DMA_CCR_EN         (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode = 0;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (* callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126
 127 static spinlock_t dma_chan_lock;
 128 static struct omap_dma_lch *dma_chan;
 129 static void __iomem *omap_dma_base;
 130
 131 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 132         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 133         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 134         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 135         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 136         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 137 };
 138
 139 static inline void disable_lnk(int lch);
 140 static void omap_disable_channel_irq(int lch);
 141 static inline void omap_enable_channel_irq(int lch);
 142
 143 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 144                                                 __func__);
 145
 146 #define dma_read(reg)                                                   \
 147 ({                                                                      \
 148         u32 __val;                                                      \
 149         if (cpu_class_is_omap1())                                       \
 150                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 151         else                                                            \
 152                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 153         __val;                                                          \
 154 })
 155
 156 #define dma_write(val, reg)                                             \
 157 ({                                                                      \
 158         if (cpu_class_is_omap1())                                       \
 159                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 160         else                                                            \
 161                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 162 })
 163
 164 #ifdef CONFIG_ARCH_OMAP15XX
 165 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 166 int omap_dma_in_1510_mode(void)
 167 {
 168         return enable_1510_mode;
 169 }
 170 #else
 171 #define omap_dma_in_1510_mode()         0
 172 #endif
 173
 174 #ifdef CONFIG_ARCH_OMAP1
 175 static inline int get_gdma_dev(int req)
 176 {
 177         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 178         int shift = ((req - 1) % 5) * 6;
 179
 180         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 181 }
 182
 183 static inline void set_gdma_dev(int req, int dev)
 184 {
 185         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 186         int shift = ((req - 1) % 5) * 6;
 187         u32 l;
 188
 189         l = omap_readl(reg);
 190         l &= ~(0x3f << shift);
 191         l |= (dev - 1) << shift;
 192         omap_writel(l, reg);
 193 }
 194 #else
 195 #define set_gdma_dev(req, dev)  do {} while (0)
 196 #endif
 197
 198 /* Omap1 only */
 199 static void clear_lch_regs(int lch)
 200 {
 201         int i;
 202         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 203
 204         for (i = 0; i < 0x2c; i += 2)
 205                 __raw_writew(0, lch_base + i);
 206 }
 207
 208 void omap_set_dma_priority(int lch, int dst_port, int priority)
 209 {
 210         unsigned long reg;
 211         u32 l;
 212
 213         if (cpu_class_is_omap1()) {
 214                 switch (dst_port) {
 215                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 216                         reg = OMAP_TC_OCPT1_PRIOR;
 217                         break;
 218                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 219                         reg = OMAP_TC_OCPT2_PRIOR;
 220                         break;
 221                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 222                         reg = OMAP_TC_EMIFF_PRIOR;
 223                         break;
 224                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 225                         reg = OMAP_TC_EMIFS_PRIOR;
 226                         break;
 227                 default:
 228                         BUG();
 229                         return;
 230                 }
 231                 l = omap_readl(reg);
 232                 l &= ~(0xf << 8);
 233                 l |= (priority & 0xf) << 8;
 234                 omap_writel(l, reg);
 235         }
 236
 237         if (cpu_class_is_omap2()) {
 238                 u32 ccr;
 239
 240                 ccr = dma_read(CCR(lch));
 241                 if (priority)
 242                         ccr |= (1 << 6);
 243                 else
 244                         ccr &= ~(1 << 6);
 245                 dma_write(ccr, CCR(lch));
 246         }
 247 }
 248
 249 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 250                                   int frame_count, int sync_mode,
 251                                   int dma_trigger, int src_or_dst_synch)
 252 {
 253         u32 l;
 254
 255         l = dma_read(CSDP(lch));
 256         l &= ~0x03;
 257         l |= data_type;
 258         dma_write(l, CSDP(lch));
 259
 260         if (cpu_class_is_omap1()) {
 261                 u16 ccr;
 262
 263                 ccr = dma_read(CCR(lch));
 264                 ccr &= ~(1 << 5);
 265                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 266                         ccr |= 1 << 5;
 267                 dma_write(ccr, CCR(lch));
 268
 269                 ccr = dma_read(CCR2(lch));
 270                 ccr &= ~(1 << 2);
 271                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 272                         ccr |= 1 << 2;
 273                 dma_write(ccr, CCR2(lch));
 274         }
 275
 276         if (cpu_class_is_omap2() && dma_trigger) {
 277                 u32 val;
 278
 279                 val = dma_read(CCR(lch));
 280                 val &= ~(3 << 19);
 281                 if (dma_trigger > 63)
 282                         val |= 1 << 20;
 283                 if (dma_trigger > 31)
 284                         val |= 1 << 19;
 285
 286                 val &= ~(0x1f);
 287                 val |= (dma_trigger & 0x1f);
 288
 289                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 290                         val |= 1 << 5;
 291                 else
 292                         val &= ~(1 << 5);
 293
 294                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 295                         val |= 1 << 18;
 296                 else
 297                         val &= ~(1 << 18);
 298
 299                 if (src_or_dst_synch)
 300                         val |= 1 << 24;         /* source synch */
 301                 else
 302                         val &= ~(1 << 24);      /* dest synch */
 303
 304                 dma_write(val, CCR(lch));
 305         }
 306
 307         dma_write(elem_count, CEN(lch));
 308         dma_write(frame_count, CFN(lch));
 309 }
 310
 311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 312 {
 313         u16 w;
 314
 315         BUG_ON(omap_dma_in_1510_mode());
 316
 317         if (cpu_class_is_omap2()) {
 318                 REVISIT_24XX();
 319                 return;
 320         }
 321
 322         w = dma_read(CCR2(lch));
 323         w &= ~0x03;
 324
 325         switch (mode) {
 326         case OMAP_DMA_CONSTANT_FILL:
 327                 w |= 0x01;
 328                 break;
 329         case OMAP_DMA_TRANSPARENT_COPY:
 330                 w |= 0x02;
 331                 break;
 332         case OMAP_DMA_COLOR_DIS:
 333                 break;
 334         default:
 335                 BUG();
 336         }
 337         dma_write(w, CCR2(lch));
 338
 339         w = dma_read(LCH_CTRL(lch));
 340         w &= ~0x0f;
 341         /* Default is channel type 2D */
 342         if (mode) {
 343                 dma_write((u16)color, COLOR_L(lch));
 344                 dma_write((u16)(color >> 16), COLOR_U(lch));
 345                 w |= 1;         /* Channel type G */
 346         }
 347         dma_write(w, LCH_CTRL(lch));
 348 }
 349
 350 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 351 {
 352         if (cpu_class_is_omap2()) {
 353                 u32 csdp;
 354
 355                 csdp = dma_read(CSDP(lch));
 356                 csdp &= ~(0x3 << 16);
 357                 csdp |= (mode << 16);
 358                 dma_write(csdp, CSDP(lch));
 359         }
 360 }
 361
 362 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 363 {
 364         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 365                 u32 l;
 366
 367                 l = dma_read(LCH_CTRL(lch));
 368                 l &= ~0x7;
 369                 l |= mode;
 370                 dma_write(l, LCH_CTRL(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 374
 375 /* Note that src_port is only for omap1 */
 376 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 377                              unsigned long src_start,
 378                              int src_ei, int src_fi)
 379 {
 380         if (cpu_class_is_omap1()) {
 381                 u16 w;
 382
 383                 w = dma_read(CSDP(lch));
 384                 w &= ~(0x1f << 2);
 385                 w |= src_port << 2;
 386                 dma_write(w, CSDP(lch));
 387
 388                 w = dma_read(CCR(lch));
 389                 w &= ~(0x03 << 12);
 390                 w |= src_amode << 12;
 391                 dma_write(w, CCR(lch));
 392
 393                 dma_write(src_start >> 16, CSSA_U(lch));
 394                 dma_write((u16)src_start, CSSA_L(lch));
 395
 396                 dma_write(src_ei, CSEI(lch));
 397                 dma_write(src_fi, CSFI(lch));
 398         }
 399
 400         if (cpu_class_is_omap2()) {
 401                 u32 l;
 402
 403                 l = dma_read(CCR(lch));
 404                 l &= ~(0x03 << 12);
 405                 l |= src_amode << 12;
 406                 dma_write(l, CCR(lch));
 407
 408                 dma_write(src_start, CSSA(lch));
 409                 dma_write(src_ei, CSEI(lch));
 410                 dma_write(src_fi, CSFI(lch));
 411         }
 412 }
 413
 414 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
 415 {
 416         omap_set_dma_transfer_params(lch, params->data_type,
 417                                      params->elem_count, params->frame_count,
 418                                      params->sync_mode, params->trigger,
 419                                      params->src_or_dst_synch);
 420         omap_set_dma_src_params(lch, params->src_port,
 421                                 params->src_amode, params->src_start,
 422                                 params->src_ei, params->src_fi);
 423
 424         omap_set_dma_dest_params(lch, params->dst_port,
 425                                  params->dst_amode, params->dst_start,
 426                                  params->dst_ei, params->dst_fi);
 427         if (params->read_prio || params->write_prio)
 428                 omap_dma_set_prio_lch(lch, params->read_prio,
 429                                       params->write_prio);
 430 }
 431
 432 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 433 {
 434         if (cpu_class_is_omap2()) {
 435                 REVISIT_24XX();
 436                 return;
 437         }
 438         dma_write(eidx, CSEI(lch));
 439         dma_write(fidx, CSFI(lch));
 440 }
 441
 442 void omap_set_dma_src_data_pack(int lch, int enable)
 443 {
 444         u32 l;
 445
 446         l = dma_read(CSDP(lch));
 447         l &= ~(1 << 6);
 448         if (enable)
 449                 l |= (1 << 6);
 450         dma_write(l, CSDP(lch));
 451 }
 452
 453 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 454 {
 455         unsigned int burst = 0;
 456         u32 l;
 457
 458         l = dma_read(CSDP(lch));
 459         l &= ~(0x03 << 7);
 460
 461         switch (burst_mode) {
 462         case OMAP_DMA_DATA_BURST_DIS:
 463                 break;
 464         case OMAP_DMA_DATA_BURST_4:
 465                 if (cpu_class_is_omap2())
 466                         burst = 0x1;
 467                 else
 468                         burst = 0x2;
 469                 break;
 470         case OMAP_DMA_DATA_BURST_8:
 471                 if (cpu_class_is_omap2()) {
 472                         burst = 0x2;
 473                         break;
 474                 }
 475                 /* not supported by current hardware on OMAP1
 476                  * w |= (0x03 << 7);
 477                  * fall through
 478                  */
 479         case OMAP_DMA_DATA_BURST_16:
 480                 if (cpu_class_is_omap2()) {
 481                         burst = 0x3;
 482                         break;
 483                 }
 484                 /* OMAP1 don't support burst 16
 485                  * fall through
 486                  */
 487         default:
 488                 BUG();
 489         }
 490
 491         l |= (burst << 7);
 492         dma_write(l, CSDP(lch));
 493 }
 494
 495 /* Note that dest_port is only for OMAP1 */
 496 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 497                               unsigned long dest_start,
 498                               int dst_ei, int dst_fi)
 499 {
 500         u32 l;
 501
 502         if (cpu_class_is_omap1()) {
 503                 l = dma_read(CSDP(lch));
 504                 l &= ~(0x1f << 9);
 505                 l |= dest_port << 9;
 506                 dma_write(l, CSDP(lch));
 507         }
 508
 509         l = dma_read(CCR(lch));
 510         l &= ~(0x03 << 14);
 511         l |= dest_amode << 14;
 512         dma_write(l, CCR(lch));
 513
 514         if (cpu_class_is_omap1()) {
 515                 dma_write(dest_start >> 16, CDSA_U(lch));
 516                 dma_write(dest_start, CDSA_L(lch));
 517         }
 518
 519         if (cpu_class_is_omap2())
 520                 dma_write(dest_start, CDSA(lch));
 521
 522         dma_write(dst_ei, CDEI(lch));
 523         dma_write(dst_fi, CDFI(lch));
 524 }
 525
 526 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 527 {
 528         if (cpu_class_is_omap2()) {
 529                 REVISIT_24XX();
 530                 return;
 531         }
 532         dma_write(eidx, CDEI(lch));
 533         dma_write(fidx, CDFI(lch));
 534 }
 535
 536 void omap_set_dma_dest_data_pack(int lch, int enable)
 537 {
 538         u32 l;
 539
 540         l = dma_read(CSDP(lch));
 541         l &= ~(1 << 13);
 542         if (enable)
 543                 l |= 1 << 13;
 544         dma_write(l, CSDP(lch));
 545 }
 546
 547 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 548 {
 549         unsigned int burst = 0;
 550         u32 l;
 551
 552         l = dma_read(CSDP(lch));
 553         l &= ~(0x03 << 14);
 554
 555         switch (burst_mode) {
 556         case OMAP_DMA_DATA_BURST_DIS:
 557                 break;
 558         case OMAP_DMA_DATA_BURST_4:
 559                 if (cpu_class_is_omap2())
 560                         burst = 0x1;
 561                 else
 562                         burst = 0x2;
 563                 break;
 564         case OMAP_DMA_DATA_BURST_8:
 565                 if (cpu_class_is_omap2())
 566                         burst = 0x2;
 567                 else
 568                         burst = 0x3;
 569                 break;
 570         case OMAP_DMA_DATA_BURST_16:
 571                 if (cpu_class_is_omap2()) {
 572                         burst = 0x3;
 573                         break;
 574                 }
 575                 /* OMAP1 don't support burst 16
 576                  * fall through
 577                  */
 578         default:
 579                 printk(KERN_ERR "Invalid DMA burst mode\n");
 580                 BUG();
 581                 return;
 582         }
 583         l |= (burst << 14);
 584         dma_write(l, CSDP(lch));
 585 }
 586
 587 static inline void omap_enable_channel_irq(int lch)
 588 {
 589         u32 status;
 590
 591         /* Clear CSR */
 592         if (cpu_class_is_omap1())
 593                 status = dma_read(CSR(lch));
 594         else if (cpu_class_is_omap2())
 595                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 596
 597         /* Enable some nice interrupts. */
 598         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 599 }
 600
 601 static void omap_disable_channel_irq(int lch)
 602 {
 603         if (cpu_class_is_omap2())
 604                 dma_write(0, CICR(lch));
 605 }
 606
 607 void omap_enable_dma_irq(int lch, u16 bits)
 608 {
 609         dma_chan[lch].enabled_irqs |= bits;
 610 }
 611
 612 void omap_disable_dma_irq(int lch, u16 bits)
 613 {
 614         dma_chan[lch].enabled_irqs &= ~bits;
 615 }
 616
 617 static inline void enable_lnk(int lch)
 618 {
 619         u32 l;
 620
 621         l = dma_read(CLNK_CTRL(lch));
 622
 623         if (cpu_class_is_omap1())
 624                 l &= ~(1 << 14);
 625
 626         /* Set the ENABLE_LNK bits */
 627         if (dma_chan[lch].next_lch != -1)
 628                 l = dma_chan[lch].next_lch | (1 << 15);
 629
 630 #ifndef CONFIG_ARCH_OMAP1
 631         if (dma_chan[lch].next_linked_ch != -1)
 632                 l = dma_chan[lch].next_linked_ch | (1 << 15);
 633 #endif
 634
 635         dma_write(l, CLNK_CTRL(lch));
 636 }
 637
 638 static inline void disable_lnk(int lch)
 639 {
 640         u32 l;
 641
 642         l = dma_read(CLNK_CTRL(lch));
 643
 644         /* Disable interrupts */
 645         if (cpu_class_is_omap1()) {
 646                 dma_write(0, CICR(lch));
 647                 /* Set the STOP_LNK bit */
 648                 l |= 1 << 14;
 649         }
 650
 651         if (cpu_class_is_omap2()) {
 652                 omap_disable_channel_irq(lch);
 653                 /* Clear the ENABLE_LNK bit */
 654                 l &= ~(1 << 15);
 655         }
 656
 657         dma_write(l, CLNK_CTRL(lch));
 658         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 659 }
 660
 661 static inline void omap2_enable_irq_lch(int lch)
 662 {
 663         u32 val;
 664
 665         if (!cpu_class_is_omap2())
 666                 return;
 667
 668         val = dma_read(IRQENABLE_L0);
 669         val |= 1 << lch;
 670         dma_write(val, IRQENABLE_L0);
 671 }
 672
 673 int omap_request_dma(int dev_id, const char *dev_name,
 674                      void (* callback)(int lch, u16 ch_status, void *data),
 675                      void *data, int *dma_ch_out)
 676 {
 677         int ch, free_ch = -1;
 678         unsigned long flags;
 679         struct omap_dma_lch *chan;
 680
 681         spin_lock_irqsave(&dma_chan_lock, flags);
 682         for (ch = 0; ch < dma_chan_count; ch++) {
 683                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 684                         free_ch = ch;
 685                         if (dev_id == 0)
 686                                 break;
 687                 }
 688         }
 689         if (free_ch == -1) {
 690                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 691                 return -EBUSY;
 692         }
 693         chan = dma_chan + free_ch;
 694         chan->dev_id = dev_id;
 695
 696         if (cpu_class_is_omap1())
 697                 clear_lch_regs(free_ch);
 698
 699         if (cpu_class_is_omap2())
 700                 omap_clear_dma(free_ch);
 701
 702         spin_unlock_irqrestore(&dma_chan_lock, flags);
 703
 704         chan->dev_name = dev_name;
 705         chan->callback = callback;
 706         chan->data = data;
 707 #ifndef CONFIG_ARCH_OMAP1
 708         chan->chain_id = -1;
 709         chan->next_linked_ch = -1;
 710 #endif
 711         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 712
 713         if (cpu_class_is_omap1())
 714                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 715         else if (cpu_class_is_omap2())
 716                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 717                         OMAP2_DMA_TRANS_ERR_IRQ;
 718
 719         if (cpu_is_omap16xx()) {
 720                 /* If the sync device is set, configure it dynamically. */
 721                 if (dev_id != 0) {
 722                         set_gdma_dev(free_ch + 1, dev_id);
 723                         dev_id = free_ch + 1;
 724                 }
 725                 /* Disable the 1510 compatibility mode and set the sync device
 726                  * id. */
 727                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 728         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 729                 dma_write(dev_id, CCR(free_ch));
 730         }
 731
 732         if (cpu_class_is_omap2()) {
 733                 omap2_enable_irq_lch(free_ch);
 734
 735                 omap_enable_channel_irq(free_ch);
 736                 /* Clear the CSR register and IRQ status register */
 737                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 738                 dma_write(1 << free_ch, IRQSTATUS_L0);
 739         }
 740
 741         *dma_ch_out = free_ch;
 742
 743         return 0;
 744 }
 745
 746 void omap_free_dma(int lch)
 747 {
 748         unsigned long flags;
 749
 750         spin_lock_irqsave(&dma_chan_lock, flags);
 751         if (dma_chan[lch].dev_id == -1) {
 752                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
 753                        lch);
 754                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 755                 return;
 756         }
 757         dma_chan[lch].dev_id = -1;
 758         dma_chan[lch].next_lch = -1;
 759         dma_chan[lch].callback = NULL;
 760         spin_unlock_irqrestore(&dma_chan_lock, flags);
 761
 762         if (cpu_class_is_omap1()) {
 763                 /* Disable all DMA interrupts for the channel. */
 764                 dma_write(0, CICR(lch));
 765                 /* Make sure the DMA transfer is stopped. */
 766                 dma_write(0, CCR(lch));
 767         }
 768
 769         if (cpu_class_is_omap2()) {
 770                 u32 val;
 771                 /* Disable interrupts */
 772                 val = dma_read(IRQENABLE_L0);
 773                 val &= ~(1 << lch);
 774                 dma_write(val, IRQENABLE_L0);
 775
 776                 /* Clear the CSR register and IRQ status register */
 777                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 778                 dma_write(1 << lch, IRQSTATUS_L0);
 779
 780                 /* Disable all DMA interrupts for the channel. */
 781                 dma_write(0, CICR(lch));
 782
 783                 /* Make sure the DMA transfer is stopped. */
 784                 dma_write(0, CCR(lch));
 785                 omap_clear_dma(lch);
 786         }
 787 }
 788
 789 /**
 790  * @brief omap_dma_set_global_params : Set global priority settings for dma
 791  *
 792  * @param arb_rate
 793  * @param max_fifo_depth
 794  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 795  *                                                  DMA_THREAD_RESERVE_ONET
 796  *                                                  DMA_THREAD_RESERVE_TWOT
 797  *                                                  DMA_THREAD_RESERVE_THREET
 798  */
 799 void
 800 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 801 {
 802         u32 reg;
 803
 804         if (!cpu_class_is_omap2()) {
 805                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 806                 return;
 807         }
 808
 809         if (arb_rate == 0)
 810                 arb_rate = 1;
 811
 812         reg = (arb_rate & 0xff) << 16;
 813         reg |= (0xff & max_fifo_depth);
 814
 815         dma_write(reg, GCR);
 816 }
 817 EXPORT_SYMBOL(omap_dma_set_global_params);
 818
 819 /**
 820  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 821  *
 822  * @param lch
 823  * @param read_prio - Read priority
 824  * @param write_prio - Write priority
 825  * Both of the above can be set with one of the following values :
 826  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 827  */
 828 int
 829 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 830                       unsigned char write_prio)
 831 {
 832         u32 l;
 833
 834         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 835                 printk(KERN_ERR "Invalid channel id\n");
 836                 return -EINVAL;
 837         }
 838         l = dma_read(CCR(lch));
 839         l &= ~((1 << 6) | (1 << 26));
 840         if (cpu_is_omap2430() || cpu_is_omap34xx())
 841                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 842         else
 843                 l |= ((read_prio & 0x1) << 6);
 844
 845         dma_write(l, CCR(lch));
 846
 847         return 0;
 848 }
 849 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 850
 851 /*
 852  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 853  * through omap_start_dma(). Any buffers in flight are discarded.
 854  */
 855 void omap_clear_dma(int lch)
 856 {
 857         unsigned long flags;
 858
 859         local_irq_save(flags);
 860
 861         if (cpu_class_is_omap1()) {
 862                 u32 l;
 863
 864                 l = dma_read(CCR(lch));
 865                 l &= ~OMAP_DMA_CCR_EN;
 866                 dma_write(l, CCR(lch));
 867
 868                 /* Clear pending interrupts */
 869                 l = dma_read(CSR(lch));
 870         }
 871
 872         if (cpu_class_is_omap2()) {
 873                 int i;
 874                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 875                 for (i = 0; i < 0x44; i += 4)
 876                         __raw_writel(0, lch_base + i);
 877         }
 878
 879         local_irq_restore(flags);
 880 }
 881
 882 void omap_start_dma(int lch)
 883 {
 884         u32 l;
 885
 886         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 887                 int next_lch, cur_lch;
 888                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 889
 890                 dma_chan_link_map[lch] = 1;
 891                 /* Set the link register of the first channel */
 892                 enable_lnk(lch);
 893
 894                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 895                 cur_lch = dma_chan[lch].next_lch;
 896                 do {
 897                         next_lch = dma_chan[cur_lch].next_lch;
 898
 899                         /* The loop case: we've been here already */
 900                         if (dma_chan_link_map[cur_lch])
 901                                 break;
 902                         /* Mark the current channel */
 903                         dma_chan_link_map[cur_lch] = 1;
 904
 905                         enable_lnk(cur_lch);
 906                         omap_enable_channel_irq(cur_lch);
 907
 908                         cur_lch = next_lch;
 909                 } while (next_lch != -1);
 910         } else if (cpu_class_is_omap2()) {
 911                 /* Errata: Need to write lch even if not using chaining */
 912                 dma_write(lch, CLNK_CTRL(lch));
 913         }
 914
 915         omap_enable_channel_irq(lch);
 916
 917         l = dma_read(CCR(lch));
 918
 919         /* Errata: On ES2.0 BUFFERING disable must be set.
 920          * This will always fail on ES1.0 */
 921         if (cpu_is_omap24xx())
 922                 l |= OMAP_DMA_CCR_EN;
 923
 924         l |= OMAP_DMA_CCR_EN;
 925         dma_write(l, CCR(lch));
 926
 927         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 928 }
 929
 930 void omap_stop_dma(int lch)
 931 {
 932         u32 l;
 933
 934         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 935                 int next_lch, cur_lch = lch;
 936                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 937
 938                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 939                 do {
 940                         /* The loop case: we've been here already */
 941                         if (dma_chan_link_map[cur_lch])
 942                                 break;
 943                         /* Mark the current channel */
 944                         dma_chan_link_map[cur_lch] = 1;
 945
 946                         disable_lnk(cur_lch);
 947
 948                         next_lch = dma_chan[cur_lch].next_lch;
 949                         cur_lch = next_lch;
 950                 } while (next_lch != -1);
 951
 952                 return;
 953         }
 954
 955         /* Disable all interrupts on the channel */
 956         if (cpu_class_is_omap1())
 957                 dma_write(0, CICR(lch));
 958
 959         l = dma_read(CCR(lch));
 960         l &= ~OMAP_DMA_CCR_EN;
 961         dma_write(l, CCR(lch));
 962
 963         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 964 }
 965
 966 /*
 967  * Allows changing the DMA callback function or data. This may be needed if
 968  * the driver shares a single DMA channel for multiple dma triggers.
 969  */
 970 int omap_set_dma_callback(int lch,
 971                           void (* callback)(int lch, u16 ch_status, void *data),
 972                           void *data)
 973 {
 974         unsigned long flags;
 975
 976         if (lch < 0)
 977                 return -ENODEV;
 978
 979         spin_lock_irqsave(&dma_chan_lock, flags);
 980         if (dma_chan[lch].dev_id == -1) {
 981                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 982                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 983                 return -EINVAL;
 984         }
 985         dma_chan[lch].callback = callback;
 986         dma_chan[lch].data = data;
 987         spin_unlock_irqrestore(&dma_chan_lock, flags);
 988
 989         return 0;
 990 }
 991
 992 /*
 993  * Returns current physical source address for the given DMA channel.
 994  * If the channel is running the caller must disable interrupts prior calling
 995  * this function and process the returned value before re-enabling interrupt to
 996  * prevent races with the interrupt handler. Note that in continuous mode there
 997  * is a chance for CSSA_L register overflow inbetween the two reads resulting
 998  * in incorrect return value.
 999  */
1000 dma_addr_t omap_get_dma_src_pos(int lch)
1001 {
1002         dma_addr_t offset = 0;
1003
1004         if (cpu_is_omap15xx())
1005                 offset = dma_read(CPC(lch));
1006         else
1007                 offset = dma_read(CSAC(lch));
1008
1009         /*
1010          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1011          * read before the DMA controller finished disabling the channel.
1012          */
1013         if (!cpu_is_omap15xx() && offset == 0)
1014                 offset = dma_read(CSAC(lch));
1015
1016         if (cpu_class_is_omap1())
1017                 offset |= (dma_read(CSSA_U(lch)) << 16);
1018
1019         return offset;
1020 }
1021
1022 /*
1023  * Returns current physical destination address for the given DMA channel.
1024  * If the channel is running the caller must disable interrupts prior calling
1025  * this function and process the returned value before re-enabling interrupt to
1026  * prevent races with the interrupt handler. Note that in continuous mode there
1027  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1028  * in incorrect return value.
1029  */
1030 dma_addr_t omap_get_dma_dst_pos(int lch)
1031 {
1032         dma_addr_t offset = 0;
1033
1034         if (cpu_is_omap15xx())
1035                 offset = dma_read(CPC(lch));
1036         else
1037                 offset = dma_read(CDAC(lch));
1038
1039         /*
1040          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1041          * read before the DMA controller finished disabling the channel.
1042          */
1043         if (!cpu_is_omap15xx() && offset == 0)
1044                 offset = dma_read(CDAC(lch));
1045
1046         if (cpu_class_is_omap1())
1047                 offset |= (dma_read(CDSA_U(lch)) << 16);
1048
1049         return offset;
1050 }
1051
1052 /*
1053  * Returns current source transfer counting for the given DMA channel.
1054  * Can be used to monitor the progress of a transfer inside a block.
1055  * It must be called with disabled interrupts.
1056  */
1057 int omap_get_dma_src_addr_counter(int lch)
1058 {
1059         return (dma_addr_t)dma_read(CSAC(lch));
1060 }
1061
1062 int omap_get_dma_active_status(int lch)
1063 {
1064         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1065 }
1066 EXPORT_SYMBOL(omap_get_dma_active_status);
1067
1068 int omap_dma_running(void)
1069 {
1070         int lch;
1071
1072         /* Check if LCD DMA is running */
1073         if (cpu_is_omap16xx())
1074                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1075                         return 1;
1076
1077         for (lch = 0; lch < dma_chan_count; lch++)
1078                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1079                         return 1;
1080
1081         return 0;
1082 }
1083
1084 /*
1085  * lch_queue DMA will start right after lch_head one is finished.
1086  * For this DMA link to start, you still need to start (see omap_start_dma)
1087  * the first one. That will fire up the entire queue.
1088  */
1089 void omap_dma_link_lch (int lch_head, int lch_queue)
1090 {
1091         if (omap_dma_in_1510_mode()) {
1092                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1093                 BUG();
1094                 return;
1095         }
1096
1097         if ((dma_chan[lch_head].dev_id == -1) ||
1098             (dma_chan[lch_queue].dev_id == -1)) {
1099                 printk(KERN_ERR "omap_dma: trying to link "
1100                        "non requested channels\n");
1101                 dump_stack();
1102         }
1103
1104         dma_chan[lch_head].next_lch = lch_queue;
1105 }
1106
1107 /*
1108  * Once the DMA queue is stopped, we can destroy it.
1109  */
1110 void omap_dma_unlink_lch (int lch_head, int lch_queue)
1111 {
1112         if (omap_dma_in_1510_mode()) {
1113                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1114                 BUG();
1115                 return;
1116         }
1117
1118         if (dma_chan[lch_head].next_lch != lch_queue ||
1119             dma_chan[lch_head].next_lch == -1) {
1120                 printk(KERN_ERR "omap_dma: trying to unlink "
1121                        "non linked channels\n");
1122                 dump_stack();
1123         }
1124
1125
1126         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1127             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1128                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1129                        "before unlinking\n");
1130                 dump_stack();
1131         }
1132
1133         dma_chan[lch_head].next_lch = -1;
1134 }
1135
1136 #ifndef CONFIG_ARCH_OMAP1
1137 /* Create chain of DMA channesls */
1138 static void create_dma_lch_chain(int lch_head, int lch_queue)
1139 {
1140         u32 l;
1141
1142         /* Check if this is the first link in chain */
1143         if (dma_chan[lch_head].next_linked_ch == -1) {
1144                 dma_chan[lch_head].next_linked_ch = lch_queue;
1145                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1146                 dma_chan[lch_queue].next_linked_ch = lch_head;
1147                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1148         }
1149
1150         /* a link exists, link the new channel in circular chain */
1151         else {
1152                 dma_chan[lch_queue].next_linked_ch =
1153                                         dma_chan[lch_head].next_linked_ch;
1154                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1155                 dma_chan[lch_head].next_linked_ch = lch_queue;
1156                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1157                                         lch_queue;
1158         }
1159
1160         l = dma_read(CLNK_CTRL(lch_head));
1161         l &= ~(0x1f);
1162         l |= lch_queue;
1163         dma_write(l, CLNK_CTRL(lch_head));
1164
1165         l = dma_read(CLNK_CTRL(lch_queue));
1166         l &= ~(0x1f);
1167         l |= (dma_chan[lch_queue].next_linked_ch);
1168         dma_write(l, CLNK_CTRL(lch_queue));
1169 }
1170
1171 /**
1172  * @brief omap_request_dma_chain : Request a chain of DMA channels
1173  *
1174  * @param dev_id - Device id using the dma channel
1175  * @param dev_name - Device name
1176  * @param callback - Call back function
1177  * @chain_id -
1178  * @no_of_chans - Number of channels requested
1179  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1180  *                                            OMAP_DMA_DYNAMIC_CHAIN
1181  * @params - Channel parameters
1182  *
1183  * @return - Succes : 0
1184  *           Failure: -EINVAL/-ENOMEM
1185  */
1186 int omap_request_dma_chain(int dev_id, const char *dev_name,
1187                            void (*callback) (int chain_id, u16 ch_status,
1188                                              void *data),
1189                            int *chain_id, int no_of_chans, int chain_mode,
1190                            struct omap_dma_channel_params params)
1191 {
1192         int *channels;
1193         int i, err;
1194
1195         /* Is the chain mode valid ? */
1196         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1197                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1198                 printk(KERN_ERR "Invalid chain mode requested\n");
1199                 return -EINVAL;
1200         }
1201
1202         if (unlikely((no_of_chans < 1
1203                         || no_of_chans > dma_lch_count))) {
1204                 printk(KERN_ERR "Invalid Number of channels requested\n");
1205                 return -EINVAL;
1206         }
1207
1208         /* Allocate a queue to maintain the status of the channels
1209          * in the chain */
1210         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1211         if (channels == NULL) {
1212                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1213                 return -ENOMEM;
1214         }
1215
1216         /* request and reserve DMA channels for the chain */
1217         for (i = 0; i < no_of_chans; i++) {
1218                 err = omap_request_dma(dev_id, dev_name,
1219                                         callback, 0, &channels[i]);
1220                 if (err < 0) {
1221                         int j;
1222                         for (j = 0; j < i; j++)
1223                                 omap_free_dma(channels[j]);
1224                         kfree(channels);
1225                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1226                         return err;
1227                 }
1228                 dma_chan[channels[i]].prev_linked_ch = -1;
1229                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1230
1231                 /*
1232                  * Allowing client drivers to set common parameters now,
1233                  * so that later only relevant (src_start, dest_start
1234                  * and element count) can be set
1235                  */
1236                 omap_set_dma_params(channels[i], &params);
1237         }
1238
1239         *chain_id = channels[0];
1240         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1241         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1242         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1243         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1244
1245         for (i = 0; i < no_of_chans; i++)
1246                 dma_chan[channels[i]].chain_id = *chain_id;
1247
1248         /* Reset the Queue pointers */
1249         OMAP_DMA_CHAIN_QINIT(*chain_id);
1250
1251         /* Set up the chain */
1252         if (no_of_chans == 1)
1253                 create_dma_lch_chain(channels[0], channels[0]);
1254         else {
1255                 for (i = 0; i < (no_of_chans - 1); i++)
1256                         create_dma_lch_chain(channels[i], channels[i + 1]);
1257         }
1258         return 0;
1259 }
1260 EXPORT_SYMBOL(omap_request_dma_chain);
1261
1262 /**
1263  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1264  * params after setting it. Dont do this while dma is running!!
1265  *
1266  * @param chain_id - Chained logical channel id.
1267  * @param params
1268  *
1269  * @return - Success : 0
1270  *           Failure : -EINVAL
1271  */
1272 int omap_modify_dma_chain_params(int chain_id,
1273                                 struct omap_dma_channel_params params)
1274 {
1275         int *channels;
1276         u32 i;
1277
1278         /* Check for input params */
1279         if (unlikely((chain_id < 0
1280                         || chain_id >= dma_lch_count))) {
1281                 printk(KERN_ERR "Invalid chain id\n");
1282                 return -EINVAL;
1283         }
1284
1285         /* Check if the chain exists */
1286         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1287                 printk(KERN_ERR "Chain doesn't exists\n");
1288                 return -EINVAL;
1289         }
1290         channels = dma_linked_lch[chain_id].linked_dmach_q;
1291
1292         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1293                 /*
1294                  * Allowing client drivers to set common parameters now,
1295                  * so that later only relevant (src_start, dest_start
1296                  * and element count) can be set
1297                  */
1298                 omap_set_dma_params(channels[i], &params);
1299         }
1300         return 0;
1301 }
1302 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1303
1304 /**
1305  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1306  *
1307  * @param chain_id
1308  *
1309  * @return - Success : 0
1310  *           Failure : -EINVAL
1311  */
1312 int omap_free_dma_chain(int chain_id)
1313 {
1314         int *channels;
1315         u32 i;
1316
1317         /* Check for input params */
1318         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1319                 printk(KERN_ERR "Invalid chain id\n");
1320                 return -EINVAL;
1321         }
1322
1323         /* Check if the chain exists */
1324         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1325                 printk(KERN_ERR "Chain doesn't exists\n");
1326                 return -EINVAL;
1327         }
1328
1329         channels = dma_linked_lch[chain_id].linked_dmach_q;
1330         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1331                 dma_chan[channels[i]].next_linked_ch = -1;
1332                 dma_chan[channels[i]].prev_linked_ch = -1;
1333                 dma_chan[channels[i]].chain_id = -1;
1334                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1335                 omap_free_dma(channels[i]);
1336         }
1337
1338         kfree(channels);
1339
1340         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1341         dma_linked_lch[chain_id].chain_mode = -1;
1342         dma_linked_lch[chain_id].chain_state = -1;
1343         return (0);
1344 }
1345 EXPORT_SYMBOL(omap_free_dma_chain);
1346
1347 /**
1348  * @brief omap_dma_chain_status - Check if the chain is in
1349  * active / inactive state.
1350  * @param chain_id
1351  *
1352  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1353  *           Failure : -EINVAL
1354  */
1355 int omap_dma_chain_status(int chain_id)
1356 {
1357         /* Check for input params */
1358         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1359                 printk(KERN_ERR "Invalid chain id\n");
1360                 return -EINVAL;
1361         }
1362
1363         /* Check if the chain exists */
1364         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1365                 printk(KERN_ERR "Chain doesn't exists\n");
1366                 return -EINVAL;
1367         }
1368         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1369                         dma_linked_lch[chain_id].q_count);
1370
1371         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1372                 return OMAP_DMA_CHAIN_INACTIVE;
1373         return OMAP_DMA_CHAIN_ACTIVE;
1374 }
1375 EXPORT_SYMBOL(omap_dma_chain_status);
1376
1377 /**
1378  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1379  * set the params and start the transfer.
1380  *
1381  * @param chain_id
1382  * @param src_start - buffer start address
1383  * @param dest_start - Dest address
1384  * @param elem_count
1385  * @param frame_count
1386  * @param callbk_data - channel callback parameter data.
1387  *
1388  * @return  - Success : 0
1389  *            Failure: -EINVAL/-EBUSY
1390  */
1391 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1392                         int elem_count, int frame_count, void *callbk_data)
1393 {
1394         int *channels;
1395         u32 l, lch;
1396         int start_dma = 0;
1397
1398         /* if buffer size is less than 1 then there is
1399          * no use of starting the chain */
1400         if (elem_count < 1) {
1401                 printk(KERN_ERR "Invalid buffer size\n");
1402                 return -EINVAL;
1403         }
1404
1405         /* Check for input params */
1406         if (unlikely((chain_id < 0
1407                         || chain_id >= dma_lch_count))) {
1408                 printk(KERN_ERR "Invalid chain id\n");
1409                 return -EINVAL;
1410         }
1411
1412         /* Check if the chain exists */
1413         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1414                 printk(KERN_ERR "Chain doesn't exist\n");
1415                 return -EINVAL;
1416         }
1417
1418         /* Check if all the channels in chain are in use */
1419         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1420                 return -EBUSY;
1421
1422         /* Frame count may be negative in case of indexed transfers */
1423         channels = dma_linked_lch[chain_id].linked_dmach_q;
1424
1425         /* Get a free channel */
1426         lch = channels[dma_linked_lch[chain_id].q_tail];
1427
1428         /* Store the callback data */
1429         dma_chan[lch].data = callbk_data;
1430
1431         /* Increment the q_tail */
1432         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1433
1434         /* Set the params to the free channel */
1435         if (src_start != 0)
1436                 dma_write(src_start, CSSA(lch));
1437         if (dest_start != 0)
1438                 dma_write(dest_start, CDSA(lch));
1439
1440         /* Write the buffer size */
1441         dma_write(elem_count, CEN(lch));
1442         dma_write(frame_count, CFN(lch));
1443
1444         /* If the chain is dynamically linked,
1445          * then we may have to start the chain if its not active */
1446         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1447
1448                 /* In Dynamic chain, if the chain is not started,
1449                  * queue the channel */
1450                 if (dma_linked_lch[chain_id].chain_state ==
1451                                                 DMA_CHAIN_NOTSTARTED) {
1452                         /* Enable the link in previous channel */
1453                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1454                                                                 DMA_CH_QUEUED)
1455                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1456                         dma_chan[lch].state = DMA_CH_QUEUED;
1457                 }
1458
1459                 /* Chain is already started, make sure its active,
1460                  * if not then start the chain */
1461                 else {
1462                         start_dma = 1;
1463
1464                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1465                                                         DMA_CH_STARTED) {
1466                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1467                                 dma_chan[lch].state = DMA_CH_QUEUED;
1468                                 start_dma = 0;
1469                                 if (0 == ((1 << 7) & dma_read(
1470                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1471                                         disable_lnk(dma_chan[lch].
1472                                                     prev_linked_ch);
1473                                         pr_debug("\n prev ch is stopped\n");
1474                                         start_dma = 1;
1475                                 }
1476                         }
1477
1478                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1479                                                         == DMA_CH_QUEUED) {
1480                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1481                                 dma_chan[lch].state = DMA_CH_QUEUED;
1482                                 start_dma = 0;
1483                         }
1484                         omap_enable_channel_irq(lch);
1485
1486                         l = dma_read(CCR(lch));
1487
1488                         if ((0 == (l & (1 << 24))))
1489                                 l &= ~(1 << 25);
1490                         else
1491                                 l |= (1 << 25);
1492                         if (start_dma == 1) {
1493                                 if (0 == (l & (1 << 7))) {
1494                                         l |= (1 << 7);
1495                                         dma_chan[lch].state = DMA_CH_STARTED;
1496                                         pr_debug("starting %d\n", lch);
1497                                         dma_write(l, CCR(lch));
1498                                 } else
1499                                         start_dma = 0;
1500                         } else {
1501                                 if (0 == (l & (1 << 7)))
1502                                         dma_write(l, CCR(lch));
1503                         }
1504                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1505                 }
1506         }
1507         return 0;
1508 }
1509 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1510
1511 /**
1512  * @brief omap_start_dma_chain_transfers - Start the chain
1513  *
1514  * @param chain_id
1515  *
1516  * @return - Success : 0
1517  *           Failure : -EINVAL/-EBUSY
1518  */
1519 int omap_start_dma_chain_transfers(int chain_id)
1520 {
1521         int *channels;
1522         u32 l, i;
1523
1524         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1525                 printk(KERN_ERR "Invalid chain id\n");
1526                 return -EINVAL;
1527         }
1528
1529         channels = dma_linked_lch[chain_id].linked_dmach_q;
1530
1531         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1532                 printk(KERN_ERR "Chain is already started\n");
1533                 return -EBUSY;
1534         }
1535
1536         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1537                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1538                                                                         i++) {
1539                         enable_lnk(channels[i]);
1540                         omap_enable_channel_irq(channels[i]);
1541                 }
1542         } else {
1543                 omap_enable_channel_irq(channels[0]);
1544         }
1545
1546         l = dma_read(CCR(channels[0]));
1547         l |= (1 << 7);
1548         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1549         dma_chan[channels[0]].state = DMA_CH_STARTED;
1550
1551         if ((0 == (l & (1 << 24))))
1552                 l &= ~(1 << 25);
1553         else
1554                 l |= (1 << 25);
1555         dma_write(l, CCR(channels[0]));
1556
1557         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1558         return 0;
1559 }
1560 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1561
1562 /**
1563  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1564  *
1565  * @param chain_id
1566  *
1567  * @return - Success : 0
1568  *           Failure : EINVAL
1569  */
1570 int omap_stop_dma_chain_transfers(int chain_id)
1571 {
1572         int *channels;
1573         u32 l, i;
1574         u32 sys_cf;
1575
1576         /* Check for input params */
1577         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1578                 printk(KERN_ERR "Invalid chain id\n");
1579                 return -EINVAL;
1580         }
1581
1582         /* Check if the chain exists */
1583         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1584                 printk(KERN_ERR "Chain doesn't exists\n");
1585                 return -EINVAL;
1586         }
1587         channels = dma_linked_lch[chain_id].linked_dmach_q;
1588
1589         /* DMA Errata:
1590          * Special programming model needed to disable DMA before end of block
1591          */
1592         sys_cf = dma_read(OCP_SYSCONFIG);
1593         l = sys_cf;
1594         /* Middle mode reg set no Standby */
1595         l &= ~((1 << 12)|(1 << 13));
1596         dma_write(l, OCP_SYSCONFIG);
1597
1598         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1599
1600                 /* Stop the Channel transmission */
1601                 l = dma_read(CCR(channels[i]));
1602                 l &= ~(1 << 7);
1603                 dma_write(l, CCR(channels[i]));
1604
1605                 /* Disable the link in all the channels */
1606                 disable_lnk(channels[i]);
1607                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1608
1609         }
1610         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1611
1612         /* Reset the Queue pointers */
1613         OMAP_DMA_CHAIN_QINIT(chain_id);
1614
1615         /* Errata - put in the old value */
1616         dma_write(sys_cf, OCP_SYSCONFIG);
1617         return 0;
1618 }
1619 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1620
1621 /* Get the index of the ongoing DMA in chain */
1622 /**
1623  * @brief omap_get_dma_chain_index - Get the element and frame index
1624  * of the ongoing DMA in chain
1625  *
1626  * @param chain_id
1627  * @param ei - Element index
1628  * @param fi - Frame index
1629  *
1630  * @return - Success : 0
1631  *           Failure : -EINVAL
1632  */
1633 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1634 {
1635         int lch;
1636         int *channels;
1637
1638         /* Check for input params */
1639         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1640                 printk(KERN_ERR "Invalid chain id\n");
1641                 return -EINVAL;
1642         }
1643
1644         /* Check if the chain exists */
1645         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1646                 printk(KERN_ERR "Chain doesn't exists\n");
1647                 return -EINVAL;
1648         }
1649         if ((!ei) || (!fi))
1650                 return -EINVAL;
1651
1652         channels = dma_linked_lch[chain_id].linked_dmach_q;
1653
1654         /* Get the current channel */
1655         lch = channels[dma_linked_lch[chain_id].q_head];
1656
1657         *ei = dma_read(CCEN(lch));
1658         *fi = dma_read(CCFN(lch));
1659
1660         return 0;
1661 }
1662 EXPORT_SYMBOL(omap_get_dma_chain_index);
1663
1664 /**
1665  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1666  * ongoing DMA in chain
1667  *
1668  * @param chain_id
1669  *
1670  * @return - Success : Destination position
1671  *           Failure : -EINVAL
1672  */
1673 int omap_get_dma_chain_dst_pos(int chain_id)
1674 {
1675         int lch;
1676         int *channels;
1677
1678         /* Check for input params */
1679         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1680                 printk(KERN_ERR "Invalid chain id\n");
1681                 return -EINVAL;
1682         }
1683
1684         /* Check if the chain exists */
1685         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1686                 printk(KERN_ERR "Chain doesn't exists\n");
1687                 return -EINVAL;
1688         }
1689
1690         channels = dma_linked_lch[chain_id].linked_dmach_q;
1691
1692         /* Get the current channel */
1693         lch = channels[dma_linked_lch[chain_id].q_head];
1694
1695         return dma_read(CDAC(lch));
1696 }
1697 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1698
1699 /**
1700  * @brief omap_get_dma_chain_src_pos - Get the source position
1701  * of the ongoing DMA in chain
1702  * @param chain_id
1703  *
1704  * @return - Success : Destination position
1705  *           Failure : -EINVAL
1706  */
1707 int omap_get_dma_chain_src_pos(int chain_id)
1708 {
1709         int lch;
1710         int *channels;
1711
1712         /* Check for input params */
1713         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1714                 printk(KERN_ERR "Invalid chain id\n");
1715                 return -EINVAL;
1716         }
1717
1718         /* Check if the chain exists */
1719         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1720                 printk(KERN_ERR "Chain doesn't exists\n");
1721                 return -EINVAL;
1722         }
1723
1724         channels = dma_linked_lch[chain_id].linked_dmach_q;
1725
1726         /* Get the current channel */
1727         lch = channels[dma_linked_lch[chain_id].q_head];
1728
1729         return dma_read(CSAC(lch));
1730 }
1731 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1732 #endif
1733
1734 /*----------------------------------------------------------------------------*/
1735
1736 #ifdef CONFIG_ARCH_OMAP1
1737
1738 static int omap1_dma_handle_ch(int ch)
1739 {
1740         u32 csr;
1741
1742         if (enable_1510_mode && ch >= 6) {
1743                 csr = dma_chan[ch].saved_csr;
1744                 dma_chan[ch].saved_csr = 0;
1745         } else
1746                 csr = dma_read(CSR(ch));
1747         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1748                 dma_chan[ch + 6].saved_csr = csr >> 7;
1749                 csr &= 0x7f;
1750         }
1751         if ((csr & 0x3f) == 0)
1752                 return 0;
1753         if (unlikely(dma_chan[ch].dev_id == -1)) {
1754                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1755                        "%d (CSR %04x)\n", ch, csr);
1756                 return 0;
1757         }
1758         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1759                 printk(KERN_WARNING "DMA timeout with device %d\n",
1760                        dma_chan[ch].dev_id);
1761         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1762                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1763                        "with device %d\n", dma_chan[ch].dev_id);
1764         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1765                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1766         if (likely(dma_chan[ch].callback != NULL))
1767                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1768         return 1;
1769 }
1770
1771 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1772 {
1773         int ch = ((int) dev_id) - 1;
1774         int handled = 0;
1775
1776         for (;;) {
1777                 int handled_now = 0;
1778
1779                 handled_now += omap1_dma_handle_ch(ch);
1780                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1781                         handled_now += omap1_dma_handle_ch(ch + 6);
1782                 if (!handled_now)
1783                         break;
1784                 handled += handled_now;
1785         }
1786
1787         return handled ? IRQ_HANDLED : IRQ_NONE;
1788 }
1789
1790 #else
1791 #define omap1_dma_irq_handler   NULL
1792 #endif
1793
1794 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1795
1796 static int omap2_dma_handle_ch(int ch)
1797 {
1798         u32 status = dma_read(CSR(ch));
1799
1800         if (!status) {
1801                 if (printk_ratelimit())
1802                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
1803                 dma_write(1 << ch, IRQSTATUS_L0);
1804                 return 0;
1805         }
1806         if (unlikely(dma_chan[ch].dev_id == -1)) {
1807                 if (printk_ratelimit())
1808                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1809                                         "channel %d\n", status, ch);
1810                 return 0;
1811         }
1812         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1813                 printk(KERN_INFO
1814                        "DMA synchronization event drop occurred with device "
1815                        "%d\n", dma_chan[ch].dev_id);
1816         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1817                 printk(KERN_INFO "DMA transaction error with device %d\n",
1818                        dma_chan[ch].dev_id);
1819         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1820                 printk(KERN_INFO "DMA secure error with device %d\n",
1821                        dma_chan[ch].dev_id);
1822         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1823                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1824                        dma_chan[ch].dev_id);
1825
1826         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1827         dma_write(1 << ch, IRQSTATUS_L0);
1828
1829         /* If the ch is not chained then chain_id will be -1 */
1830         if (dma_chan[ch].chain_id != -1) {
1831                 int chain_id = dma_chan[ch].chain_id;
1832                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1833                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1834                         dma_chan[dma_chan[ch].next_linked_ch].state =
1835                                                         DMA_CH_STARTED;
1836                 if (dma_linked_lch[chain_id].chain_mode ==
1837                                                 OMAP_DMA_DYNAMIC_CHAIN)
1838                         disable_lnk(ch);
1839
1840                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1841                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1842
1843                 status = dma_read(CSR(ch));
1844         }
1845
1846         if (likely(dma_chan[ch].callback != NULL))
1847                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1848
1849         dma_write(status, CSR(ch));
1850
1851         return 0;
1852 }
1853
1854 /* STATUS register count is from 1-32 while our is 0-31 */
1855 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1856 {
1857         u32 val;
1858         int i;
1859
1860         val = dma_read(IRQSTATUS_L0);
1861         if (val == 0) {
1862                 if (printk_ratelimit())
1863                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1864                 return IRQ_HANDLED;
1865         }
1866         for (i = 0; i < dma_lch_count && val != 0; i++) {
1867                 if (val & 1)
1868                         omap2_dma_handle_ch(i);
1869                 val >>= 1;
1870         }
1871
1872         return IRQ_HANDLED;
1873 }
1874
1875 static struct irqaction omap24xx_dma_irq = {
1876         .name = "DMA",
1877         .handler = omap2_dma_irq_handler,
1878         .flags = IRQF_DISABLED
1879 };
1880
1881 #else
1882 static struct irqaction omap24xx_dma_irq;
1883 #endif
1884
1885 /*----------------------------------------------------------------------------*/
1886
1887 static struct lcd_dma_info {
1888         spinlock_t lock;
1889         int reserved;
1890         void (* callback)(u16 status, void *data);
1891         void *cb_data;
1892
1893         int active;
1894         unsigned long addr, size;
1895         int rotate, data_type, xres, yres;
1896         int vxres;
1897         int mirror;
1898         int xscale, yscale;
1899         int ext_ctrl;
1900         int src_port;
1901         int single_transfer;
1902 } lcd_dma;
1903
1904 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1905                          int data_type)
1906 {
1907         lcd_dma.addr = addr;
1908         lcd_dma.data_type = data_type;
1909         lcd_dma.xres = fb_xres;
1910         lcd_dma.yres = fb_yres;
1911 }
1912
1913 void omap_set_lcd_dma_src_port(int port)
1914 {
1915         lcd_dma.src_port = port;
1916 }
1917
1918 void omap_set_lcd_dma_ext_controller(int external)
1919 {
1920         lcd_dma.ext_ctrl = external;
1921 }
1922
1923 void omap_set_lcd_dma_single_transfer(int single)
1924 {
1925         lcd_dma.single_transfer = single;
1926 }
1927
1928
1929 void omap_set_lcd_dma_b1_rotation(int rotate)
1930 {
1931         if (omap_dma_in_1510_mode()) {
1932                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1933                 BUG();
1934                 return;
1935         }
1936         lcd_dma.rotate = rotate;
1937 }
1938
1939 void omap_set_lcd_dma_b1_mirror(int mirror)
1940 {
1941         if (omap_dma_in_1510_mode()) {
1942                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1943                 BUG();
1944         }
1945         lcd_dma.mirror = mirror;
1946 }
1947
1948 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1949 {
1950         if (omap_dma_in_1510_mode()) {
1951                 printk(KERN_ERR "DMA virtual resulotion is not supported "
1952                                 "in 1510 mode\n");
1953                 BUG();
1954         }
1955         lcd_dma.vxres = vxres;
1956 }
1957
1958 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1959 {
1960         if (omap_dma_in_1510_mode()) {
1961                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1962                 BUG();
1963         }
1964         lcd_dma.xscale = xscale;
1965         lcd_dma.yscale = yscale;
1966 }
1967
1968 static void set_b1_regs(void)
1969 {
1970         unsigned long top, bottom;
1971         int es;
1972         u16 w;
1973         unsigned long en, fn;
1974         long ei, fi;
1975         unsigned long vxres;
1976         unsigned int xscale, yscale;
1977
1978         switch (lcd_dma.data_type) {
1979         case OMAP_DMA_DATA_TYPE_S8:
1980                 es = 1;
1981                 break;
1982         case OMAP_DMA_DATA_TYPE_S16:
1983                 es = 2;
1984                 break;
1985         case OMAP_DMA_DATA_TYPE_S32:
1986                 es = 4;
1987                 break;
1988         default:
1989                 BUG();
1990                 return;
1991         }
1992
1993         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1994         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1995         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1996         BUG_ON(vxres < lcd_dma.xres);
1997 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1998 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1999         switch (lcd_dma.rotate) {
2000         case 0:
2001                 if (!lcd_dma.mirror) {
2002                         top = PIXADDR(0, 0);
2003                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2004                         /* 1510 DMA requires the bottom address to be 2 more
2005                          * than the actual last memory access location. */
2006                         if (omap_dma_in_1510_mode() &&
2007                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2008                                 bottom += 2;
2009                         ei = PIXSTEP(0, 0, 1, 0);
2010                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2011                 } else {
2012                         top = PIXADDR(lcd_dma.xres - 1, 0);
2013                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2014                         ei = PIXSTEP(1, 0, 0, 0);
2015                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2016                 }
2017                 en = lcd_dma.xres;
2018                 fn = lcd_dma.yres;
2019                 break;
2020         case 90:
2021                 if (!lcd_dma.mirror) {
2022                         top = PIXADDR(0, lcd_dma.yres - 1);
2023                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2024                         ei = PIXSTEP(0, 1, 0, 0);
2025                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2026                 } else {
2027                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2028                         bottom = PIXADDR(0, 0);
2029                         ei = PIXSTEP(0, 1, 0, 0);
2030                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2031                 }
2032                 en = lcd_dma.yres;
2033                 fn = lcd_dma.xres;
2034                 break;
2035         case 180:
2036                 if (!lcd_dma.mirror) {
2037                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2038                         bottom = PIXADDR(0, 0);
2039                         ei = PIXSTEP(1, 0, 0, 0);
2040                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2041                 } else {
2042                         top = PIXADDR(0, lcd_dma.yres - 1);
2043                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2044                         ei = PIXSTEP(0, 0, 1, 0);
2045                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2046                 }
2047                 en = lcd_dma.xres;
2048                 fn = lcd_dma.yres;
2049                 break;
2050         case 270:
2051                 if (!lcd_dma.mirror) {
2052                         top = PIXADDR(lcd_dma.xres - 1, 0);
2053                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2054                         ei = PIXSTEP(0, 0, 0, 1);
2055                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2056                 } else {
2057                         top = PIXADDR(0, 0);
2058                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2059                         ei = PIXSTEP(0, 0, 0, 1);
2060                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2061                 }
2062                 en = lcd_dma.yres;
2063                 fn = lcd_dma.xres;
2064                 break;
2065         default:
2066                 BUG();
2067                 return; /* Suppress warning about uninitialized vars */
2068         }
2069
2070         if (omap_dma_in_1510_mode()) {
2071                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2072                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2073                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2074                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2075
2076                 return;
2077         }
2078
2079         /* 1610 regs */
2080         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2081         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2082         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2083         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2084
2085         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2086         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2087
2088         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2089         w &= ~0x03;
2090         w |= lcd_dma.data_type;
2091         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2092
2093         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2094         /* Always set the source port as SDRAM for now*/
2095         w &= ~(0x03 << 6);
2096         if (lcd_dma.callback != NULL)
2097                 w |= 1 << 1;            /* Block interrupt enable */
2098         else
2099                 w &= ~(1 << 1);
2100         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2101
2102         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2103               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2104                 return;
2105
2106         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2107         /* Set the double-indexed addressing mode */
2108         w |= (0x03 << 12);
2109         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2110
2111         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2112         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2113         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2114 }
2115
2116 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2117 {
2118         u16 w;
2119
2120         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2121         if (unlikely(!(w & (1 << 3)))) {
2122                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2123                 return IRQ_NONE;
2124         }
2125         /* Ack the IRQ */
2126         w |= (1 << 3);
2127         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2128         lcd_dma.active = 0;
2129         if (lcd_dma.callback != NULL)
2130                 lcd_dma.callback(w, lcd_dma.cb_data);
2131
2132         return IRQ_HANDLED;
2133 }
2134
2135 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2136                          void *data)
2137 {
2138         spin_lock_irq(&lcd_dma.lock);
2139         if (lcd_dma.reserved) {
2140                 spin_unlock_irq(&lcd_dma.lock);
2141                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2142                 BUG();
2143                 return -EBUSY;
2144         }
2145         lcd_dma.reserved = 1;
2146         spin_unlock_irq(&lcd_dma.lock);
2147         lcd_dma.callback = callback;
2148         lcd_dma.cb_data = data;
2149         lcd_dma.active = 0;
2150         lcd_dma.single_transfer = 0;
2151         lcd_dma.rotate = 0;
2152         lcd_dma.vxres = 0;
2153         lcd_dma.mirror = 0;
2154         lcd_dma.xscale = 0;
2155         lcd_dma.yscale = 0;
2156         lcd_dma.ext_ctrl = 0;
2157         lcd_dma.src_port = 0;
2158
2159         return 0;
2160 }
2161
2162 void omap_free_lcd_dma(void)
2163 {
2164         spin_lock(&lcd_dma.lock);
2165         if (!lcd_dma.reserved) {
2166                 spin_unlock(&lcd_dma.lock);
2167                 printk(KERN_ERR "LCD DMA is not reserved\n");
2168                 BUG();
2169                 return;
2170         }
2171         if (!enable_1510_mode)
2172                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2173                             OMAP1610_DMA_LCD_CCR);
2174         lcd_dma.reserved = 0;
2175         spin_unlock(&lcd_dma.lock);
2176 }
2177
2178 void omap_enable_lcd_dma(void)
2179 {
2180         u16 w;
2181
2182         /* Set the Enable bit only if an external controller is
2183          * connected. Otherwise the OMAP internal controller will
2184          * start the transfer when it gets enabled.
2185          */
2186         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2187                 return;
2188
2189         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2190         w |= 1 << 8;
2191         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2192
2193         lcd_dma.active = 1;
2194
2195         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2196         w |= 1 << 7;
2197         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2198 }
2199
2200 void omap_setup_lcd_dma(void)
2201 {
2202         BUG_ON(lcd_dma.active);
2203         if (!enable_1510_mode) {
2204                 /* Set some reasonable defaults */
2205                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2206                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2207                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2208         }
2209         set_b1_regs();
2210         if (!enable_1510_mode) {
2211                 u16 w;
2212
2213                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2214                 /* If DMA was already active set the end_prog bit to have
2215                  * the programmed register set loaded into the active
2216                  * register set.
2217                  */
2218                 w |= 1 << 11;           /* End_prog */
2219                 if (!lcd_dma.single_transfer)
2220                         w |= (3 << 8);  /* Auto_init, repeat */
2221                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2222         }
2223 }
2224
2225 void omap_stop_lcd_dma(void)
2226 {
2227         u16 w;
2228
2229         lcd_dma.active = 0;
2230         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2231                 return;
2232
2233         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2234         w &= ~(1 << 7);
2235         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2236
2237         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2238         w &= ~(1 << 8);
2239         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2240 }
2241
2242 /*----------------------------------------------------------------------------*/
2243
2244 static int __init omap_init_dma(void)
2245 {
2246         int ch, r;
2247
2248         if (cpu_class_is_omap1()) {
2249                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2250                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2251         } else if (cpu_is_omap24xx()) {
2252                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2253                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2254         } else if (cpu_is_omap34xx()) {
2255                 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2256                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2257         } else {
2258                 pr_err("DMA init failed for unsupported omap\n");
2259                 return -ENODEV;
2260         }
2261
2262         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2263                                 GFP_KERNEL);
2264         if (!dma_chan)
2265                 return -ENOMEM;
2266
2267         if (cpu_class_is_omap2()) {
2268                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2269                                                 dma_lch_count, GFP_KERNEL);
2270                 if (!dma_linked_lch) {
2271                         kfree(dma_chan);
2272                         return -ENOMEM;
2273                 }
2274         }
2275
2276         if (cpu_is_omap15xx()) {
2277                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2278                 dma_chan_count = 9;
2279                 enable_1510_mode = 1;
2280         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2281                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2282                        dma_read(HW_ID));
2283                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2284                        (dma_read(CAPS_0_U) << 16) |
2285                        dma_read(CAPS_0_L),
2286                        (dma_read(CAPS_1_U) << 16) |
2287                        dma_read(CAPS_1_L),
2288                        dma_read(CAPS_2), dma_read(CAPS_3),
2289                        dma_read(CAPS_4));
2290                 if (!enable_1510_mode) {
2291                         u16 w;
2292
2293                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2294                         w = dma_read(GSCR);
2295                         w |= 1 << 3;
2296                         dma_write(w, GSCR);
2297                         dma_chan_count = 16;
2298                 } else
2299                         dma_chan_count = 9;
2300                 if (cpu_is_omap16xx()) {
2301                         u16 w;
2302
2303                         /* this would prevent OMAP sleep */
2304                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2305                         w &= ~(1 << 8);
2306                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2307                 }
2308         } else if (cpu_class_is_omap2()) {
2309                 u8 revision = dma_read(REVISION) & 0xff;
2310                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2311                        revision >> 4, revision & 0xf);
2312                 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2313         } else {
2314                 dma_chan_count = 0;
2315                 return 0;
2316         }
2317
2318         spin_lock_init(&lcd_dma.lock);
2319         spin_lock_init(&dma_chan_lock);
2320
2321         for (ch = 0; ch < dma_chan_count; ch++) {
2322                 omap_clear_dma(ch);
2323                 dma_chan[ch].dev_id = -1;
2324                 dma_chan[ch].next_lch = -1;
2325
2326                 if (ch >= 6 && enable_1510_mode)
2327                         continue;
2328
2329                 if (cpu_class_is_omap1()) {
2330                         /* request_irq() doesn't like dev_id (ie. ch) being
2331                          * zero, so we have to kludge around this. */
2332                         r = request_irq(omap1_dma_irq[ch],
2333                                         omap1_dma_irq_handler, 0, "DMA",
2334                                         (void *) (ch + 1));
2335                         if (r != 0) {
2336                                 int i;
2337
2338                                 printk(KERN_ERR "unable to request IRQ %d "
2339                                        "for DMA (error %d)\n",
2340                                        omap1_dma_irq[ch], r);
2341                                 for (i = 0; i < ch; i++)
2342                                         free_irq(omap1_dma_irq[i],
2343                                                  (void *) (i + 1));
2344                                 return r;
2345                         }
2346                 }
2347         }
2348
2349         if (cpu_is_omap2430() || cpu_is_omap34xx())
2350                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2351                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2352
2353         if (cpu_class_is_omap2())
2354                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2355
2356         /* FIXME: Update LCD DMA to work on 24xx */
2357         if (cpu_class_is_omap1()) {
2358                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2359                                 "LCD DMA", NULL);
2360                 if (r != 0) {
2361                         int i;
2362
2363                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2364                                "(error %d)\n", r);
2365                         for (i = 0; i < dma_chan_count; i++)
2366                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2367                         return r;
2368                 }
2369         }
2370
2371         return 0;
2372 }
2373
2374 arch_initcall(omap_init_dma);
2375
2376 EXPORT_SYMBOL(omap_get_dma_src_pos);
2377 EXPORT_SYMBOL(omap_get_dma_dst_pos);
2378 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2379 EXPORT_SYMBOL(omap_clear_dma);
2380 EXPORT_SYMBOL(omap_set_dma_priority);
2381 EXPORT_SYMBOL(omap_request_dma);
2382 EXPORT_SYMBOL(omap_free_dma);
2383 EXPORT_SYMBOL(omap_start_dma);
2384 EXPORT_SYMBOL(omap_stop_dma);
2385 EXPORT_SYMBOL(omap_set_dma_callback);
2386 EXPORT_SYMBOL(omap_enable_dma_irq);
2387 EXPORT_SYMBOL(omap_disable_dma_irq);
2388
2389 EXPORT_SYMBOL(omap_set_dma_transfer_params);
2390 EXPORT_SYMBOL(omap_set_dma_color_mode);
2391 EXPORT_SYMBOL(omap_set_dma_write_mode);
2392
2393 EXPORT_SYMBOL(omap_set_dma_src_params);
2394 EXPORT_SYMBOL(omap_set_dma_src_index);
2395 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2396 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2397
2398 EXPORT_SYMBOL(omap_set_dma_dest_params);
2399 EXPORT_SYMBOL(omap_set_dma_dest_index);
2400 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2401 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2402
2403 EXPORT_SYMBOL(omap_set_dma_params);
2404
2405 EXPORT_SYMBOL(omap_dma_link_lch);
2406 EXPORT_SYMBOL(omap_dma_unlink_lch);
2407
2408 EXPORT_SYMBOL(omap_request_lcd_dma);
2409 EXPORT_SYMBOL(omap_free_lcd_dma);
2410 EXPORT_SYMBOL(omap_enable_lcd_dma);
2411 EXPORT_SYMBOL(omap_setup_lcd_dma);
2412 EXPORT_SYMBOL(omap_stop_lcd_dma);
2413 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2414 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2415 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2416 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2417 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2418 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2419 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2420