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   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 129         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 130         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 131         /* Virtual clocks */
 132         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 133         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 134         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 135         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
 136         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 137         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 138         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 139         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 140         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 141         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 142         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 143         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 144         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 145         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 146 };
 147
 148 static int omap1_clk_enable_generic(struct clk * clk);
 149 static int omap1_clk_enable(struct clk *clk);
 150 static void omap1_clk_disable_generic(struct clk * clk);
 151 static void omap1_clk_disable(struct clk *clk);
 152
 153 __u32 arm_idlect1_mask;
 154
 155 /*-------------------------------------------------------------------------
 156  * Omap1 specific clock functions
 157  *-------------------------------------------------------------------------*/
 158
 159 static unsigned long omap1_watchdog_recalc(struct clk *clk)
 160 {
 161         return clk->parent->rate / 14;
 162 }
 163
 164 static unsigned long omap1_uart_recalc(struct clk *clk)
 165 {
 166         unsigned int val = __raw_readl(clk->enable_reg);
 167         return val & clk->enable_bit ? 48000000 : 12000000;
 168 }
 169
 170 static unsigned long omap1_sossi_recalc(struct clk *clk)
 171 {
 172         u32 div = omap_readl(MOD_CONF_CTRL_1);
 173
 174         div = (div >> 17) & 0x7;
 175         div++;
 176
 177         return clk->parent->rate / div;
 178 }
 179
 180 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 181 {
 182         int retval;
 183
 184         retval = omap1_clk_enable(&api_ck.clk);
 185         if (!retval) {
 186                 retval = omap1_clk_enable_generic(clk);
 187                 omap1_clk_disable(&api_ck.clk);
 188         }
 189
 190         return retval;
 191 }
 192
 193 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 194 {
 195         if (omap1_clk_enable(&api_ck.clk) == 0) {
 196                 omap1_clk_disable_generic(clk);
 197                 omap1_clk_disable(&api_ck.clk);
 198         }
 199 }
 200
 201 static const struct clkops clkops_dspck = {
 202         .enable         = &omap1_clk_enable_dsp_domain,
 203         .disable        = &omap1_clk_disable_dsp_domain,
 204 };
 205
 206 static int omap1_clk_enable_uart_functional(struct clk *clk)
 207 {
 208         int ret;
 209         struct uart_clk *uclk;
 210
 211         ret = omap1_clk_enable_generic(clk);
 212         if (ret == 0) {
 213                 /* Set smart idle acknowledgement mode */
 214                 uclk = (struct uart_clk *)clk;
 215                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 216                             uclk->sysc_addr);
 217         }
 218
 219         return ret;
 220 }
 221
 222 static void omap1_clk_disable_uart_functional(struct clk *clk)
 223 {
 224         struct uart_clk *uclk;
 225
 226         /* Set force idle acknowledgement mode */
 227         uclk = (struct uart_clk *)clk;
 228         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 229
 230         omap1_clk_disable_generic(clk);
 231 }
 232
 233 static const struct clkops clkops_uart = {
 234         .enable         = &omap1_clk_enable_uart_functional,
 235         .disable        = &omap1_clk_disable_uart_functional,
 236 };
 237
 238 static void omap1_clk_allow_idle(struct clk *clk)
 239 {
 240         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 241
 242         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 243                 return;
 244
 245         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 246                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 247 }
 248
 249 static void omap1_clk_deny_idle(struct clk *clk)
 250 {
 251         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 252
 253         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 254                 return;
 255
 256         if (iclk->no_idle_count++ == 0)
 257                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 258 }
 259
 260 static __u16 verify_ckctl_value(__u16 newval)
 261 {
 262         /* This function checks for following limitations set
 263          * by the hardware (all conditions must be true):
 264          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 265          * ARM_CK >= TC_CK
 266          * DSP_CK >= TC_CK
 267          * DSPMMU_CK >= TC_CK
 268          *
 269          * In addition following rules are enforced:
 270          * LCD_CK <= TC_CK
 271          * ARMPER_CK <= TC_CK
 272          *
 273          * However, maximum frequencies are not checked for!
 274          */
 275         __u8 per_exp;
 276         __u8 lcd_exp;
 277         __u8 arm_exp;
 278         __u8 dsp_exp;
 279         __u8 tc_exp;
 280         __u8 dspmmu_exp;
 281
 282         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 283         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 284         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 285         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 286         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 287         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 288
 289         if (dspmmu_exp < dsp_exp)
 290                 dspmmu_exp = dsp_exp;
 291         if (dspmmu_exp > dsp_exp+1)
 292                 dspmmu_exp = dsp_exp+1;
 293         if (tc_exp < arm_exp)
 294                 tc_exp = arm_exp;
 295         if (tc_exp < dspmmu_exp)
 296                 tc_exp = dspmmu_exp;
 297         if (tc_exp > lcd_exp)
 298                 lcd_exp = tc_exp;
 299         if (tc_exp > per_exp)
 300                 per_exp = tc_exp;
 301
 302         newval &= 0xf000;
 303         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 304         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 305         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 306         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 307         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 308         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 309
 310         return newval;
 311 }
 312
 313 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 314 {
 315         /* Note: If target frequency is too low, this function will return 4,
 316          * which is invalid value. Caller must check for this value and act
 317          * accordingly.
 318          *
 319          * Note: This function does not check for following limitations set
 320          * by the hardware (all conditions must be true):
 321          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 322          * ARM_CK >= TC_CK
 323          * DSP_CK >= TC_CK
 324          * DSPMMU_CK >= TC_CK
 325          */
 326         unsigned long realrate;
 327         struct clk * parent;
 328         unsigned  dsor_exp;
 329
 330         parent = clk->parent;
 331         if (unlikely(parent == NULL))
 332                 return -EIO;
 333
 334         realrate = parent->rate;
 335         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 336                 if (realrate <= rate)
 337                         break;
 338
 339                 realrate /= 2;
 340         }
 341
 342         return dsor_exp;
 343 }
 344
 345 static unsigned long omap1_ckctl_recalc(struct clk *clk)
 346 {
 347         /* Calculate divisor encoded as 2-bit exponent */
 348         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 349
 350         return clk->parent->rate / dsor;
 351 }
 352
 353 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 354 {
 355         int dsor;
 356
 357         /* Calculate divisor encoded as 2-bit exponent
 358          *
 359          * The clock control bits are in DSP domain,
 360          * so api_ck is needed for access.
 361          * Note that DSP_CKCTL virt addr = phys addr, so
 362          * we must use __raw_readw() instead of omap_readw().
 363          */
 364         omap1_clk_enable(&api_ck.clk);
 365         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 366         omap1_clk_disable(&api_ck.clk);
 367
 368         return clk->parent->rate / dsor;
 369 }
 370
 371 /* MPU virtual clock functions */
 372 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 373 {
 374         /* Find the highest supported frequency <= rate and switch to it */
 375         struct mpu_rate * ptr;
 376
 377         if (clk != &virtual_ck_mpu)
 378                 return -EINVAL;
 379
 380         for (ptr = rate_table; ptr->rate; ptr++) {
 381                 if (ptr->xtal != ck_ref.rate)
 382                         continue;
 383
 384                 /* DPLL1 cannot be reprogrammed without risking system crash */
 385                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 386                         continue;
 387
 388                 /* Can check only after xtal frequency check */
 389                 if (ptr->rate <= rate)
 390                         break;
 391         }
 392
 393         if (!ptr->rate)
 394                 return -EINVAL;
 395
 396         /*
 397          * In most cases we should not need to reprogram DPLL.
 398          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 399          * (on 730, bit 13 must always be 1)
 400          */
 401         if (cpu_is_omap730())
 402                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 403         else
 404                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 405
 406         ck_dpll1.rate = ptr->pll_rate;
 407         return 0;
 408 }
 409
 410 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 411 {
 412         int dsor_exp;
 413         u16 regval;
 414
 415         dsor_exp = calc_dsor_exp(clk, rate);
 416         if (dsor_exp > 3)
 417                 dsor_exp = -EINVAL;
 418         if (dsor_exp < 0)
 419                 return dsor_exp;
 420
 421         regval = __raw_readw(DSP_CKCTL);
 422         regval &= ~(3 << clk->rate_offset);
 423         regval |= dsor_exp << clk->rate_offset;
 424         __raw_writew(regval, DSP_CKCTL);
 425         clk->rate = clk->parent->rate / (1 << dsor_exp);
 426
 427         return 0;
 428 }
 429
 430 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 431 {
 432         int dsor_exp = calc_dsor_exp(clk, rate);
 433         if (dsor_exp < 0)
 434                 return dsor_exp;
 435         if (dsor_exp > 3)
 436                 dsor_exp = 3;
 437         return clk->parent->rate / (1 << dsor_exp);
 438 }
 439
 440 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 441 {
 442         int dsor_exp;
 443         u16 regval;
 444
 445         dsor_exp = calc_dsor_exp(clk, rate);
 446         if (dsor_exp > 3)
 447                 dsor_exp = -EINVAL;
 448         if (dsor_exp < 0)
 449                 return dsor_exp;
 450
 451         regval = omap_readw(ARM_CKCTL);
 452         regval &= ~(3 << clk->rate_offset);
 453         regval |= dsor_exp << clk->rate_offset;
 454         regval = verify_ckctl_value(regval);
 455         omap_writew(regval, ARM_CKCTL);
 456         clk->rate = clk->parent->rate / (1 << dsor_exp);
 457         return 0;
 458 }
 459
 460 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 461 {
 462         /* Find the highest supported frequency <= rate */
 463         struct mpu_rate * ptr;
 464         long  highest_rate;
 465
 466         if (clk != &virtual_ck_mpu)
 467                 return -EINVAL;
 468
 469         highest_rate = -EINVAL;
 470
 471         for (ptr = rate_table; ptr->rate; ptr++) {
 472                 if (ptr->xtal != ck_ref.rate)
 473                         continue;
 474
 475                 highest_rate = ptr->rate;
 476
 477                 /* Can check only after xtal frequency check */
 478                 if (ptr->rate <= rate)
 479                         break;
 480         }
 481
 482         return highest_rate;
 483 }
 484
 485 static unsigned calc_ext_dsor(unsigned long rate)
 486 {
 487         unsigned dsor;
 488
 489         /* MCLK and BCLK divisor selection is not linear:
 490          * freq = 96MHz / dsor
 491          *
 492          * RATIO_SEL range: dsor <-> RATIO_SEL
 493          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 494          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 495          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 496          * can not be used.
 497          */
 498         for (dsor = 2; dsor < 96; ++dsor) {
 499                 if ((dsor & 1) && dsor > 8)
 500                         continue;
 501                 if (rate >= 96000000 / dsor)
 502                         break;
 503         }
 504         return dsor;
 505 }
 506
 507 /* Only needed on 1510 */
 508 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 509 {
 510         unsigned int val;
 511
 512         val = __raw_readl(clk->enable_reg);
 513         if (rate == 12000000)
 514                 val &= ~(1 << clk->enable_bit);
 515         else if (rate == 48000000)
 516                 val |= (1 << clk->enable_bit);
 517         else
 518                 return -EINVAL;
 519         __raw_writel(val, clk->enable_reg);
 520         clk->rate = rate;
 521
 522         return 0;
 523 }
 524
 525 /* External clock (MCLK & BCLK) functions */
 526 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 527 {
 528         unsigned dsor;
 529         __u16 ratio_bits;
 530
 531         dsor = calc_ext_dsor(rate);
 532         clk->rate = 96000000 / dsor;
 533         if (dsor > 8)
 534                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 535         else
 536                 ratio_bits = (dsor - 2) << 2;
 537
 538         ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
 539         __raw_writew(ratio_bits, clk->enable_reg);
 540
 541         return 0;
 542 }
 543
 544 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 545 {
 546         u32 l;
 547         int div;
 548         unsigned long p_rate;
 549
 550         p_rate = clk->parent->rate;
 551         /* Round towards slower frequency */
 552         div = (p_rate + rate - 1) / rate;
 553         div--;
 554         if (div < 0 || div > 7)
 555                 return -EINVAL;
 556
 557         l = omap_readl(MOD_CONF_CTRL_1);
 558         l &= ~(7 << 17);
 559         l |= div << 17;
 560         omap_writel(l, MOD_CONF_CTRL_1);
 561
 562         clk->rate = p_rate / (div + 1);
 563
 564         return 0;
 565 }
 566
 567 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 568 {
 569         return 96000000 / calc_ext_dsor(rate);
 570 }
 571
 572 static void omap1_init_ext_clk(struct clk * clk)
 573 {
 574         unsigned dsor;
 575         __u16 ratio_bits;
 576
 577         /* Determine current rate and ensure clock is based on 96MHz APLL */
 578         ratio_bits = __raw_readw(clk->enable_reg) & ~1;
 579         __raw_writew(ratio_bits, clk->enable_reg);
 580
 581         ratio_bits = (ratio_bits & 0xfc) >> 2;
 582         if (ratio_bits > 6)
 583                 dsor = (ratio_bits - 6) * 2 + 8;
 584         else
 585                 dsor = ratio_bits + 2;
 586
 587         clk-> rate = 96000000 / dsor;
 588 }
 589
 590 static int omap1_clk_enable(struct clk *clk)
 591 {
 592         int ret = 0;
 593
 594         if (clk->usecount++ == 0) {
 595                 if (clk->parent) {
 596                         ret = omap1_clk_enable(clk->parent);
 597                         if (ret)
 598                                 goto err;
 599
 600                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 601                                 omap1_clk_deny_idle(clk->parent);
 602                 }
 603
 604                 ret = clk->ops->enable(clk);
 605                 if (ret) {
 606                         if (clk->parent)
 607                                 omap1_clk_disable(clk->parent);
 608                         goto err;
 609                 }
 610         }
 611         return ret;
 612
 613 err:
 614         clk->usecount--;
 615         return ret;
 616 }
 617
 618 static void omap1_clk_disable(struct clk *clk)
 619 {
 620         if (clk->usecount > 0 && !(--clk->usecount)) {
 621                 clk->ops->disable(clk);
 622                 if (likely(clk->parent)) {
 623                         omap1_clk_disable(clk->parent);
 624                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 625                                 omap1_clk_allow_idle(clk->parent);
 626                 }
 627         }
 628 }
 629
 630 static int omap1_clk_enable_generic(struct clk *clk)
 631 {
 632         __u16 regval16;
 633         __u32 regval32;
 634
 635         if (unlikely(clk->enable_reg == NULL)) {
 636                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 637                        clk->name);
 638                 return -EINVAL;
 639         }
 640
 641         if (clk->flags & ENABLE_REG_32BIT) {
 642                 regval32 = __raw_readl(clk->enable_reg);
 643                 regval32 |= (1 << clk->enable_bit);
 644                 __raw_writel(regval32, clk->enable_reg);
 645         } else {
 646                 regval16 = __raw_readw(clk->enable_reg);
 647                 regval16 |= (1 << clk->enable_bit);
 648                 __raw_writew(regval16, clk->enable_reg);
 649         }
 650
 651         return 0;
 652 }
 653
 654 static void omap1_clk_disable_generic(struct clk *clk)
 655 {
 656         __u16 regval16;
 657         __u32 regval32;
 658
 659         if (clk->enable_reg == NULL)
 660                 return;
 661
 662         if (clk->flags & ENABLE_REG_32BIT) {
 663                 regval32 = __raw_readl(clk->enable_reg);
 664                 regval32 &= ~(1 << clk->enable_bit);
 665                 __raw_writel(regval32, clk->enable_reg);
 666         } else {
 667                 regval16 = __raw_readw(clk->enable_reg);
 668                 regval16 &= ~(1 << clk->enable_bit);
 669                 __raw_writew(regval16, clk->enable_reg);
 670         }
 671 }
 672
 673 static const struct clkops clkops_generic = {
 674         .enable         = &omap1_clk_enable_generic,
 675         .disable        = &omap1_clk_disable_generic,
 676 };
 677
 678 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 679 {
 680         if (clk->flags & RATE_FIXED)
 681                 return clk->rate;
 682
 683         if (clk->round_rate != NULL)
 684                 return clk->round_rate(clk, rate);
 685
 686         return clk->rate;
 687 }
 688
 689 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 690 {
 691         int  ret = -EINVAL;
 692
 693         if (clk->set_rate)
 694                 ret = clk->set_rate(clk, rate);
 695         return ret;
 696 }
 697
 698 /*-------------------------------------------------------------------------
 699  * Omap1 clock reset and init functions
 700  *-------------------------------------------------------------------------*/
 701
 702 #ifdef CONFIG_OMAP_RESET_CLOCKS
 703
 704 static void __init omap1_clk_disable_unused(struct clk *clk)
 705 {
 706         __u32 regval32;
 707
 708         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 709          * has not enabled any DSP clocks */
 710         if (clk->enable_reg == DSP_IDLECT2) {
 711                 printk(KERN_INFO "Skipping reset check for DSP domain "
 712                        "clock \"%s\"\n", clk->name);
 713                 return;
 714         }
 715
 716         /* Is the clock already disabled? */
 717         if (clk->flags & ENABLE_REG_32BIT)
 718                 regval32 = __raw_readl(clk->enable_reg);
 719         else
 720                 regval32 = __raw_readw(clk->enable_reg);
 721
 722         if ((regval32 & (1 << clk->enable_bit)) == 0)
 723                 return;
 724
 725         /* FIXME: This clock seems to be necessary but no-one
 726          * has asked for its activation. */
 727         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 728             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 729             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 730                 ) {
 731                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 732                        clk->name);
 733                 return;
 734         }
 735
 736         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 737         clk->ops->disable(clk);
 738         printk(" done\n");
 739 }
 740
 741 #else
 742 #define omap1_clk_disable_unused        NULL
 743 #endif
 744
 745 static struct clk_functions omap1_clk_functions = {
 746         .clk_enable             = omap1_clk_enable,
 747         .clk_disable            = omap1_clk_disable,
 748         .clk_round_rate         = omap1_clk_round_rate,
 749         .clk_set_rate           = omap1_clk_set_rate,
 750         .clk_disable_unused     = omap1_clk_disable_unused,
 751 };
 752
 753 int __init omap1_clk_init(void)
 754 {
 755         struct omap_clk *c;
 756         const struct omap_clock_config *info;
 757         int crystal_type = 0; /* Default 12 MHz */
 758         u32 reg, cpu_mask;
 759
 760 #ifdef CONFIG_DEBUG_LL
 761         /* Resets some clocks that may be left on from bootloader,
 762          * but leaves serial clocks on.
 763          */
 764         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 765 #endif
 766
 767         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 768         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 769         omap_writew(reg, SOFT_REQ_REG);
 770         if (!cpu_is_omap15xx())
 771                 omap_writew(0, SOFT_REQ_REG2);
 772
 773         clk_init(&omap1_clk_functions);
 774
 775         /* By default all idlect1 clocks are allowed to idle */
 776         arm_idlect1_mask = ~0;
 777
 778         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 779                 clk_init_one(c->lk.clk);
 780
 781         cpu_mask = 0;
 782         if (cpu_is_omap16xx())
 783                 cpu_mask |= CK_16XX;
 784         if (cpu_is_omap1510())
 785                 cpu_mask |= CK_1510;
 786         if (cpu_is_omap730())
 787                 cpu_mask |= CK_730;
 788         if (cpu_is_omap310())
 789                 cpu_mask |= CK_310;
 790
 791         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 792                 if (c->cpu & cpu_mask) {
 793                         clkdev_add(&c->lk);
 794                         clk_register(c->lk.clk);
 795                 }
 796
 797         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 798         if (info != NULL) {
 799                 if (!cpu_is_omap15xx())
 800                         crystal_type = info->system_clock_type;
 801         }
 802
 803 #if defined(CONFIG_ARCH_OMAP730)
 804         ck_ref.rate = 13000000;
 805 #elif defined(CONFIG_ARCH_OMAP16XX)
 806         if (crystal_type == 2)
 807                 ck_ref.rate = 19200000;
 808 #endif
 809
 810         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 811                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 812                omap_readw(ARM_CKCTL));
 813
 814         /* We want to be in syncronous scalable mode */
 815         omap_writew(0x1000, ARM_SYSST);
 816
 817 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 818         /* Use values set by bootloader. Determine PLL rate and recalculate
 819          * dependent clocks as if kernel had changed PLL or divisors.
 820          */
 821         {
 822                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 823
 824                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 825                 if (pll_ctl_val & 0x10) {
 826                         /* PLL enabled, apply multiplier and divisor */
 827                         if (pll_ctl_val & 0xf80)
 828                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 829                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 830                 } else {
 831                         /* PLL disabled, apply bypass divisor */
 832                         switch (pll_ctl_val & 0xc) {
 833                         case 0:
 834                                 break;
 835                         case 0x4:
 836                                 ck_dpll1.rate /= 2;
 837                                 break;
 838                         default:
 839                                 ck_dpll1.rate /= 4;
 840                                 break;
 841                         }
 842                 }
 843         }
 844 #else
 845         /* Find the highest supported frequency and enable it */
 846         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 847                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 848                 /* Guess sane values (60MHz) */
 849                 omap_writew(0x2290, DPLL_CTL);
 850                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 851                 ck_dpll1.rate = 60000000;
 852         }
 853 #endif
 854         propagate_rate(&ck_dpll1);
 855         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 856         propagate_rate(&ck_ref);
 857         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 858                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 859                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 860                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 861                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 862
 863 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 864         /* Select slicer output as OMAP input clock */
 865         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 866 #endif
 867
 868         /* Amstrad Delta wants BCLK high when inactive */
 869         if (machine_is_ams_delta())
 870                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 871                                 (1 << SDW_MCLK_INV_BIT),
 872                                 ULPD_CLOCK_CTRL);
 873
 874         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 875         /* (on 730, bit 13 must not be cleared) */
 876         if (cpu_is_omap730())
 877                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 878         else
 879                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 880
 881         /* Put DSP/MPUI into reset until needed */
 882         omap_writew(0, ARM_RSTCT1);
 883         omap_writew(1, ARM_RSTCT2);
 884         omap_writew(0x400, ARM_IDLECT1);
 885
 886         /*
 887          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 888          * of the ARM_IDLECT2 register must be set to zero. The power-on
 889          * default value of this bit is one.
 890          */
 891         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 892
 893         /*
 894          * Only enable those clocks we will need, let the drivers
 895          * enable other clocks as necessary
 896          */
 897         clk_enable(&armper_ck.clk);
 898         clk_enable(&armxor_ck.clk);
 899         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 900
 901         if (cpu_is_omap15xx())
 902                 clk_enable(&arm_gpio_ck);
 903
 904         return 0;
 905 }