3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <net/iw_handler.h>
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_radio.h"
47 #include "bcm43xx_phy.h"
48 #include "bcm43xx_dma.h"
49 #include "bcm43xx_pio.h"
50 #include "bcm43xx_power.h"
51 #include "bcm43xx_wx.h"
52 #include "bcm43xx_ethtool.h"
53 #include "bcm43xx_xmit.h"
56 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
62 #ifdef CONFIG_BCM947XX
63 extern char *nvram_get(char *name);
66 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
67 static int modparam_pio;
68 module_param_named(pio, modparam_pio, int, 0444);
69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_BCM43XX_DMA)
71 # define modparam_pio 0
72 #elif defined(CONFIG_BCM43XX_PIO)
73 # define modparam_pio 1
76 static int modparam_bad_frames_preempt;
77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
80 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
81 module_param_named(short_retry, modparam_short_retry, int, 0444);
82 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
84 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
85 module_param_named(long_retry, modparam_long_retry, int, 0444);
86 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
88 static int modparam_locale = -1;
89 module_param_named(locale, modparam_locale, int, 0444);
90 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
92 static int modparam_noleds;
93 module_param_named(noleds, modparam_noleds, int, 0444);
94 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
96 #ifdef CONFIG_BCM43XX_DEBUG
97 static char modparam_fwpostfix[64];
98 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
99 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
101 # define modparam_fwpostfix ""
102 #endif /* CONFIG_BCM43XX_DEBUG*/
105 /* If you want to debug with just a single device, enable this,
106 * where the string is the pci device ID (as given by the kernel's
107 * pci_name function) of the device to be used.
109 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
111 /* If you want to enable printing of each MMIO access, enable this. */
112 //#define DEBUG_ENABLE_MMIO_PRINT
114 /* If you want to enable printing of MMIO access within
115 * ucode/pcm upload, initvals write, enable this.
117 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
119 /* If you want to enable printing of PCI Config Space access, enable this */
120 //#define DEBUG_ENABLE_PCILOG
123 /* Detailed list maintained at:
124 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
126 static struct pci_device_id bcm43xx_pci_tbl[] = {
127 /* Broadcom 4303 802.11b */
128 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 /* Broadcom 4307 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4318 802.11b/g */
132 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4306 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4306 802.11a */
136 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4309 802.11a/b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 43XG 802.11b/g */
140 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 #ifdef CONFIG_BCM947XX
142 /* SB bus on BCM947xx */
143 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
149 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
153 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
154 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
157 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
159 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
163 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
164 u16 routing, u16 offset)
168 /* "offset" is the WORD offset. */
173 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
176 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
177 u16 routing, u16 offset)
181 if (routing == BCM43xx_SHM_SHARED) {
182 if (offset & 0x0003) {
183 /* Unaligned access */
184 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
185 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
187 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
188 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
194 bcm43xx_shm_control_word(bcm, routing, offset);
195 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
200 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
201 u16 routing, u16 offset)
205 if (routing == BCM43xx_SHM_SHARED) {
206 if (offset & 0x0003) {
207 /* Unaligned access */
208 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
209 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
215 bcm43xx_shm_control_word(bcm, routing, offset);
216 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
221 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
222 u16 routing, u16 offset,
225 if (routing == BCM43xx_SHM_SHARED) {
226 if (offset & 0x0003) {
227 /* Unaligned access */
228 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
230 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
231 (value >> 16) & 0xffff);
233 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
235 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
241 bcm43xx_shm_control_word(bcm, routing, offset);
243 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
246 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
247 u16 routing, u16 offset,
250 if (routing == BCM43xx_SHM_SHARED) {
251 if (offset & 0x0003) {
252 /* Unaligned access */
253 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
255 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
261 bcm43xx_shm_control_word(bcm, routing, offset);
263 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
266 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
268 /* We need to be careful. As we read the TSF from multiple
269 * registers, we should take care of register overflows.
270 * In theory, the whole tsf read process should be atomic.
271 * We try to be atomic here, by restaring the read process,
272 * if any of the high registers changed (overflew).
274 if (bcm->current_core->rev >= 3) {
275 u32 low, high, high2;
278 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
279 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
280 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
281 } while (unlikely(high != high2));
289 u16 test1, test2, test3;
292 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
293 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
294 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
295 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
297 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
298 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
299 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
300 } while (v3 != test3 || v2 != test2 || v1 != test1);
314 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
318 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
319 status |= BCM43xx_SBF_TIME_UPDATE;
320 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
323 /* Be careful with the in-progress timer.
324 * First zero out the low register, so we have a full
325 * register-overflow duration to complete the operation.
327 if (bcm->current_core->rev >= 3) {
328 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
329 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
331 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
333 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
337 u16 v0 = (tsf & 0x000000000000FFFFULL);
338 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
339 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
340 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
342 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
344 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
353 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
354 status &= ~BCM43xx_SBF_TIME_UPDATE;
355 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
359 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
366 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
373 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
376 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
379 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
382 const u8 zero_addr[ETH_ALEN] = { 0 };
384 bcm43xx_macfilter_set(bcm, offset, zero_addr);
387 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
389 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
390 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
391 u8 mac_bssid[ETH_ALEN * 2];
394 memcpy(mac_bssid, mac, ETH_ALEN);
395 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
397 /* Write our MAC address and BSSID to template ram */
398 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
399 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
400 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
401 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
406 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
408 /* slot_time is in usec. */
409 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
411 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
412 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
415 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
417 bcm43xx_set_slot_time(bcm, 9);
420 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
422 bcm43xx_set_slot_time(bcm, 20);
425 //FIXME: rename this func?
426 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
428 bcm43xx_mac_suspend(bcm);
429 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
431 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
432 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
433 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
434 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
435 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
436 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
438 if (bcm->current_core->rev < 3) {
439 bcm43xx_write16(bcm, 0x0610, 0x8000);
440 bcm43xx_write16(bcm, 0x060E, 0x0000);
442 bcm43xx_write32(bcm, 0x0188, 0x80000000);
444 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
446 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
447 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
448 bcm43xx_short_slot_timing_enable(bcm);
450 bcm43xx_mac_enable(bcm);
453 //FIXME: rename this func?
454 static void bcm43xx_associate(struct bcm43xx_private *bcm,
457 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
459 bcm43xx_mac_suspend(bcm);
460 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
461 bcm43xx_write_mac_bssid_templates(bcm);
462 bcm43xx_mac_enable(bcm);
465 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
466 * Returns the _previously_ enabled IRQ mask.
468 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
472 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
473 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
478 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
479 * Returns the _previously_ enabled IRQ mask.
481 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
485 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
486 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
491 /* Make sure we don't receive more data from the device. */
492 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
497 bcm43xx_lock_mmio(bcm, flags);
498 if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
499 bcm43xx_unlock_mmio(bcm, flags);
502 old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
503 tasklet_disable(&bcm->isr_tasklet);
504 bcm43xx_unlock_mmio(bcm, flags);
511 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
513 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
514 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
521 if (bcm->chip_id == 0x4317) {
522 if (bcm->chip_rev == 0x00)
523 radio_id = 0x3205017F;
524 else if (bcm->chip_rev == 0x01)
525 radio_id = 0x4205017F;
527 radio_id = 0x5205017F;
529 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
530 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
532 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
533 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
536 manufact = (radio_id & 0x00000FFF);
537 version = (radio_id & 0x0FFFF000) >> 12;
538 revision = (radio_id & 0xF0000000) >> 28;
540 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
541 radio_id, manufact, version, revision);
544 case BCM43xx_PHYTYPE_A:
545 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
546 goto err_unsupported_radio;
548 case BCM43xx_PHYTYPE_B:
549 if ((version & 0xFFF0) != 0x2050)
550 goto err_unsupported_radio;
552 case BCM43xx_PHYTYPE_G:
553 if (version != 0x2050)
554 goto err_unsupported_radio;
558 radio->manufact = manufact;
559 radio->version = version;
560 radio->revision = revision;
562 /* Set default attenuation values. */
563 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
564 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
565 radio->txctl1 = bcm43xx_default_txctl1(bcm);
566 if (phy->type == BCM43xx_PHYTYPE_A)
567 radio->txpower_desired = bcm->sprom.maxpower_aphy;
569 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
571 /* Initialize the in-memory nrssi Lookup Table. */
572 for (i = 0; i < 64; i++)
573 radio->nrssi_lt[i] = i;
577 err_unsupported_radio:
578 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
582 static const char * bcm43xx_locale_iso(u8 locale)
584 /* ISO 3166-1 country codes.
585 * Note that there aren't ISO 3166-1 codes for
586 * all or locales. (Not all locales are countries)
589 case BCM43xx_LOCALE_WORLD:
590 case BCM43xx_LOCALE_ALL:
592 case BCM43xx_LOCALE_THAILAND:
594 case BCM43xx_LOCALE_ISRAEL:
596 case BCM43xx_LOCALE_JORDAN:
598 case BCM43xx_LOCALE_CHINA:
600 case BCM43xx_LOCALE_JAPAN:
601 case BCM43xx_LOCALE_JAPAN_HIGH:
603 case BCM43xx_LOCALE_USA_CANADA_ANZ:
604 case BCM43xx_LOCALE_USA_LOW:
606 case BCM43xx_LOCALE_EUROPE:
608 case BCM43xx_LOCALE_NONE:
615 static const char * bcm43xx_locale_string(u8 locale)
618 case BCM43xx_LOCALE_WORLD:
620 case BCM43xx_LOCALE_THAILAND:
622 case BCM43xx_LOCALE_ISRAEL:
624 case BCM43xx_LOCALE_JORDAN:
626 case BCM43xx_LOCALE_CHINA:
628 case BCM43xx_LOCALE_JAPAN:
630 case BCM43xx_LOCALE_USA_CANADA_ANZ:
631 return "USA/Canada/ANZ";
632 case BCM43xx_LOCALE_EUROPE:
634 case BCM43xx_LOCALE_USA_LOW:
636 case BCM43xx_LOCALE_JAPAN_HIGH:
638 case BCM43xx_LOCALE_ALL:
640 case BCM43xx_LOCALE_NONE:
647 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
649 static const u8 t[] = {
650 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
651 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
652 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
653 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
654 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
655 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
656 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
657 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
658 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
659 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
660 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
661 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
662 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
663 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
664 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
665 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
666 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
667 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
668 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
669 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
670 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
671 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
672 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
673 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
674 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
675 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
676 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
677 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
678 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
679 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
680 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
681 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
683 return t[crc ^ data];
686 static u8 bcm43xx_sprom_crc(const u16 *sprom)
691 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
692 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
693 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
695 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
701 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
704 u8 crc, expected_crc;
706 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
707 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
709 crc = bcm43xx_sprom_crc(sprom);
710 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
711 if (crc != expected_crc) {
712 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
713 "(0x%02X, expected: 0x%02X)\n",
721 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
724 u8 crc, expected_crc;
727 /* CRC-8 validation of the input data. */
728 crc = bcm43xx_sprom_crc(sprom);
729 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
730 if (crc != expected_crc) {
731 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
735 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
736 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
739 spromctl |= 0x10; /* SPROM WRITE enable. */
740 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
743 /* We must burn lots of CPU cycles here, but that does not
744 * really matter as one does not write the SPROM every other minute...
746 printk(KERN_INFO PFX "[ 0%%");
748 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
757 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
761 spromctl &= ~0x10; /* SPROM WRITE enable. */
762 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
767 printk(KERN_INFO PFX "SPROM written.\n");
768 bcm43xx_controller_restart(bcm, "SPROM update");
772 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
776 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
780 #ifdef CONFIG_BCM947XX
784 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
787 printk(KERN_ERR PFX "sprom_extract OOM\n");
790 #ifdef CONFIG_BCM947XX
791 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
792 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
794 if ((c = nvram_get("il0macaddr")) != NULL)
795 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
797 if ((c = nvram_get("et1macaddr")) != NULL)
798 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
800 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
801 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
802 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
804 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
805 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
806 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
808 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
810 bcm43xx_sprom_read(bcm, sprom);
814 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
815 bcm->sprom.boardflags2 = value;
818 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
819 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
820 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
821 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
822 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
823 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
826 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
827 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
828 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
829 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
830 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
831 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
834 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
835 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
836 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
837 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
838 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
839 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
841 /* ethernet phy settings */
842 value = sprom[BCM43xx_SPROM_ETHPHY];
843 bcm->sprom.et0phyaddr = (value & 0x001F);
844 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
845 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
846 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
848 /* boardrev, antennas, locale */
849 value = sprom[BCM43xx_SPROM_BOARDREV];
850 bcm->sprom.boardrev = (value & 0x00FF);
851 bcm->sprom.locale = (value & 0x0F00) >> 8;
852 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
853 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
854 if (modparam_locale != -1) {
855 if (modparam_locale >= 0 && modparam_locale <= 11) {
856 bcm->sprom.locale = modparam_locale;
857 printk(KERN_WARNING PFX "Operating with modified "
858 "LocaleCode %u (%s)\n",
860 bcm43xx_locale_string(bcm->sprom.locale));
862 printk(KERN_WARNING PFX "Module parameter \"locale\" "
863 "invalid value. (0 - 11)\n");
868 value = sprom[BCM43xx_SPROM_PA0B0];
869 bcm->sprom.pa0b0 = value;
870 value = sprom[BCM43xx_SPROM_PA0B1];
871 bcm->sprom.pa0b1 = value;
872 value = sprom[BCM43xx_SPROM_PA0B2];
873 bcm->sprom.pa0b2 = value;
876 value = sprom[BCM43xx_SPROM_WL0GPIO0];
879 bcm->sprom.wl0gpio0 = value & 0x00FF;
880 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
881 value = sprom[BCM43xx_SPROM_WL0GPIO2];
884 bcm->sprom.wl0gpio2 = value & 0x00FF;
885 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
888 value = sprom[BCM43xx_SPROM_MAXPWR];
889 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
890 bcm->sprom.maxpower_bgphy = value & 0x00FF;
893 value = sprom[BCM43xx_SPROM_PA1B0];
894 bcm->sprom.pa1b0 = value;
895 value = sprom[BCM43xx_SPROM_PA1B1];
896 bcm->sprom.pa1b1 = value;
897 value = sprom[BCM43xx_SPROM_PA1B2];
898 bcm->sprom.pa1b2 = value;
900 /* idle tssi target */
901 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
902 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
903 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
906 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
909 bcm->sprom.boardflags = value;
910 /* boardflags workarounds */
911 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
912 bcm->chip_id == 0x4301 &&
913 bcm->board_revision == 0x74)
914 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
915 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
916 bcm->board_type == 0x4E &&
917 bcm->board_revision > 0x40)
918 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
921 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
922 if (value == 0x0000 || value == 0xFFFF)
924 /* convert values to Q5.2 */
925 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
926 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
933 static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
935 struct ieee80211_geo geo;
936 struct ieee80211_channel *chan;
937 int have_a = 0, have_bg = 0;
940 struct bcm43xx_phyinfo *phy;
941 const char *iso_country;
943 memset(&geo, 0, sizeof(geo));
944 for (i = 0; i < bcm->nr_80211_available; i++) {
945 phy = &(bcm->core_80211_ext[i].phy);
947 case BCM43xx_PHYTYPE_B:
948 case BCM43xx_PHYTYPE_G:
951 case BCM43xx_PHYTYPE_A:
958 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
961 for (i = 0, channel = 0; channel < 201; channel++) {
963 chan->freq = bcm43xx_channel_to_freq_a(channel);
964 chan->channel = channel;
969 for (i = 0, channel = 1; channel < 15; channel++) {
971 chan->freq = bcm43xx_channel_to_freq_bg(channel);
972 chan->channel = channel;
976 memcpy(geo.name, iso_country, 2);
977 if (0 /*TODO: Outdoor use only */)
979 else if (0 /*TODO: Indoor use only */)
985 ieee80211_set_geo(bcm->ieee, &geo);
988 /* DummyTransmission function, as documented on
989 * http://bcm-specs.sipsolutions.net/DummyTransmission
991 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
993 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
994 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
995 unsigned int i, max_loop;
1005 switch (phy->type) {
1006 case BCM43xx_PHYTYPE_A:
1008 buffer[0] = 0xCC010200;
1010 case BCM43xx_PHYTYPE_B:
1011 case BCM43xx_PHYTYPE_G:
1013 buffer[0] = 0x6E840B00;
1020 for (i = 0; i < 5; i++)
1021 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1023 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1025 bcm43xx_write16(bcm, 0x0568, 0x0000);
1026 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1027 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1028 bcm43xx_write16(bcm, 0x0508, 0x0000);
1029 bcm43xx_write16(bcm, 0x050A, 0x0000);
1030 bcm43xx_write16(bcm, 0x054C, 0x0000);
1031 bcm43xx_write16(bcm, 0x056A, 0x0014);
1032 bcm43xx_write16(bcm, 0x0568, 0x0826);
1033 bcm43xx_write16(bcm, 0x0500, 0x0000);
1034 bcm43xx_write16(bcm, 0x0502, 0x0030);
1036 if (radio->version == 0x2050 && radio->revision <= 0x5)
1037 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1038 for (i = 0x00; i < max_loop; i++) {
1039 value = bcm43xx_read16(bcm, 0x050E);
1044 for (i = 0x00; i < 0x0A; i++) {
1045 value = bcm43xx_read16(bcm, 0x050E);
1050 for (i = 0x00; i < 0x0A; i++) {
1051 value = bcm43xx_read16(bcm, 0x0690);
1052 if (!(value & 0x0100))
1056 if (radio->version == 0x2050 && radio->revision <= 0x5)
1057 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1060 static void key_write(struct bcm43xx_private *bcm,
1061 u8 index, u8 algorithm, const u16 *key)
1063 unsigned int i, basic_wep = 0;
1067 /* Write associated key information */
1068 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1069 ((index << 4) | (algorithm & 0x0F)));
1071 /* The first 4 WEP keys need extra love */
1072 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1073 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1076 /* Write key payload, 8 little endian words */
1077 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1078 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1079 value = cpu_to_le16(key[i]);
1080 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1081 offset + (i * 2), value);
1086 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1087 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1092 static void keymac_write(struct bcm43xx_private *bcm,
1093 u8 index, const u32 *addr)
1095 /* for keys 0-3 there is no associated mac address */
1100 if (bcm->current_core->rev >= 5) {
1101 bcm43xx_shm_write32(bcm,
1104 cpu_to_be32(*addr));
1105 bcm43xx_shm_write16(bcm,
1108 cpu_to_be16(*((u16 *)(addr + 1))));
1111 TODO(); /* Put them in the macaddress filter */
1114 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1115 Keep in mind to update the count of keymacs in 0x003E as well! */
1120 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1121 u8 index, u8 algorithm,
1122 const u8 *_key, int key_len,
1125 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1127 if (index >= ARRAY_SIZE(bcm->key))
1129 if (key_len > ARRAY_SIZE(key))
1131 if (algorithm < 1 || algorithm > 5)
1134 memcpy(key, _key, key_len);
1135 key_write(bcm, index, algorithm, (const u16 *)key);
1136 keymac_write(bcm, index, (const u32 *)mac_addr);
1138 bcm->key[index].algorithm = algorithm;
1143 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1145 static const u32 zero_mac[2] = { 0 };
1146 unsigned int i,j, nr_keys = 54;
1149 if (bcm->current_core->rev < 5)
1151 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1153 for (i = 0; i < nr_keys; i++) {
1154 bcm->key[i].enabled = 0;
1155 /* returns for i < 4 immediately */
1156 keymac_write(bcm, i, zero_mac);
1157 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1158 0x100 + (i * 2), 0x0000);
1159 for (j = 0; j < 8; j++) {
1160 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1161 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1165 dprintk(KERN_INFO PFX "Keys cleared\n");
1168 /* Lowlevel core-switch function. This is only to be used in
1169 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1171 static int _switch_core(struct bcm43xx_private *bcm, int core)
1179 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1180 (core * 0x1000) + 0x18000000);
1183 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1187 current_core = (current_core - 0x18000000) / 0x1000;
1188 if (current_core == core)
1191 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1195 #ifdef CONFIG_BCM947XX
1196 if (bcm->pci_dev->bus->number == 0)
1197 bcm->current_core_offset = 0x1000 * core;
1199 bcm->current_core_offset = 0;
1204 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1208 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1212 if (unlikely(!new_core))
1214 if (!new_core->available)
1216 if (bcm->current_core == new_core)
1218 err = _switch_core(bcm, new_core->index);
1222 bcm->current_core = new_core;
1223 bcm->current_80211_core_idx = -1;
1224 if (new_core->id == BCM43xx_COREID_80211)
1225 bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
1231 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1235 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1236 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1237 | BCM43xx_SBTMSTATELOW_REJECT;
1239 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1242 /* disable current core */
1243 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1249 /* fetch sbtmstatelow from core information registers */
1250 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1252 /* core is already in reset */
1253 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1256 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1257 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1258 BCM43xx_SBTMSTATELOW_REJECT;
1259 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1261 for (i = 0; i < 1000; i++) {
1262 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1263 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1270 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1274 for (i = 0; i < 1000; i++) {
1275 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1276 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1283 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1287 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1288 BCM43xx_SBTMSTATELOW_REJECT |
1289 BCM43xx_SBTMSTATELOW_RESET |
1290 BCM43xx_SBTMSTATELOW_CLOCK |
1292 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1296 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1297 BCM43xx_SBTMSTATELOW_REJECT |
1299 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1302 bcm->current_core->enabled = 0;
1307 /* enable (reset) current core */
1308 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1315 err = bcm43xx_core_disable(bcm, core_flags);
1319 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1320 BCM43xx_SBTMSTATELOW_RESET |
1321 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1323 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1326 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1327 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1328 sbtmstatehigh = 0x00000000;
1329 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1332 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1333 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1334 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1335 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1338 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1339 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1341 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1344 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1345 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1348 bcm->current_core->enabled = 1;
1354 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1355 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1357 u32 flags = 0x00040000;
1359 if ((bcm43xx_core_enabled(bcm)) &&
1360 !bcm43xx_using_pio(bcm)) {
1361 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1362 #ifndef CONFIG_BCM947XX
1363 /* reset all used DMA controllers. */
1364 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1365 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1366 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1367 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1368 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1369 if (bcm->current_core->rev < 5)
1370 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1373 if (bcm->shutting_down) {
1374 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1375 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1376 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1379 flags |= 0x20000000;
1380 bcm43xx_phy_connect(bcm, connect_phy);
1381 bcm43xx_core_enable(bcm, flags);
1382 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1383 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1384 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1389 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1391 bcm43xx_radio_turn_off(bcm);
1392 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1393 bcm43xx_core_disable(bcm, 0);
1396 /* Mark the current 80211 core inactive.
1397 * "active_80211_core" is the other 80211 core, which is used.
1399 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
1400 struct bcm43xx_coreinfo *active_80211_core)
1403 struct bcm43xx_coreinfo *old_core;
1406 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1407 bcm43xx_radio_turn_off(bcm);
1408 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1409 sbtmstatelow &= ~0x200a0000;
1410 sbtmstatelow |= 0xa0000;
1411 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1413 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1414 sbtmstatelow &= ~0xa0000;
1415 sbtmstatelow |= 0x80000;
1416 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1419 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
1420 old_core = bcm->current_core;
1421 err = bcm43xx_switch_core(bcm, active_80211_core);
1424 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1425 sbtmstatelow &= ~0x20000000;
1426 sbtmstatelow |= 0x20000000;
1427 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1428 err = bcm43xx_switch_core(bcm, old_core);
1435 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1439 struct bcm43xx_xmitstatus stat;
1442 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1445 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1447 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1448 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1449 stat.flags = tmp & 0xFF;
1450 stat.cnt1 = (tmp & 0x0F00) >> 8;
1451 stat.cnt2 = (tmp & 0xF000) >> 12;
1452 stat.seq = (u16)(v1 & 0xFFFF);
1453 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1455 bcm43xx_debugfs_log_txstat(bcm, &stat);
1457 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1459 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1460 //TODO: packet was not acked (was lost)
1462 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1464 if (bcm43xx_using_pio(bcm))
1465 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1467 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1471 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1473 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1474 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1475 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1476 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1477 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1478 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1481 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1483 /* Top half of Link Quality calculation. */
1485 if (bcm->noisecalc.calculation_running)
1487 bcm->noisecalc.core_at_start = bcm->current_core;
1488 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1489 bcm->noisecalc.calculation_running = 1;
1490 bcm->noisecalc.nr_samples = 0;
1492 bcm43xx_generate_noise_sample(bcm);
1495 static void handle_irq_noise(struct bcm43xx_private *bcm)
1497 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1503 /* Bottom half of Link Quality calculation. */
1505 assert(bcm->noisecalc.calculation_running);
1506 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1507 bcm->noisecalc.channel_at_start != radio->channel)
1508 goto drop_calculation;
1509 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1510 noise[0] = (tmp & 0x00FF);
1511 noise[1] = (tmp & 0xFF00) >> 8;
1512 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1513 noise[2] = (tmp & 0x00FF);
1514 noise[3] = (tmp & 0xFF00) >> 8;
1515 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1516 noise[2] == 0x7F || noise[3] == 0x7F)
1519 /* Get the noise samples. */
1520 assert(bcm->noisecalc.nr_samples <= 8);
1521 i = bcm->noisecalc.nr_samples;
1522 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1523 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1524 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1525 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1526 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1527 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1528 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1529 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1530 bcm->noisecalc.nr_samples++;
1531 if (bcm->noisecalc.nr_samples == 8) {
1532 /* Calculate the Link Quality by the noise samples. */
1534 for (i = 0; i < 8; i++) {
1535 for (j = 0; j < 4; j++)
1536 average += bcm->noisecalc.samples[i][j];
1543 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1544 tmp = (tmp / 128) & 0x1F;
1554 /* FIXME: This is wrong, but people want fancy stats. well... */
1555 bcm->stats.noise = average;
1557 bcm->stats.link_quality = 0;
1558 else if (average > -75)
1559 bcm->stats.link_quality = 1;
1560 else if (average > -85)
1561 bcm->stats.link_quality = 2;
1563 bcm->stats.link_quality = 3;
1564 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1566 bcm->noisecalc.calculation_running = 0;
1570 bcm43xx_generate_noise_sample(bcm);
1573 static void handle_irq_ps(struct bcm43xx_private *bcm)
1575 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1578 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1579 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1581 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1582 bcm->reg124_set_0x4 = 1;
1583 //FIXME else set to false?
1586 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1588 if (!bcm->reg124_set_0x4)
1590 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1591 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1593 //FIXME: reset reg124_set_0x4 to false?
1596 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1603 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1604 if (!(tmp & 0x00000008))
1607 /* 16bit write is odd, but correct. */
1608 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1611 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1612 u16 ram_offset, u16 shm_size_offset)
1618 //FIXME: assumption: The chip sets the timestamp
1620 bcm43xx_ram_write(bcm, ram_offset++, value);
1621 bcm43xx_ram_write(bcm, ram_offset++, value);
1624 /* Beacon Interval / Capability Information */
1625 value = 0x0000;//FIXME: Which interval?
1626 value |= (1 << 0) << 16; /* ESS */
1627 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1628 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1629 if (!bcm->ieee->open_wep)
1630 value |= (1 << 4) << 16; /* Privacy */
1631 bcm43xx_ram_write(bcm, ram_offset++, value);
1637 /* FH Parameter Set */
1640 /* DS Parameter Set */
1643 /* CF Parameter Set */
1649 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1652 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1656 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1657 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1659 if ((status & 0x1) && (status & 0x2)) {
1660 /* ACK beacon IRQ. */
1661 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1662 BCM43xx_IRQ_BEACON);
1663 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1666 if (!(status & 0x1)) {
1667 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1669 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1671 if (!(status & 0x2)) {
1672 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1674 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1678 /* Interrupt handler bottom-half */
1679 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1684 unsigned long flags;
1686 #ifdef CONFIG_BCM43XX_DEBUG
1687 u32 _handled = 0x00000000;
1688 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1690 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1691 #endif /* CONFIG_BCM43XX_DEBUG*/
1693 bcm43xx_lock_mmio(bcm, flags);
1694 reason = bcm->irq_reason;
1695 dma_reason[0] = bcm->dma_reason[0];
1696 dma_reason[1] = bcm->dma_reason[1];
1697 dma_reason[2] = bcm->dma_reason[2];
1698 dma_reason[3] = bcm->dma_reason[3];
1700 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1701 /* TX error. We get this when Template Ram is written in wrong endianess
1702 * in dummy_tx(). We also get this if something is wrong with the TX header
1703 * on DMA or PIO queues.
1704 * Maybe we get this in other error conditions, too.
1706 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1707 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1709 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
1710 (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
1711 (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
1712 (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
1713 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1714 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1715 dma_reason[0], dma_reason[1],
1716 dma_reason[2], dma_reason[3]);
1717 bcm43xx_controller_restart(bcm, "DMA error");
1718 bcm43xx_unlock_mmio(bcm, flags);
1721 if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
1722 (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
1723 (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
1724 (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
1725 printkl(KERN_ERR PFX "DMA error: "
1726 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1727 dma_reason[0], dma_reason[1],
1728 dma_reason[2], dma_reason[3]);
1731 if (reason & BCM43xx_IRQ_PS) {
1733 bcmirq_handled(BCM43xx_IRQ_PS);
1736 if (reason & BCM43xx_IRQ_REG124) {
1737 handle_irq_reg124(bcm);
1738 bcmirq_handled(BCM43xx_IRQ_REG124);
1741 if (reason & BCM43xx_IRQ_BEACON) {
1742 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1743 handle_irq_beacon(bcm);
1744 bcmirq_handled(BCM43xx_IRQ_BEACON);
1747 if (reason & BCM43xx_IRQ_PMQ) {
1748 handle_irq_pmq(bcm);
1749 bcmirq_handled(BCM43xx_IRQ_PMQ);
1752 if (reason & BCM43xx_IRQ_SCAN) {
1754 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1757 if (reason & BCM43xx_IRQ_NOISE) {
1758 handle_irq_noise(bcm);
1759 bcmirq_handled(BCM43xx_IRQ_NOISE);
1762 /* Check the DMA reason registers for received data. */
1763 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1764 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1765 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1766 if (bcm43xx_using_pio(bcm))
1767 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1769 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1770 /* We intentionally don't set "activity" to 1, here. */
1772 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1773 if (bcm43xx_using_pio(bcm))
1774 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1776 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
1779 bcmirq_handled(BCM43xx_IRQ_RX);
1781 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1782 handle_irq_transmit_status(bcm);
1784 //TODO: In AP mode, this also causes sending of powersave responses.
1785 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1788 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1789 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1790 #ifdef CONFIG_BCM43XX_DEBUG
1791 if (unlikely(reason & ~_handled)) {
1792 printkl(KERN_WARNING PFX
1793 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1794 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1795 reason, (reason & ~_handled),
1796 dma_reason[0], dma_reason[1],
1797 dma_reason[2], dma_reason[3]);
1800 #undef bcmirq_handled
1802 if (!modparam_noleds)
1803 bcm43xx_leds_update(bcm, activity);
1804 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1805 bcm43xx_unlock_mmio(bcm, flags);
1808 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1809 u16 base, int queueidx)
1813 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1814 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1815 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1817 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1820 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1822 if (bcm43xx_using_pio(bcm) &&
1823 (bcm->current_core->rev < 3) &&
1824 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1825 /* Apply a PIO specific workaround to the dma_reasons */
1826 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1827 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1828 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1829 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1832 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1834 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1835 bcm->dma_reason[0]);
1836 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1837 bcm->dma_reason[1]);
1838 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1839 bcm->dma_reason[2]);
1840 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1841 bcm->dma_reason[3]);
1844 /* Interrupt handler top-half */
1845 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1847 irqreturn_t ret = IRQ_HANDLED;
1848 struct bcm43xx_private *bcm = dev_id;
1854 spin_lock(&bcm->_lock);
1856 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1857 if (reason == 0xffffffff) {
1858 /* irq not for us (shared irq) */
1862 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1866 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1868 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1870 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1872 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1875 bcm43xx_interrupt_ack(bcm, reason);
1877 /* Only accept IRQs, if we are initialized properly.
1878 * This avoids an RX race while initializing.
1879 * We should probably not enable IRQs before we are initialized
1880 * completely, but some careful work is needed to fix this. I think it
1881 * is best to stay with this cheap workaround for now... .
1883 if (likely(bcm->initialized)) {
1884 /* disable all IRQs. They are enabled again in the bottom half. */
1885 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1886 /* save the reason code and call our bottom half. */
1887 bcm->irq_reason = reason;
1888 tasklet_schedule(&bcm->isr_tasklet);
1893 spin_unlock(&bcm->_lock);
1898 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1900 if (bcm->firmware_norelease && !force)
1901 return; /* Suspending or controller reset. */
1902 release_firmware(bcm->ucode);
1904 release_firmware(bcm->pcm);
1906 release_firmware(bcm->initvals0);
1907 bcm->initvals0 = NULL;
1908 release_firmware(bcm->initvals1);
1909 bcm->initvals1 = NULL;
1912 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1914 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1915 u8 rev = bcm->current_core->rev;
1918 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1921 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1922 (rev >= 5 ? 5 : rev),
1923 modparam_fwpostfix);
1924 err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
1927 "Error: Microcode \"%s\" not available or load failed.\n",
1934 snprintf(buf, ARRAY_SIZE(buf),
1935 "bcm43xx_pcm%d%s.fw",
1937 modparam_fwpostfix);
1938 err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
1941 "Error: PCM \"%s\" not available or load failed.\n",
1947 if (!bcm->initvals0) {
1948 if (rev == 2 || rev == 4) {
1949 switch (phy->type) {
1950 case BCM43xx_PHYTYPE_A:
1953 case BCM43xx_PHYTYPE_B:
1954 case BCM43xx_PHYTYPE_G:
1961 } else if (rev >= 5) {
1962 switch (phy->type) {
1963 case BCM43xx_PHYTYPE_A:
1966 case BCM43xx_PHYTYPE_B:
1967 case BCM43xx_PHYTYPE_G:
1975 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1976 nr, modparam_fwpostfix);
1978 err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
1981 "Error: InitVals \"%s\" not available or load failed.\n",
1985 if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
1986 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1991 if (!bcm->initvals1) {
1995 switch (phy->type) {
1996 case BCM43xx_PHYTYPE_A:
1997 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1998 if (sbtmstatehigh & 0x00010000)
2003 case BCM43xx_PHYTYPE_B:
2004 case BCM43xx_PHYTYPE_G:
2010 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2011 nr, modparam_fwpostfix);
2013 err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
2016 "Error: InitVals \"%s\" not available or load failed.\n",
2020 if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
2021 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2030 bcm43xx_release_firmware(bcm, 1);
2033 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2038 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2041 unsigned int i, len;
2043 /* Upload Microcode. */
2044 data = (u32 *)(bcm->ucode->data);
2045 len = bcm->ucode->size / sizeof(u32);
2046 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2047 for (i = 0; i < len; i++) {
2048 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2049 be32_to_cpu(data[i]));
2053 /* Upload PCM data. */
2054 data = (u32 *)(bcm->pcm->data);
2055 len = bcm->pcm->size / sizeof(u32);
2056 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2057 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2058 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2059 for (i = 0; i < len; i++) {
2060 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2061 be32_to_cpu(data[i]));
2066 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2067 const struct bcm43xx_initval *data,
2068 const unsigned int len)
2074 for (i = 0; i < len; i++) {
2075 offset = be16_to_cpu(data[i].offset);
2076 size = be16_to_cpu(data[i].size);
2077 value = be32_to_cpu(data[i].value);
2079 if (unlikely(offset >= 0x1000))
2082 if (unlikely(value & 0xFFFF0000))
2084 bcm43xx_write16(bcm, offset, (u16)value);
2085 } else if (size == 4) {
2086 bcm43xx_write32(bcm, offset, value);
2094 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2095 "Please fix your bcm43xx firmware files.\n");
2099 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2103 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
2104 bcm->initvals0->size / sizeof(struct bcm43xx_initval));
2107 if (bcm->initvals1) {
2108 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
2109 bcm->initvals1->size / sizeof(struct bcm43xx_initval));
2117 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2123 bcm->irq = bcm->pci_dev->irq;
2124 #ifdef CONFIG_BCM947XX
2125 if (bcm->pci_dev->bus->number == 0) {
2126 struct pci_dev *d = NULL;
2127 /* FIXME: we will probably need more device IDs here... */
2128 d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
2134 res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2135 SA_SHIRQ, KBUILD_MODNAME, bcm);
2137 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2140 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
2141 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2144 data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2145 if (data == BCM43xx_IRQ_READY)
2148 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2149 printk(KERN_ERR PFX "Card IRQ register not responding. "
2151 free_irq(bcm->irq, bcm);
2157 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2162 /* Switch to the core used to write the GPIO register.
2163 * This is either the ChipCommon, or the PCI core.
2165 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2169 /* Where to find the GPIO register depends on the chipset.
2170 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2171 * control register. Otherwise the register at offset 0x6c in the
2172 * PCI core is the GPIO control register.
2174 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2175 if (err == -ENODEV) {
2176 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2177 if (unlikely(err == -ENODEV)) {
2178 printk(KERN_ERR PFX "gpio error: "
2179 "Neither ChipCommon nor PCI core available!\n");
2186 /* Initialize the GPIOs
2187 * http://bcm-specs.sipsolutions.net/GPIO
2189 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2191 struct bcm43xx_coreinfo *old_core;
2195 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2196 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2199 bcm43xx_leds_switch_all(bcm, 0);
2200 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2201 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2205 if (bcm->chip_id == 0x4301) {
2209 if (0 /* FIXME: conditional unknown */) {
2210 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2211 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2216 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2217 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2218 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2223 if (bcm->current_core->rev >= 2)
2224 mask |= 0x0010; /* FIXME: This is redundant. */
2226 old_core = bcm->current_core;
2227 err = switch_to_gpio_core(bcm);
2230 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2231 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2232 err = bcm43xx_switch_core(bcm, old_core);
2237 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2238 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2240 struct bcm43xx_coreinfo *old_core;
2243 old_core = bcm->current_core;
2244 err = switch_to_gpio_core(bcm);
2247 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2248 err = bcm43xx_switch_core(bcm, old_core);
2254 /* http://bcm-specs.sipsolutions.net/EnableMac */
2255 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2257 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2258 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2259 | BCM43xx_SBF_MAC_ENABLED);
2260 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2261 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2262 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2263 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2266 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2267 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2272 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2273 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2274 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2275 & ~BCM43xx_SBF_MAC_ENABLED);
2276 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2277 for (i = 100000; i; i--) {
2278 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2279 if (tmp & BCM43xx_IRQ_READY)
2283 printkl(KERN_ERR PFX "MAC suspend failed\n");
2286 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2289 unsigned long flags;
2290 struct net_device *net_dev = bcm->net_dev;
2294 spin_lock_irqsave(&bcm->ieee->lock, flags);
2295 bcm->ieee->iw_mode = iw_mode;
2296 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2297 if (iw_mode == IW_MODE_MONITOR)
2298 net_dev->type = ARPHRD_IEEE80211;
2300 net_dev->type = ARPHRD_ETHER;
2302 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2303 /* Reset status to infrastructured mode */
2304 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2305 status &= ~BCM43xx_SBF_MODE_PROMISC;
2306 status |= BCM43xx_SBF_MODE_NOTADHOC;
2308 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2309 status |= BCM43xx_SBF_MODE_PROMISC;
2312 case IW_MODE_MONITOR:
2313 status |= BCM43xx_SBF_MODE_MONITOR;
2314 status |= BCM43xx_SBF_MODE_PROMISC;
2317 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2319 case IW_MODE_MASTER:
2320 status |= BCM43xx_SBF_MODE_AP;
2322 case IW_MODE_SECOND:
2323 case IW_MODE_REPEAT:
2327 /* nothing to be done here... */
2330 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2332 if (net_dev->flags & IFF_PROMISC)
2333 status |= BCM43xx_SBF_MODE_PROMISC;
2334 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2337 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2338 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2343 bcm43xx_write16(bcm, 0x0612, value);
2346 /* This is the opposite of bcm43xx_chip_init() */
2347 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2349 bcm43xx_radio_turn_off(bcm);
2350 if (!modparam_noleds)
2351 bcm43xx_leds_exit(bcm);
2352 bcm43xx_gpio_cleanup(bcm);
2353 free_irq(bcm->irq, bcm);
2354 bcm43xx_release_firmware(bcm, 0);
2357 /* Initialize the chip
2358 * http://bcm-specs.sipsolutions.net/ChipInit
2360 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2362 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2363 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2369 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2370 BCM43xx_SBF_CORE_READY
2373 err = bcm43xx_request_firmware(bcm);
2376 bcm43xx_upload_microcode(bcm);
2378 err = bcm43xx_initialize_irq(bcm);
2380 goto err_release_fw;
2382 err = bcm43xx_gpio_init(bcm);
2386 err = bcm43xx_upload_initvals(bcm);
2388 goto err_gpio_cleanup;
2389 bcm43xx_radio_turn_on(bcm);
2391 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2392 err = bcm43xx_phy_init(bcm);
2396 /* Select initial Interference Mitigation. */
2397 tmp = radio->interfmode;
2398 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2399 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2401 bcm43xx_phy_set_antenna_diversity(bcm);
2402 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2403 if (phy->type == BCM43xx_PHYTYPE_B) {
2404 value16 = bcm43xx_read16(bcm, 0x005E);
2406 bcm43xx_write16(bcm, 0x005E, value16);
2408 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2409 if (bcm->current_core->rev < 5)
2410 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2412 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2413 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2414 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2415 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2416 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2417 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2419 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2420 value32 |= 0x100000;
2421 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2423 if (bcm43xx_using_pio(bcm)) {
2424 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2425 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2426 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2427 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2428 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2431 /* Probe Response Timeout value */
2432 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2433 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2435 /* Initially set the wireless operation mode. */
2436 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2438 if (bcm->current_core->rev < 3) {
2439 bcm43xx_write16(bcm, 0x060E, 0x0000);
2440 bcm43xx_write16(bcm, 0x0610, 0x8000);
2441 bcm43xx_write16(bcm, 0x0604, 0x0000);
2442 bcm43xx_write16(bcm, 0x0606, 0x0200);
2444 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2445 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2447 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2448 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
2449 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2450 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
2451 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
2453 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2454 value32 |= 0x00100000;
2455 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2457 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2460 dprintk(KERN_INFO PFX "Chip initialized\n");
2465 bcm43xx_radio_turn_off(bcm);
2467 bcm43xx_gpio_cleanup(bcm);
2469 free_irq(bcm->irq, bcm);
2471 bcm43xx_release_firmware(bcm, 1);
2475 /* Validate chip access
2476 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2477 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2482 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2483 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2484 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2486 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2487 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2489 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2491 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2492 if ((value | 0x80000000) != 0x80000400)
2495 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2496 if (value != 0x00000000)
2501 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2505 void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2507 /* Initialize a "phyinfo" structure. The structure is already
2510 phy->antenna_diversity = 0xFFFF;
2511 phy->savedpctlreg = 0xFFFF;
2512 phy->minlowsig[0] = 0xFFFF;
2513 phy->minlowsig[1] = 0xFFFF;
2514 spin_lock_init(&phy->lock);
2517 void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2519 /* Initialize a "radioinfo" structure. The structure is already
2522 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2523 radio->channel = 0xFF;
2524 radio->initial_channel = 0xFF;
2525 radio->lofcal = 0xFFFF;
2526 radio->initval = 0xFFFF;
2527 radio->nrssi[0] = -1000;
2528 radio->nrssi[1] = -1000;
2531 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2535 u32 core_vendor, core_id, core_rev;
2536 u32 sb_id_hi, chip_id_32 = 0;
2537 u16 pci_device, chip_id_16;
2540 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2541 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2542 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2543 * BCM43xx_MAX_80211_CORES);
2544 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2545 * BCM43xx_MAX_80211_CORES);
2546 bcm->current_80211_core_idx = -1;
2547 bcm->nr_80211_available = 0;
2548 bcm->current_core = NULL;
2549 bcm->active_80211_core = NULL;
2552 err = _switch_core(bcm, 0);
2556 /* fetch sb_id_hi from core information registers */
2557 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2559 core_id = (sb_id_hi & 0xFFF0) >> 4;
2560 core_rev = (sb_id_hi & 0xF);
2561 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2563 /* if present, chipcommon is always core 0; read the chipid from it */
2564 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2565 chip_id_32 = bcm43xx_read32(bcm, 0);
2566 chip_id_16 = chip_id_32 & 0xFFFF;
2567 bcm->core_chipcommon.available = 1;
2568 bcm->core_chipcommon.id = core_id;
2569 bcm->core_chipcommon.rev = core_rev;
2570 bcm->core_chipcommon.index = 0;
2571 /* While we are at it, also read the capabilities. */
2572 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2574 /* without a chipCommon, use a hard coded table. */
2575 pci_device = bcm->pci_dev->device;
2576 if (pci_device == 0x4301)
2577 chip_id_16 = 0x4301;
2578 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2579 chip_id_16 = 0x4307;
2580 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2581 chip_id_16 = 0x4402;
2582 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2583 chip_id_16 = 0x4610;
2584 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2585 chip_id_16 = 0x4710;
2586 #ifdef CONFIG_BCM947XX
2587 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2588 chip_id_16 = 0x4309;
2591 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2596 /* ChipCommon with Core Rev >=4 encodes number of cores,
2597 * otherwise consult hardcoded table */
2598 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2599 core_count = (chip_id_32 & 0x0F000000) >> 24;
2601 switch (chip_id_16) {
2624 /* SOL if we get here */
2630 bcm->chip_id = chip_id_16;
2631 bcm->chip_rev = (chip_id_32 & 0x000f0000) >> 16;
2633 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2634 bcm->chip_id, bcm->chip_rev);
2635 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2636 if (bcm->core_chipcommon.available) {
2637 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2638 core_id, core_rev, core_vendor,
2639 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2642 if (bcm->core_chipcommon.available)
2646 for ( ; current_core < core_count; current_core++) {
2647 struct bcm43xx_coreinfo *core;
2648 struct bcm43xx_coreinfo_80211 *ext_80211;
2650 err = _switch_core(bcm, current_core);
2653 /* Gather information */
2654 /* fetch sb_id_hi from core information registers */
2655 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2657 /* extract core_id, core_rev, core_vendor */
2658 core_id = (sb_id_hi & 0xFFF0) >> 4;
2659 core_rev = (sb_id_hi & 0xF);
2660 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2662 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2663 current_core, core_id, core_rev, core_vendor,
2664 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2668 case BCM43xx_COREID_PCI:
2669 core = &bcm->core_pci;
2670 if (core->available) {
2671 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2675 case BCM43xx_COREID_80211:
2676 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2677 core = &(bcm->core_80211[i]);
2678 ext_80211 = &(bcm->core_80211_ext[i]);
2679 if (!core->available)
2684 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2685 BCM43xx_MAX_80211_CORES);
2689 /* More than one 80211 core is only supported
2691 * There are chips with two 80211 cores, but with
2692 * dangling pins on the second core. Be careful
2693 * and ignore these cores here.
2695 if (bcm->pci_dev->device != 0x4324) {
2696 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2709 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2714 bcm->nr_80211_available++;
2715 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2716 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2718 case BCM43xx_COREID_CHIPCOMMON:
2719 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2723 core->available = 1;
2725 core->rev = core_rev;
2726 core->index = current_core;
2730 if (!bcm->core_80211[0].available) {
2731 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2736 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2743 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2745 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2746 u8 *bssid = bcm->ieee->bssid;
2748 switch (bcm->ieee->iw_mode) {
2750 random_ether_addr(bssid);
2752 case IW_MODE_MASTER:
2754 case IW_MODE_REPEAT:
2755 case IW_MODE_SECOND:
2756 case IW_MODE_MONITOR:
2757 memcpy(bssid, mac, ETH_ALEN);
2764 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2772 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2776 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2778 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2779 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2782 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2784 switch (bcm43xx_current_phy(bcm)->type) {
2785 case BCM43xx_PHYTYPE_A:
2786 case BCM43xx_PHYTYPE_G:
2787 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2788 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2789 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2790 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2791 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2792 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2793 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2794 case BCM43xx_PHYTYPE_B:
2795 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2796 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2797 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2798 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2805 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2807 bcm43xx_chip_cleanup(bcm);
2808 bcm43xx_pio_free(bcm);
2809 bcm43xx_dma_free(bcm);
2811 bcm->current_core->initialized = 0;
2814 /* http://bcm-specs.sipsolutions.net/80211Init */
2815 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
2817 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2818 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2824 if (bcm->chip_rev < 5) {
2825 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2826 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2827 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2828 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2829 sbimconfiglow |= 0x32;
2830 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2831 sbimconfiglow |= 0x53;
2834 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2837 bcm43xx_phy_calibrate(bcm);
2838 err = bcm43xx_chip_init(bcm);
2842 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2843 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2845 if (0 /*FIXME: which condition has to be used here? */)
2846 ucodeflags |= 0x00000010;
2848 /* HW decryption needs to be set now */
2849 ucodeflags |= 0x40000000;
2851 if (phy->type == BCM43xx_PHYTYPE_G) {
2852 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2854 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2855 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2856 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2857 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2858 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2859 if (phy->rev >= 2 && radio->version == 0x2050)
2860 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2863 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2864 BCM43xx_UCODEFLAGS_OFFSET)) {
2865 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2866 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2869 /* Short/Long Retry Limit.
2870 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2871 * the chip-internal counter.
2873 limit = limit_value(modparam_short_retry, 0, 0xF);
2874 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2875 limit = limit_value(modparam_long_retry, 0, 0xF);
2876 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2878 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2879 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2881 bcm43xx_rate_memory_init(bcm);
2883 /* Minimum Contention Window */
2884 if (phy->type == BCM43xx_PHYTYPE_B)
2885 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2887 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2888 /* Maximum Contention Window */
2889 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2891 bcm43xx_gen_bssid(bcm);
2892 bcm43xx_write_mac_bssid_templates(bcm);
2894 if (bcm->current_core->rev >= 5)
2895 bcm43xx_write16(bcm, 0x043C, 0x000C);
2897 if (bcm43xx_using_pio(bcm))
2898 err = bcm43xx_pio_init(bcm);
2900 err = bcm43xx_dma_init(bcm);
2902 goto err_chip_cleanup;
2903 bcm43xx_write16(bcm, 0x0612, 0x0050);
2904 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2905 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2907 bcm43xx_mac_enable(bcm);
2908 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
2910 bcm->current_core->initialized = 1;
2915 bcm43xx_chip_cleanup(bcm);
2919 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2924 err = bcm43xx_pctl_set_crystal(bcm, 1);
2927 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2928 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2934 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2936 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2937 bcm43xx_pctl_set_crystal(bcm, 0);
2940 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2944 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2945 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2948 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2951 struct bcm43xx_coreinfo *old_core;
2953 old_core = bcm->current_core;
2954 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2958 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2960 bcm43xx_switch_core(bcm, old_core);
2966 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2967 * To enable core 0, pass a core_mask of 1<<0
2969 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2972 u32 backplane_flag_nr;
2974 struct bcm43xx_coreinfo *old_core;
2977 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2978 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2980 old_core = bcm->current_core;
2981 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2985 if (bcm->core_pci.rev < 6) {
2986 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
2987 value |= (1 << backplane_flag_nr);
2988 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
2990 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
2992 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
2993 goto out_switch_back;
2995 value |= core_mask << 8;
2996 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
2998 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
2999 goto out_switch_back;
3003 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3004 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3005 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3007 if (bcm->core_pci.rev < 5) {
3008 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3009 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3010 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3011 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3012 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3013 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3014 err = bcm43xx_pcicore_commit_settings(bcm);
3019 err = bcm43xx_switch_core(bcm, old_core);
3024 static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
3026 ieee80211softmac_start(bcm->net_dev);
3029 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3031 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3033 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3036 bcm43xx_mac_suspend(bcm);
3037 bcm43xx_phy_lo_g_measure(bcm);
3038 bcm43xx_mac_enable(bcm);
3041 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3043 bcm43xx_phy_lo_mark_all_unused(bcm);
3044 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3045 bcm43xx_mac_suspend(bcm);
3046 bcm43xx_calc_nrssi_slope(bcm);
3047 bcm43xx_mac_enable(bcm);
3051 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3053 /* Update device statistics. */
3054 bcm43xx_calculate_link_quality(bcm);
3057 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3059 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3060 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3062 if (phy->type == BCM43xx_PHYTYPE_G) {
3063 //TODO: update_aci_moving_average
3064 if (radio->aci_enable && radio->aci_wlan_automatic) {
3065 bcm43xx_mac_suspend(bcm);
3066 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3067 if (0 /*TODO: bunch of conditions*/) {
3068 bcm43xx_radio_set_interference_mitigation(bcm,
3069 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3071 } else if (1/*TODO*/) {
3073 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3074 bcm43xx_radio_set_interference_mitigation(bcm,
3075 BCM43xx_RADIO_INTERFMODE_NONE);
3079 bcm43xx_mac_enable(bcm);
3080 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3082 //TODO: implement rev1 workaround
3085 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3086 //TODO for APHY (temperature?)
3089 static void bcm43xx_periodic_task_handler(unsigned long d)
3091 struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
3092 unsigned long flags;
3095 bcm43xx_lock_mmio(bcm, flags);
3097 assert(bcm->initialized);
3098 state = bcm->periodic_state;
3100 bcm43xx_periodic_every120sec(bcm);
3102 bcm43xx_periodic_every60sec(bcm);
3104 bcm43xx_periodic_every30sec(bcm);
3105 bcm43xx_periodic_every15sec(bcm);
3106 bcm->periodic_state = state + 1;
3108 mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
3110 bcm43xx_unlock_mmio(bcm, flags);
3113 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3115 del_timer_sync(&bcm->periodic_tasks);
3118 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3120 struct timer_list *timer = &(bcm->periodic_tasks);
3122 assert(bcm->initialized);
3124 bcm43xx_periodic_task_handler,
3125 (unsigned long)bcm);
3126 timer->expires = jiffies;
3130 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3132 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3134 bcm43xx_clear_keys(bcm);
3137 /* This is the opposite of bcm43xx_init_board() */
3138 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3141 unsigned long flags;
3143 bcm43xx_sysfs_unregister(bcm);
3145 bcm43xx_periodic_tasks_delete(bcm);
3147 bcm43xx_lock(bcm, flags);
3148 bcm->initialized = 0;
3149 bcm->shutting_down = 1;
3150 bcm43xx_unlock(bcm, flags);
3152 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3153 if (!bcm->core_80211[i].available)
3155 if (!bcm->core_80211[i].initialized)
3158 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3160 bcm43xx_wireless_core_cleanup(bcm);
3163 bcm43xx_pctl_set_crystal(bcm, 0);
3165 bcm43xx_lock(bcm, flags);
3166 bcm->shutting_down = 0;
3167 bcm43xx_unlock(bcm, flags);
3170 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3174 unsigned long flags;
3178 bcm43xx_lock(bcm, flags);
3179 bcm->initialized = 0;
3180 bcm->shutting_down = 0;
3181 bcm43xx_unlock(bcm, flags);
3183 err = bcm43xx_pctl_set_crystal(bcm, 1);
3186 err = bcm43xx_pctl_init(bcm);
3188 goto err_crystal_off;
3189 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3191 goto err_crystal_off;
3193 tasklet_enable(&bcm->isr_tasklet);
3194 for (i = 0; i < bcm->nr_80211_available; i++) {
3195 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3196 assert(err != -ENODEV);
3198 goto err_80211_unwind;
3200 /* Enable the selected wireless core.
3201 * Connect PHY only on the first core.
3203 if (!bcm43xx_core_enabled(bcm)) {
3204 if (bcm->nr_80211_available == 1) {
3205 connect_phy = bcm43xx_current_phy(bcm)->connected;
3212 bcm43xx_wireless_core_reset(bcm, connect_phy);
3216 bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
3218 err = bcm43xx_wireless_core_init(bcm);
3220 goto err_80211_unwind;
3223 bcm43xx_mac_suspend(bcm);
3224 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3225 bcm43xx_radio_turn_off(bcm);
3228 bcm->active_80211_core = &bcm->core_80211[0];
3229 if (bcm->nr_80211_available >= 2) {
3230 bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
3231 bcm43xx_mac_enable(bcm);
3233 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3234 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3235 dprintk(KERN_INFO PFX "80211 cores initialized\n");
3236 bcm43xx_security_init(bcm);
3237 bcm43xx_softmac_init(bcm);
3239 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3241 if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
3242 bcm43xx_mac_suspend(bcm);
3243 bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
3244 bcm43xx_mac_enable(bcm);
3247 /* Initialization of the board is done. Flag it as such. */
3248 bcm43xx_lock(bcm, flags);
3249 bcm->initialized = 1;
3250 bcm43xx_unlock(bcm, flags);
3252 bcm43xx_periodic_tasks_setup(bcm);
3253 bcm43xx_sysfs_register(bcm);
3254 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3261 tasklet_disable(&bcm->isr_tasklet);
3262 /* unwind all 80211 initialization */
3263 for (i = 0; i < bcm->nr_80211_available; i++) {
3264 if (!bcm->core_80211[i].initialized)
3266 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3267 bcm43xx_wireless_core_cleanup(bcm);
3270 bcm43xx_pctl_set_crystal(bcm, 0);
3274 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3276 struct pci_dev *pci_dev = bcm->pci_dev;
3279 bcm43xx_chipset_detach(bcm);
3280 /* Do _not_ access the chip, after it is detached. */
3281 iounmap(bcm->mmio_addr);
3283 pci_release_regions(pci_dev);
3284 pci_disable_device(pci_dev);
3286 /* Free allocated structures/fields */
3287 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3288 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3289 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3290 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3294 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3296 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3304 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3306 phy_version = (value & 0xF000) >> 12;
3307 phy_type = (value & 0x0F00) >> 8;
3308 phy_rev = (value & 0x000F);
3310 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3311 phy_version, phy_type, phy_rev);
3314 case BCM43xx_PHYTYPE_A:
3317 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3318 * if we switch 80211 cores after init is done.
3319 * As we do not implement on the fly switching between
3320 * wireless cores, I will leave this as a future task.
3322 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3323 bcm->ieee->mode = IEEE_A;
3324 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3325 IEEE80211_24GHZ_BAND;
3327 case BCM43xx_PHYTYPE_B:
3328 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3330 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3331 bcm->ieee->mode = IEEE_B;
3332 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3334 case BCM43xx_PHYTYPE_G:
3337 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3338 IEEE80211_CCK_MODULATION;
3339 bcm->ieee->mode = IEEE_G;
3340 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3343 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3348 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3352 phy->version = phy_version;
3353 phy->type = phy_type;
3355 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3356 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3366 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3368 struct pci_dev *pci_dev = bcm->pci_dev;
3369 struct net_device *net_dev = bcm->net_dev;
3372 unsigned long mmio_start, mmio_flags, mmio_len;
3375 err = pci_enable_device(pci_dev);
3377 printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
3380 mmio_start = pci_resource_start(pci_dev, 0);
3381 mmio_flags = pci_resource_flags(pci_dev, 0);
3382 mmio_len = pci_resource_len(pci_dev, 0);
3383 if (!(mmio_flags & IORESOURCE_MEM)) {
3385 "%s, region #0 not an MMIO resource, aborting\n",
3388 goto err_pci_disable;
3390 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3393 "could not access PCI resources (%i)\n", err);
3394 goto err_pci_disable;
3396 /* enable PCI bus-mastering */
3397 pci_set_master(pci_dev);
3398 bcm->mmio_addr = ioremap(mmio_start, mmio_len);
3399 if (!bcm->mmio_addr) {
3400 printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
3403 goto err_pci_release;
3405 bcm->mmio_len = mmio_len;
3406 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3408 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3409 &bcm->board_vendor);
3410 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3412 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3413 &bcm->board_revision);
3415 err = bcm43xx_chipset_attach(bcm);
3418 err = bcm43xx_pctl_init(bcm);
3420 goto err_chipset_detach;
3421 err = bcm43xx_probe_cores(bcm);
3423 goto err_chipset_detach;
3425 /* Attach all IO cores to the backplane. */
3427 for (i = 0; i < bcm->nr_80211_available; i++)
3428 coremask |= (1 << bcm->core_80211[i].index);
3429 //FIXME: Also attach some non80211 cores?
3430 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3432 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3433 goto err_chipset_detach;
3436 err = bcm43xx_sprom_extract(bcm);
3438 goto err_chipset_detach;
3439 err = bcm43xx_leds_init(bcm);
3441 goto err_chipset_detach;
3443 for (i = 0; i < bcm->nr_80211_available; i++) {
3444 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3445 assert(err != -ENODEV);
3447 goto err_80211_unwind;
3449 /* Enable the selected wireless core.
3450 * Connect PHY only on the first core.
3452 bcm43xx_wireless_core_reset(bcm, (i == 0));
3454 err = bcm43xx_read_phyinfo(bcm);
3455 if (err && (i == 0))
3456 goto err_80211_unwind;
3458 err = bcm43xx_read_radioinfo(bcm);
3459 if (err && (i == 0))
3460 goto err_80211_unwind;
3462 err = bcm43xx_validate_chip(bcm);
3463 if (err && (i == 0))
3464 goto err_80211_unwind;
3466 bcm43xx_radio_turn_off(bcm);
3467 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3469 goto err_80211_unwind;
3470 bcm43xx_wireless_core_disable(bcm);
3472 bcm43xx_pctl_set_crystal(bcm, 0);
3474 /* Set the MAC address in the networking subsystem */
3475 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
3476 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3478 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3480 bcm43xx_geo_init(bcm);
3482 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3483 "Broadcom %04X", bcm->chip_id);
3490 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3491 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3492 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3493 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3496 bcm43xx_chipset_detach(bcm);
3498 iounmap(bcm->mmio_addr);
3500 pci_release_regions(pci_dev);
3502 pci_disable_device(pci_dev);
3506 /* Do the Hardware IO operations to send the txb */
3507 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3508 struct ieee80211_txb *txb)
3512 if (bcm43xx_using_pio(bcm))
3513 err = bcm43xx_pio_tx(bcm, txb);
3515 err = bcm43xx_dma_tx(bcm, txb);
3520 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3523 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3524 unsigned long flags;
3526 bcm43xx_lock_mmio(bcm, flags);
3527 bcm43xx_mac_suspend(bcm);
3528 bcm43xx_radio_selectchannel(bcm, channel, 0);
3529 bcm43xx_mac_enable(bcm);
3530 bcm43xx_unlock_mmio(bcm, flags);
3533 /* set_security() callback in struct ieee80211_device */
3534 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3535 struct ieee80211_security *sec)
3537 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3538 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3539 unsigned long flags;
3542 dprintk(KERN_INFO PFX "set security called\n");
3544 bcm43xx_lock_mmio(bcm, flags);
3546 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3547 if (sec->flags & (1<<keyidx)) {
3548 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3549 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3550 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3553 if (sec->flags & SEC_ACTIVE_KEY) {
3554 secinfo->active_key = sec->active_key;
3555 dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
3557 if (sec->flags & SEC_UNICAST_GROUP) {
3558 secinfo->unicast_uses_group = sec->unicast_uses_group;
3559 dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
3561 if (sec->flags & SEC_LEVEL) {
3562 secinfo->level = sec->level;
3563 dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
3565 if (sec->flags & SEC_ENABLED) {
3566 secinfo->enabled = sec->enabled;
3567 dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
3569 if (sec->flags & SEC_ENCRYPT) {
3570 secinfo->encrypt = sec->encrypt;
3571 dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
3573 if (bcm->initialized && !bcm->ieee->host_encrypt) {
3574 if (secinfo->enabled) {
3575 /* upload WEP keys to hardware */
3576 char null_address[6] = { 0 };
3578 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3579 if (!(sec->flags & (1<<keyidx)))
3581 switch (sec->encode_alg[keyidx]) {
3582 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3584 algorithm = BCM43xx_SEC_ALGO_WEP;
3585 if (secinfo->key_sizes[keyidx] == 13)
3586 algorithm = BCM43xx_SEC_ALGO_WEP104;
3590 algorithm = BCM43xx_SEC_ALGO_TKIP;
3594 algorithm = BCM43xx_SEC_ALGO_AES;
3600 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3601 bcm->key[keyidx].enabled = 1;
3602 bcm->key[keyidx].algorithm = algorithm;
3605 bcm43xx_clear_keys(bcm);
3607 bcm43xx_unlock_mmio(bcm, flags);
3610 /* hard_start_xmit() callback in struct ieee80211_device */
3611 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3612 struct net_device *net_dev,
3615 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3617 unsigned long flags;
3619 bcm43xx_lock_mmio(bcm, flags);
3620 if (likely(bcm->initialized))
3621 err = bcm43xx_tx(bcm, txb);
3622 bcm43xx_unlock_mmio(bcm, flags);
3627 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3629 return &(bcm43xx_priv(net_dev)->ieee->stats);
3632 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3634 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3635 unsigned long flags;
3637 bcm43xx_lock_mmio(bcm, flags);
3638 bcm43xx_controller_restart(bcm, "TX timeout");
3639 bcm43xx_unlock_mmio(bcm, flags);
3642 #ifdef CONFIG_NET_POLL_CONTROLLER
3643 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3645 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3646 unsigned long flags;
3648 local_irq_save(flags);
3649 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3650 local_irq_restore(flags);
3652 #endif /* CONFIG_NET_POLL_CONTROLLER */
3654 static int bcm43xx_net_open(struct net_device *net_dev)
3656 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3658 return bcm43xx_init_board(bcm);
3661 static int bcm43xx_net_stop(struct net_device *net_dev)
3663 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3665 ieee80211softmac_stop(net_dev);
3666 bcm43xx_disable_interrupts_sync(bcm, NULL);
3667 bcm43xx_free_board(bcm);
3672 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3673 struct net_device *net_dev,
3674 struct pci_dev *pci_dev)
3678 bcm->ieee = netdev_priv(net_dev);
3679 bcm->softmac = ieee80211_priv(net_dev);
3680 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3682 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3683 bcm->pci_dev = pci_dev;
3684 bcm->net_dev = net_dev;
3685 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3686 spin_lock_init(&bcm->_lock);
3687 tasklet_init(&bcm->isr_tasklet,
3688 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3689 (unsigned long)bcm);
3690 tasklet_disable_nosync(&bcm->isr_tasklet);
3692 bcm->__using_pio = 1;
3694 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3695 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3697 #ifdef CONFIG_BCM43XX_PIO
3698 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3699 bcm->__using_pio = 1;
3701 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
3702 "Recompile the driver with PIO support, please.\n");
3704 #endif /* CONFIG_BCM43XX_PIO */
3707 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
3709 /* default to sw encryption for now */
3710 bcm->ieee->host_build_iv = 0;
3711 bcm->ieee->host_encrypt = 1;
3712 bcm->ieee->host_decrypt = 1;
3714 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
3715 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
3716 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
3717 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
3722 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
3723 const struct pci_device_id *ent)
3725 struct net_device *net_dev;
3726 struct bcm43xx_private *bcm;
3729 #ifdef CONFIG_BCM947XX
3730 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
3734 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3735 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
3739 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
3742 "could not allocate ieee80211 device %s\n",
3747 /* initialize the net_device struct */
3748 SET_MODULE_OWNER(net_dev);
3749 SET_NETDEV_DEV(net_dev, &pdev->dev);
3751 net_dev->open = bcm43xx_net_open;
3752 net_dev->stop = bcm43xx_net_stop;
3753 net_dev->get_stats = bcm43xx_net_get_stats;
3754 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
3755 #ifdef CONFIG_NET_POLL_CONTROLLER
3756 net_dev->poll_controller = bcm43xx_net_poll_controller;
3758 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
3759 net_dev->irq = pdev->irq;
3760 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
3762 /* initialize the bcm43xx_private struct */
3763 bcm = bcm43xx_priv(net_dev);
3764 memset(bcm, 0, sizeof(*bcm));
3765 err = bcm43xx_init_private(bcm, net_dev, pdev);
3767 goto err_free_netdev;
3769 pci_set_drvdata(pdev, net_dev);
3771 err = bcm43xx_attach_board(bcm);
3773 goto err_free_netdev;
3775 err = register_netdev(net_dev);
3777 printk(KERN_ERR PFX "Cannot register net device, "
3780 goto err_detach_board;
3783 bcm43xx_debugfs_add_device(bcm);
3790 bcm43xx_detach_board(bcm);
3792 free_ieee80211softmac(net_dev);
3796 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
3798 struct net_device *net_dev = pci_get_drvdata(pdev);
3799 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3801 bcm43xx_debugfs_remove_device(bcm);
3802 unregister_netdev(net_dev);
3803 bcm43xx_detach_board(bcm);
3804 assert(bcm->ucode == NULL);
3805 free_ieee80211softmac(net_dev);
3808 /* Hard-reset the chip. Do not call this directly.
3809 * Use bcm43xx_controller_restart()
3811 static void bcm43xx_chip_reset(void *_bcm)
3813 struct bcm43xx_private *bcm = _bcm;
3814 struct net_device *net_dev = bcm->net_dev;
3815 struct pci_dev *pci_dev = bcm->pci_dev;
3817 int was_initialized = bcm->initialized;
3819 netif_stop_queue(bcm->net_dev);
3820 tasklet_disable(&bcm->isr_tasklet);
3822 bcm->firmware_norelease = 1;
3823 if (was_initialized)
3824 bcm43xx_free_board(bcm);
3825 bcm->firmware_norelease = 0;
3826 bcm43xx_detach_board(bcm);
3827 err = bcm43xx_init_private(bcm, net_dev, pci_dev);
3830 err = bcm43xx_attach_board(bcm);
3833 if (was_initialized) {
3834 err = bcm43xx_init_board(bcm);
3838 netif_wake_queue(bcm->net_dev);
3839 printk(KERN_INFO PFX "Controller restarted\n");
3843 printk(KERN_ERR PFX "Controller restart failed\n");
3846 /* Hard-reset the chip.
3847 * This can be called from interrupt or process context.
3848 * Make sure to _not_ re-enable device interrupts after this has been called.
3850 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
3852 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3853 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
3854 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3855 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
3856 schedule_work(&bcm->restart_work);
3861 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
3863 struct net_device *net_dev = pci_get_drvdata(pdev);
3864 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3865 unsigned long flags;
3866 int try_to_shutdown = 0, err;
3868 dprintk(KERN_INFO PFX "Suspending...\n");
3870 bcm43xx_lock(bcm, flags);
3871 bcm->was_initialized = bcm->initialized;
3872 if (bcm->initialized)
3873 try_to_shutdown = 1;
3874 bcm43xx_unlock(bcm, flags);
3876 netif_device_detach(net_dev);
3877 if (try_to_shutdown) {
3878 ieee80211softmac_stop(net_dev);
3879 err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
3880 if (unlikely(err)) {
3881 dprintk(KERN_ERR PFX "Suspend failed.\n");
3884 bcm->firmware_norelease = 1;
3885 bcm43xx_free_board(bcm);
3886 bcm->firmware_norelease = 0;
3888 bcm43xx_chipset_detach(bcm);
3890 pci_save_state(pdev);
3891 pci_disable_device(pdev);
3892 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3894 dprintk(KERN_INFO PFX "Device suspended.\n");
3899 static int bcm43xx_resume(struct pci_dev *pdev)
3901 struct net_device *net_dev = pci_get_drvdata(pdev);
3902 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3905 dprintk(KERN_INFO PFX "Resuming...\n");
3907 pci_set_power_state(pdev, 0);
3908 pci_enable_device(pdev);
3909 pci_restore_state(pdev);
3911 bcm43xx_chipset_attach(bcm);
3912 if (bcm->was_initialized) {
3913 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3914 err = bcm43xx_init_board(bcm);
3917 printk(KERN_ERR PFX "Resume failed!\n");
3921 netif_device_attach(net_dev);
3923 /*FIXME: This should be handled by softmac instead. */
3924 schedule_work(&bcm->softmac->associnfo.work);
3926 dprintk(KERN_INFO PFX "Device resumed.\n");
3931 #endif /* CONFIG_PM */
3933 static struct pci_driver bcm43xx_pci_driver = {
3934 .name = KBUILD_MODNAME,
3935 .id_table = bcm43xx_pci_tbl,
3936 .probe = bcm43xx_init_one,
3937 .remove = __devexit_p(bcm43xx_remove_one),
3939 .suspend = bcm43xx_suspend,
3940 .resume = bcm43xx_resume,
3941 #endif /* CONFIG_PM */
3944 static int __init bcm43xx_init(void)
3946 printk(KERN_INFO KBUILD_MODNAME " driver\n");
3947 bcm43xx_debugfs_init();
3948 return pci_register_driver(&bcm43xx_pci_driver);
3951 static void __exit bcm43xx_exit(void)
3953 pci_unregister_driver(&bcm43xx_pci_driver);
3954 bcm43xx_debugfs_exit();
3957 module_init(bcm43xx_init)
3958 module_exit(bcm43xx_exit)