git.oblomov.eu Git - linux-2.6/blob - drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include <linux/netdevice.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/delay.h>
  60 #include <linux/pci.h>
  61
  62 #include "e1000.h"
  63
  64 #define ICH_FLASH_GFPREG                0x0000
  65 #define ICH_FLASH_HSFSTS                0x0004
  66 #define ICH_FLASH_HSFCTL                0x0006
  67 #define ICH_FLASH_FADDR                 0x0008
  68 #define ICH_FLASH_FDATA0                0x0010
  69 #define ICH_FLASH_PR0                   0x0074
  70
  71 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  74 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  75 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  76
  77 #define ICH_CYCLE_READ                  0
  78 #define ICH_CYCLE_WRITE                 2
  79 #define ICH_CYCLE_ERASE                 3
  80
  81 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  82 #define FLASH_SECTOR_ADDR_SHIFT         12
  83
  84 #define ICH_FLASH_SEG_SIZE_256          256
  85 #define ICH_FLASH_SEG_SIZE_4K           4096
  86 #define ICH_FLASH_SEG_SIZE_8K           8192
  87 #define ICH_FLASH_SEG_SIZE_64K          65536
  88
  89
  90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  91
  92 #define E1000_ICH_MNG_IAMT_MODE         0x2
  93
  94 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  95                                  (ID_LED_DEF1_OFF2 <<  8) | \
  96                                  (ID_LED_DEF1_ON2  <<  4) | \
  97                                  (ID_LED_DEF1_DEF2))
  98
  99 #define E1000_ICH_NVM_SIG_WORD          0x13
 100 #define E1000_ICH_NVM_SIG_MASK          0xC000
 101 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 102 #define E1000_ICH_NVM_SIG_VALUE         0x80
 103
 104 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 105
 106 #define E1000_FEXTNVM_SW_CONFIG         1
 107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 108
 109 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 110
 111 #define E1000_ICH_RAR_ENTRIES           7
 112
 113 #define PHY_PAGE_SHIFT 5
 114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 115                            ((reg) & MAX_PHY_REG_ADDRESS))
 116 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 117 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 118
 119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 121 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 122
 123 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 124
 125 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 126 /* Offset 04h HSFSTS */
 127 union ich8_hws_flash_status {
 128         struct ich8_hsfsts {
 129                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 130                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 131                 u16 dael       :1; /* bit 2 Direct Access error Log */
 132                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 133                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 134                 u16 reserved1  :2; /* bit 13:6 Reserved */
 135                 u16 reserved2  :6; /* bit 13:6 Reserved */
 136                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 137                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 138         } hsf_status;
 139         u16 regval;
 140 };
 141
 142 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 143 /* Offset 06h FLCTL */
 144 union ich8_hws_flash_ctrl {
 145         struct ich8_hsflctl {
 146                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 147                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 148                 u16 reserved   :5;   /* 7:3 Reserved  */
 149                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 150                 u16 flockdn    :6;   /* 15:10 Reserved */
 151         } hsf_ctrl;
 152         u16 regval;
 153 };
 154
 155 /* ICH Flash Region Access Permissions */
 156 union ich8_hws_flash_regacc {
 157         struct ich8_flracc {
 158                 u32 grra      :8; /* 0:7 GbE region Read Access */
 159                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 160                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 161                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 162         } hsf_flregacc;
 163         u16 regval;
 164 };
 165
 166 /* ICH Flash Protected Region */
 167 union ich8_flash_protected_range {
 168         struct ich8_pr {
 169                 u32 base:13;     /* 0:12 Protected Range Base */
 170                 u32 reserved1:2; /* 13:14 Reserved */
 171                 u32 rpe:1;       /* 15 Read Protection Enable */
 172                 u32 limit:13;    /* 16:28 Protected Range Limit */
 173                 u32 reserved2:2; /* 29:30 Reserved */
 174                 u32 wpe:1;       /* 31 Write Protection Enable */
 175         } range;
 176         u32 regval;
 177 };
 178
 179 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 180 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 181 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 182 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 183 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 184 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 185                                                 u32 offset, u8 byte);
 186 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 187                                          u8 *data);
 188 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 189                                          u16 *data);
 190 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 191                                          u8 size, u16 *data);
 192 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 193 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 194 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 195 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 196 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 197 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 199 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 200 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 201 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 202 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 203
 204 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 205 {
 206         return readw(hw->flash_address + reg);
 207 }
 208
 209 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 210 {
 211         return readl(hw->flash_address + reg);
 212 }
 213
 214 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 215 {
 216         writew(val, hw->flash_address + reg);
 217 }
 218
 219 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 220 {
 221         writel(val, hw->flash_address + reg);
 222 }
 223
 224 #define er16flash(reg)          __er16flash(hw, (reg))
 225 #define er32flash(reg)          __er32flash(hw, (reg))
 226 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 227 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 228
 229 /**
 230  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 231  *  @hw: pointer to the HW structure
 232  *
 233  *  Initialize family-specific PHY parameters and function pointers.
 234  **/
 235 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 236 {
 237         struct e1000_phy_info *phy = &hw->phy;
 238         s32 ret_val = 0;
 239
 240         phy->addr                     = 1;
 241         phy->reset_delay_us           = 100;
 242
 243         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 244         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 245         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 246         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 247
 248         phy->id = e1000_phy_unknown;
 249         e1000e_get_phy_id(hw);
 250         phy->type = e1000e_get_phy_type_from_id(phy->id);
 251
 252         if (phy->type == e1000_phy_82577) {
 253                 phy->ops.check_polarity = e1000_check_polarity_82577;
 254                 phy->ops.force_speed_duplex =
 255                         e1000_phy_force_speed_duplex_82577;
 256                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 257                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 258                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 259         }
 260
 261         return ret_val;
 262 }
 263
 264 /**
 265  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 266  *  @hw: pointer to the HW structure
 267  *
 268  *  Initialize family-specific PHY parameters and function pointers.
 269  **/
 270 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 271 {
 272         struct e1000_phy_info *phy = &hw->phy;
 273         s32 ret_val;
 274         u16 i = 0;
 275
 276         phy->addr                       = 1;
 277         phy->reset_delay_us             = 100;
 278
 279         /*
 280          * We may need to do this twice - once for IGP and if that fails,
 281          * we'll set BM func pointers and try again
 282          */
 283         ret_val = e1000e_determine_phy_address(hw);
 284         if (ret_val) {
 285                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 286                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 287                 ret_val = e1000e_determine_phy_address(hw);
 288                 if (ret_val)
 289                         return ret_val;
 290         }
 291
 292         phy->id = 0;
 293         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 294                (i++ < 100)) {
 295                 msleep(1);
 296                 ret_val = e1000e_get_phy_id(hw);
 297                 if (ret_val)
 298                         return ret_val;
 299         }
 300
 301         /* Verify phy id */
 302         switch (phy->id) {
 303         case IGP03E1000_E_PHY_ID:
 304                 phy->type = e1000_phy_igp_3;
 305                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 306                 break;
 307         case IFE_E_PHY_ID:
 308         case IFE_PLUS_E_PHY_ID:
 309         case IFE_C_E_PHY_ID:
 310                 phy->type = e1000_phy_ife;
 311                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 312                 break;
 313         case BME1000_E_PHY_ID:
 314                 phy->type = e1000_phy_bm;
 315                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 316                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 317                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 318                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 319                 break;
 320         default:
 321                 return -E1000_ERR_PHY;
 322                 break;
 323         }
 324
 325         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 326
 327         return 0;
 328 }
 329
 330 /**
 331  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Initialize family-specific NVM parameters and function
 335  *  pointers.
 336  **/
 337 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 338 {
 339         struct e1000_nvm_info *nvm = &hw->nvm;
 340         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 341         union ich8_hws_flash_status hsfsts;
 342         u32 gfpreg;
 343         u32 sector_base_addr;
 344         u32 sector_end_addr;
 345         u16 i;
 346
 347         /* Can't read flash registers if the register set isn't mapped. */
 348         if (!hw->flash_address) {
 349                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 350                 return -E1000_ERR_CONFIG;
 351         }
 352
 353         nvm->type = e1000_nvm_flash_sw;
 354
 355         gfpreg = er32flash(ICH_FLASH_GFPREG);
 356
 357         /*
 358          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 359          * Add 1 to sector_end_addr since this sector is included in
 360          * the overall size.
 361          */
 362         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 363         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 364
 365         /* flash_base_addr is byte-aligned */
 366         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 367
 368         /*
 369          * find total size of the NVM, then cut in half since the total
 370          * size represents two separate NVM banks.
 371          */
 372         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 373                                 << FLASH_SECTOR_ADDR_SHIFT;
 374         nvm->flash_bank_size /= 2;
 375         /* Adjust to word count */
 376         nvm->flash_bank_size /= sizeof(u16);
 377
 378         /*
 379          * Make sure the flash bank size does not overwrite the 4k
 380          * sector ranges. We may have 64k allotted to us but we only care
 381          * about the first 2 4k sectors. Therefore, if we have anything less
 382          * than 64k set in the HSFSTS register, we will reduce the bank size
 383          * down to 4k and let the rest remain unused. If berasesz == 3, then
 384          * we are working in 64k mode. Otherwise we are not.
 385          */
 386         if (nvm->flash_bank_size > E1000_ICH8_SHADOW_RAM_WORDS) {
 387                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 388                 if (hsfsts.hsf_status.berasesz != 3)
 389                         nvm->flash_bank_size = E1000_ICH8_SHADOW_RAM_WORDS;
 390         }
 391
 392         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 393
 394         /* Clear shadow ram */
 395         for (i = 0; i < nvm->word_size; i++) {
 396                 dev_spec->shadow_ram[i].modified = 0;
 397                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 398         }
 399
 400         return 0;
 401 }
 402
 403 /**
 404  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 405  *  @hw: pointer to the HW structure
 406  *
 407  *  Initialize family-specific MAC parameters and function
 408  *  pointers.
 409  **/
 410 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 411 {
 412         struct e1000_hw *hw = &adapter->hw;
 413         struct e1000_mac_info *mac = &hw->mac;
 414
 415         /* Set media type function pointer */
 416         hw->phy.media_type = e1000_media_type_copper;
 417
 418         /* Set mta register count */
 419         mac->mta_reg_count = 32;
 420         /* Set rar entry count */
 421         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 422         if (mac->type == e1000_ich8lan)
 423                 mac->rar_entry_count--;
 424         /* Set if manageability features are enabled. */
 425         mac->arc_subsystem_valid = 1;
 426
 427         /* LED operations */
 428         switch (mac->type) {
 429         case e1000_ich8lan:
 430         case e1000_ich9lan:
 431         case e1000_ich10lan:
 432                 /* ID LED init */
 433                 mac->ops.id_led_init = e1000e_id_led_init;
 434                 /* setup LED */
 435                 mac->ops.setup_led = e1000e_setup_led_generic;
 436                 /* cleanup LED */
 437                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 438                 /* turn on/off LED */
 439                 mac->ops.led_on = e1000_led_on_ich8lan;
 440                 mac->ops.led_off = e1000_led_off_ich8lan;
 441                 break;
 442         case e1000_pchlan:
 443                 /* ID LED init */
 444                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 445                 /* setup LED */
 446                 mac->ops.setup_led = e1000_setup_led_pchlan;
 447                 /* cleanup LED */
 448                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 449                 /* turn on/off LED */
 450                 mac->ops.led_on = e1000_led_on_pchlan;
 451                 mac->ops.led_off = e1000_led_off_pchlan;
 452                 break;
 453         default:
 454                 break;
 455         }
 456
 457         /* Enable PCS Lock-loss workaround for ICH8 */
 458         if (mac->type == e1000_ich8lan)
 459                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 460
 461         return 0;
 462 }
 463
 464 /**
 465  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 466  *  @hw: pointer to the HW structure
 467  *
 468  *  Checks to see of the link status of the hardware has changed.  If a
 469  *  change in link status has been detected, then we read the PHY registers
 470  *  to get the current speed/duplex if link exists.
 471  **/
 472 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 473 {
 474         struct e1000_mac_info *mac = &hw->mac;
 475         s32 ret_val;
 476         bool link;
 477
 478         /*
 479          * We only want to go out to the PHY registers to see if Auto-Neg
 480          * has completed and/or if our link status has changed.  The
 481          * get_link_status flag is set upon receiving a Link Status
 482          * Change or Rx Sequence Error interrupt.
 483          */
 484         if (!mac->get_link_status) {
 485                 ret_val = 0;
 486                 goto out;
 487         }
 488
 489         if (hw->mac.type == e1000_pchlan) {
 490                 ret_val = e1000e_write_kmrn_reg(hw,
 491                                                    E1000_KMRNCTRLSTA_K1_CONFIG,
 492                                                    E1000_KMRNCTRLSTA_K1_ENABLE);
 493                 if (ret_val)
 494                         goto out;
 495         }
 496
 497         /*
 498          * First we want to see if the MII Status Register reports
 499          * link.  If so, then we want to get the current speed/duplex
 500          * of the PHY.
 501          */
 502         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 503         if (ret_val)
 504                 goto out;
 505
 506         if (!link)
 507                 goto out; /* No link detected */
 508
 509         mac->get_link_status = false;
 510
 511         if (hw->phy.type == e1000_phy_82578) {
 512                 ret_val = e1000_link_stall_workaround_hv(hw);
 513                 if (ret_val)
 514                         goto out;
 515         }
 516
 517         /*
 518          * Check if there was DownShift, must be checked
 519          * immediately after link-up
 520          */
 521         e1000e_check_downshift(hw);
 522
 523         /*
 524          * If we are forcing speed/duplex, then we simply return since
 525          * we have already determined whether we have link or not.
 526          */
 527         if (!mac->autoneg) {
 528                 ret_val = -E1000_ERR_CONFIG;
 529                 goto out;
 530         }
 531
 532         /*
 533          * Auto-Neg is enabled.  Auto Speed Detection takes care
 534          * of MAC speed/duplex configuration.  So we only need to
 535          * configure Collision Distance in the MAC.
 536          */
 537         e1000e_config_collision_dist(hw);
 538
 539         /*
 540          * Configure Flow Control now that Auto-Neg has completed.
 541          * First, we need to restore the desired flow control
 542          * settings because we may have had to re-autoneg with a
 543          * different link partner.
 544          */
 545         ret_val = e1000e_config_fc_after_link_up(hw);
 546         if (ret_val)
 547                 hw_dbg(hw, "Error configuring flow control\n");
 548
 549 out:
 550         return ret_val;
 551 }
 552
 553 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 554 {
 555         struct e1000_hw *hw = &adapter->hw;
 556         s32 rc;
 557
 558         rc = e1000_init_mac_params_ich8lan(adapter);
 559         if (rc)
 560                 return rc;
 561
 562         rc = e1000_init_nvm_params_ich8lan(hw);
 563         if (rc)
 564                 return rc;
 565
 566         if (hw->mac.type == e1000_pchlan)
 567                 rc = e1000_init_phy_params_pchlan(hw);
 568         else
 569                 rc = e1000_init_phy_params_ich8lan(hw);
 570         if (rc)
 571                 return rc;
 572
 573         if (adapter->hw.phy.type == e1000_phy_ife) {
 574                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 575                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 576         }
 577
 578         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 579             (adapter->hw.phy.type == e1000_phy_igp_3))
 580                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 581
 582         return 0;
 583 }
 584
 585 static DEFINE_MUTEX(nvm_mutex);
 586
 587 /**
 588  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 589  *  @hw: pointer to the HW structure
 590  *
 591  *  Acquires the software control flag for performing NVM and PHY
 592  *  operations.  This is a function pointer entry point only called by
 593  *  read/write routines for the PHY and NVM parts.
 594  **/
 595 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 596 {
 597         u32 extcnf_ctrl;
 598         u32 timeout = PHY_CFG_TIMEOUT;
 599
 600         might_sleep();
 601
 602         mutex_lock(&nvm_mutex);
 603
 604         while (timeout) {
 605                 extcnf_ctrl = er32(EXTCNF_CTRL);
 606
 607                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
 608                         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 609                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 610
 611                         extcnf_ctrl = er32(EXTCNF_CTRL);
 612                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 613                                 break;
 614                 }
 615                 mdelay(1);
 616                 timeout--;
 617         }
 618
 619         if (!timeout) {
 620                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 621                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 622                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 623                 mutex_unlock(&nvm_mutex);
 624                 return -E1000_ERR_CONFIG;
 625         }
 626
 627         return 0;
 628 }
 629
 630 /**
 631  *  e1000_release_swflag_ich8lan - Release software control flag
 632  *  @hw: pointer to the HW structure
 633  *
 634  *  Releases the software control flag for performing NVM and PHY operations.
 635  *  This is a function pointer entry point only called by read/write
 636  *  routines for the PHY and NVM parts.
 637  **/
 638 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 639 {
 640         u32 extcnf_ctrl;
 641
 642         extcnf_ctrl = er32(EXTCNF_CTRL);
 643         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 644         ew32(EXTCNF_CTRL, extcnf_ctrl);
 645
 646         mutex_unlock(&nvm_mutex);
 647 }
 648
 649 /**
 650  *  e1000_check_mng_mode_ich8lan - Checks management mode
 651  *  @hw: pointer to the HW structure
 652  *
 653  *  This checks if the adapter has manageability enabled.
 654  *  This is a function pointer entry point only called by read/write
 655  *  routines for the PHY and NVM parts.
 656  **/
 657 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 658 {
 659         u32 fwsm = er32(FWSM);
 660
 661         return (fwsm & E1000_FWSM_MODE_MASK) ==
 662                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 663 }
 664
 665 /**
 666  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 667  *  @hw: pointer to the HW structure
 668  *
 669  *  Checks if firmware is blocking the reset of the PHY.
 670  *  This is a function pointer entry point only called by
 671  *  reset routines.
 672  **/
 673 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 674 {
 675         u32 fwsm;
 676
 677         fwsm = er32(FWSM);
 678
 679         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 680 }
 681
 682 /**
 683  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Forces the speed and duplex settings of the PHY.
 687  *  This is a function pointer entry point only called by
 688  *  PHY setup routines.
 689  **/
 690 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 691 {
 692         struct e1000_phy_info *phy = &hw->phy;
 693         s32 ret_val;
 694         u16 data;
 695         bool link;
 696
 697         if (phy->type != e1000_phy_ife) {
 698                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 699                 return ret_val;
 700         }
 701
 702         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 703         if (ret_val)
 704                 return ret_val;
 705
 706         e1000e_phy_force_speed_duplex_setup(hw, &data);
 707
 708         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 709         if (ret_val)
 710                 return ret_val;
 711
 712         /* Disable MDI-X support for 10/100 */
 713         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         data &= ~IFE_PMC_AUTO_MDIX;
 718         data &= ~IFE_PMC_FORCE_MDIX;
 719
 720         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 721         if (ret_val)
 722                 return ret_val;
 723
 724         hw_dbg(hw, "IFE PMC: %X\n", data);
 725
 726         udelay(1);
 727
 728         if (phy->autoneg_wait_to_complete) {
 729                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 730
 731                 ret_val = e1000e_phy_has_link_generic(hw,
 732                                                      PHY_FORCE_LIMIT,
 733                                                      100000,
 734                                                      &link);
 735                 if (ret_val)
 736                         return ret_val;
 737
 738                 if (!link)
 739                         hw_dbg(hw, "Link taking longer than expected.\n");
 740
 741                 /* Try once more */
 742                 ret_val = e1000e_phy_has_link_generic(hw,
 743                                                      PHY_FORCE_LIMIT,
 744                                                      100000,
 745                                                      &link);
 746                 if (ret_val)
 747                         return ret_val;
 748         }
 749
 750         return 0;
 751 }
 752
 753 /**
 754  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 755  *  done after every PHY reset.
 756  **/
 757 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 758 {
 759         s32 ret_val = 0;
 760
 761         if (hw->mac.type != e1000_pchlan)
 762                 return ret_val;
 763
 764         if (((hw->phy.type == e1000_phy_82577) &&
 765              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 766             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
 767                 /* Disable generation of early preamble */
 768                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
 769                 if (ret_val)
 770                         return ret_val;
 771
 772                 /* Preamble tuning for SSC */
 773                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
 774                 if (ret_val)
 775                         return ret_val;
 776         }
 777
 778         if (hw->phy.type == e1000_phy_82578) {
 779                 /*
 780                  * Return registers to default by doing a soft reset then
 781                  * writing 0x3140 to the control register.
 782                  */
 783                 if (hw->phy.revision < 2) {
 784                         e1000e_phy_sw_reset(hw);
 785                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
 786                 }
 787         }
 788
 789         /* Select page 0 */
 790         ret_val = hw->phy.ops.acquire_phy(hw);
 791         if (ret_val)
 792                 return ret_val;
 793         hw->phy.addr = 1;
 794         e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
 795         hw->phy.ops.release_phy(hw);
 796
 797         return ret_val;
 798 }
 799
 800 /**
 801  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 802  *  @hw: pointer to the HW structure
 803  *
 804  *  Check the appropriate indication the MAC has finished configuring the
 805  *  PHY after a software reset.
 806  **/
 807 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
 808 {
 809         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 810
 811         /* Wait for basic configuration completes before proceeding */
 812         do {
 813                 data = er32(STATUS);
 814                 data &= E1000_STATUS_LAN_INIT_DONE;
 815                 udelay(100);
 816         } while ((!data) && --loop);
 817
 818         /*
 819          * If basic configuration is incomplete before the above loop
 820          * count reaches 0, loading the configuration from NVM will
 821          * leave the PHY in a bad state possibly resulting in no link.
 822          */
 823         if (loop == 0)
 824                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 825
 826         /* Clear the Init Done bit for the next init event */
 827         data = er32(STATUS);
 828         data &= ~E1000_STATUS_LAN_INIT_DONE;
 829         ew32(STATUS, data);
 830 }
 831
 832 /**
 833  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 834  *  @hw: pointer to the HW structure
 835  *
 836  *  Resets the PHY
 837  *  This is a function pointer entry point called by drivers
 838  *  or other shared routines.
 839  **/
 840 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 841 {
 842         struct e1000_phy_info *phy = &hw->phy;
 843         u32 i;
 844         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 845         s32 ret_val;
 846         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 847
 848         ret_val = e1000e_phy_hw_reset_generic(hw);
 849         if (ret_val)
 850                 return ret_val;
 851
 852         /* Allow time for h/w to get to a quiescent state after reset */
 853         mdelay(10);
 854
 855         if (hw->mac.type == e1000_pchlan) {
 856                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 857                 if (ret_val)
 858                         return ret_val;
 859         }
 860
 861         /*
 862          * Initialize the PHY from the NVM on ICH platforms.  This
 863          * is needed due to an issue where the NVM configuration is
 864          * not properly autoloaded after power transitions.
 865          * Therefore, after each PHY reset, we will load the
 866          * configuration data out of the NVM manually.
 867          */
 868         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 869                 struct e1000_adapter *adapter = hw->adapter;
 870
 871                 /* Check if SW needs configure the PHY */
 872                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 873                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 874                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 875                 else
 876                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 877
 878                 data = er32(FEXTNVM);
 879                 if (!(data & sw_cfg_mask))
 880                         return 0;
 881
 882                 /* Wait for basic configuration completes before proceeding */
 883                 e1000_lan_init_done_ich8lan(hw);
 884
 885                 /*
 886                  * Make sure HW does not configure LCD from PHY
 887                  * extended configuration before SW configuration
 888                  */
 889                 data = er32(EXTCNF_CTRL);
 890                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 891                         return 0;
 892
 893                 cnf_size = er32(EXTCNF_SIZE);
 894                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 895                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 896                 if (!cnf_size)
 897                         return 0;
 898
 899                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 900                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 901
 902                 /* Configure LCD from extended configuration region. */
 903
 904                 /* cnf_base_addr is in DWORD */
 905                 word_addr = (u16)(cnf_base_addr << 1);
 906
 907                 for (i = 0; i < cnf_size; i++) {
 908                         ret_val = e1000_read_nvm(hw,
 909                                                 (word_addr + i * 2),
 910                                                 1,
 911                                                 &reg_data);
 912                         if (ret_val)
 913                                 return ret_val;
 914
 915                         ret_val = e1000_read_nvm(hw,
 916                                                 (word_addr + i * 2 + 1),
 917                                                 1,
 918                                                 &reg_addr);
 919                         if (ret_val)
 920                                 return ret_val;
 921
 922                         /* Save off the PHY page for future writes. */
 923                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 924                                 phy_page = reg_data;
 925                                 continue;
 926                         }
 927
 928                         reg_addr |= phy_page;
 929
 930                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 931                         if (ret_val)
 932                                 return ret_val;
 933                 }
 934         }
 935
 936         return 0;
 937 }
 938
 939 /**
 940  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 941  *  @hw: pointer to the HW structure
 942  *
 943  *  Populates "phy" structure with various feature states.
 944  *  This function is only called by other family-specific
 945  *  routines.
 946  **/
 947 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 948 {
 949         struct e1000_phy_info *phy = &hw->phy;
 950         s32 ret_val;
 951         u16 data;
 952         bool link;
 953
 954         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 955         if (ret_val)
 956                 return ret_val;
 957
 958         if (!link) {
 959                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 960                 return -E1000_ERR_CONFIG;
 961         }
 962
 963         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 964         if (ret_val)
 965                 return ret_val;
 966         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 967
 968         if (phy->polarity_correction) {
 969                 ret_val = phy->ops.check_polarity(hw);
 970                 if (ret_val)
 971                         return ret_val;
 972         } else {
 973                 /* Polarity is forced */
 974                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 975                                       ? e1000_rev_polarity_reversed
 976                                       : e1000_rev_polarity_normal;
 977         }
 978
 979         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 980         if (ret_val)
 981                 return ret_val;
 982
 983         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 984
 985         /* The following parameters are undefined for 10/100 operation. */
 986         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 987         phy->local_rx = e1000_1000t_rx_status_undefined;
 988         phy->remote_rx = e1000_1000t_rx_status_undefined;
 989
 990         return 0;
 991 }
 992
 993 /**
 994  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 995  *  @hw: pointer to the HW structure
 996  *
 997  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 998  *  This is a function pointer entry point called by drivers
 999  *  or other shared routines.
1000  **/
1001 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1002 {
1003         switch (hw->phy.type) {
1004         case e1000_phy_ife:
1005                 return e1000_get_phy_info_ife_ich8lan(hw);
1006                 break;
1007         case e1000_phy_igp_3:
1008         case e1000_phy_bm:
1009         case e1000_phy_82578:
1010         case e1000_phy_82577:
1011                 return e1000e_get_phy_info_igp(hw);
1012                 break;
1013         default:
1014                 break;
1015         }
1016
1017         return -E1000_ERR_PHY_TYPE;
1018 }
1019
1020 /**
1021  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1022  *  @hw: pointer to the HW structure
1023  *
1024  *  Polarity is determined on the polarity reversal feature being enabled.
1025  *  This function is only called by other family-specific
1026  *  routines.
1027  **/
1028 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1029 {
1030         struct e1000_phy_info *phy = &hw->phy;
1031         s32 ret_val;
1032         u16 phy_data, offset, mask;
1033
1034         /*
1035          * Polarity is determined based on the reversal feature being enabled.
1036          */
1037         if (phy->polarity_correction) {
1038                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1039                 mask    = IFE_PESC_POLARITY_REVERSED;
1040         } else {
1041                 offset  = IFE_PHY_SPECIAL_CONTROL;
1042                 mask    = IFE_PSC_FORCE_POLARITY;
1043         }
1044
1045         ret_val = e1e_rphy(hw, offset, &phy_data);
1046
1047         if (!ret_val)
1048                 phy->cable_polarity = (phy_data & mask)
1049                                       ? e1000_rev_polarity_reversed
1050                                       : e1000_rev_polarity_normal;
1051
1052         return ret_val;
1053 }
1054
1055 /**
1056  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1057  *  @hw: pointer to the HW structure
1058  *  @active: TRUE to enable LPLU, FALSE to disable
1059  *
1060  *  Sets the LPLU D0 state according to the active flag.  When
1061  *  activating LPLU this function also disables smart speed
1062  *  and vice versa.  LPLU will not be activated unless the
1063  *  device autonegotiation advertisement meets standards of
1064  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1065  *  This is a function pointer entry point only called by
1066  *  PHY setup routines.
1067  **/
1068 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1069 {
1070         struct e1000_phy_info *phy = &hw->phy;
1071         u32 phy_ctrl;
1072         s32 ret_val = 0;
1073         u16 data;
1074
1075         if (phy->type == e1000_phy_ife)
1076                 return ret_val;
1077
1078         phy_ctrl = er32(PHY_CTRL);
1079
1080         if (active) {
1081                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1082                 ew32(PHY_CTRL, phy_ctrl);
1083
1084                 if (phy->type != e1000_phy_igp_3)
1085                         return 0;
1086
1087                 /*
1088                  * Call gig speed drop workaround on LPLU before accessing
1089                  * any PHY registers
1090                  */
1091                 if (hw->mac.type == e1000_ich8lan)
1092                         e1000e_gig_downshift_workaround_ich8lan(hw);
1093
1094                 /* When LPLU is enabled, we should disable SmartSpeed */
1095                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1096                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1097                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1098                 if (ret_val)
1099                         return ret_val;
1100         } else {
1101                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1102                 ew32(PHY_CTRL, phy_ctrl);
1103
1104                 if (phy->type != e1000_phy_igp_3)
1105                         return 0;
1106
1107                 /*
1108                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1109                  * during Dx states where the power conservation is most
1110                  * important.  During driver activity we should enable
1111                  * SmartSpeed, so performance is maintained.
1112                  */
1113                 if (phy->smart_speed == e1000_smart_speed_on) {
1114                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1115                                            &data);
1116                         if (ret_val)
1117                                 return ret_val;
1118
1119                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1120                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1121                                            data);
1122                         if (ret_val)
1123                                 return ret_val;
1124                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1125                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1126                                            &data);
1127                         if (ret_val)
1128                                 return ret_val;
1129
1130                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1131                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1132                                            data);
1133                         if (ret_val)
1134                                 return ret_val;
1135                 }
1136         }
1137
1138         return 0;
1139 }
1140
1141 /**
1142  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1143  *  @hw: pointer to the HW structure
1144  *  @active: TRUE to enable LPLU, FALSE to disable
1145  *
1146  *  Sets the LPLU D3 state according to the active flag.  When
1147  *  activating LPLU this function also disables smart speed
1148  *  and vice versa.  LPLU will not be activated unless the
1149  *  device autonegotiation advertisement meets standards of
1150  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1151  *  This is a function pointer entry point only called by
1152  *  PHY setup routines.
1153  **/
1154 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1155 {
1156         struct e1000_phy_info *phy = &hw->phy;
1157         u32 phy_ctrl;
1158         s32 ret_val;
1159         u16 data;
1160
1161         phy_ctrl = er32(PHY_CTRL);
1162
1163         if (!active) {
1164                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1165                 ew32(PHY_CTRL, phy_ctrl);
1166
1167                 if (phy->type != e1000_phy_igp_3)
1168                         return 0;
1169
1170                 /*
1171                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1172                  * during Dx states where the power conservation is most
1173                  * important.  During driver activity we should enable
1174                  * SmartSpeed, so performance is maintained.
1175                  */
1176                 if (phy->smart_speed == e1000_smart_speed_on) {
1177                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1178                                            &data);
1179                         if (ret_val)
1180                                 return ret_val;
1181
1182                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1183                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1184                                            data);
1185                         if (ret_val)
1186                                 return ret_val;
1187                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1188                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1189                                            &data);
1190                         if (ret_val)
1191                                 return ret_val;
1192
1193                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1194                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1195                                            data);
1196                         if (ret_val)
1197                                 return ret_val;
1198                 }
1199         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1200                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1201                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1202                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1203                 ew32(PHY_CTRL, phy_ctrl);
1204
1205                 if (phy->type != e1000_phy_igp_3)
1206                         return 0;
1207
1208                 /*
1209                  * Call gig speed drop workaround on LPLU before accessing
1210                  * any PHY registers
1211                  */
1212                 if (hw->mac.type == e1000_ich8lan)
1213                         e1000e_gig_downshift_workaround_ich8lan(hw);
1214
1215                 /* When LPLU is enabled, we should disable SmartSpeed */
1216                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1217                 if (ret_val)
1218                         return ret_val;
1219
1220                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1221                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1222         }
1223
1224         return 0;
1225 }
1226
1227 /**
1228  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1229  *  @hw: pointer to the HW structure
1230  *  @bank:  pointer to the variable that returns the active bank
1231  *
1232  *  Reads signature byte from the NVM using the flash access registers.
1233  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1234  **/
1235 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1236 {
1237         u32 eecd;
1238         struct e1000_nvm_info *nvm = &hw->nvm;
1239         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1240         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1241         u8 sig_byte = 0;
1242         s32 ret_val = 0;
1243
1244         switch (hw->mac.type) {
1245         case e1000_ich8lan:
1246         case e1000_ich9lan:
1247                 eecd = er32(EECD);
1248                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1249                     E1000_EECD_SEC1VAL_VALID_MASK) {
1250                         if (eecd & E1000_EECD_SEC1VAL)
1251                                 *bank = 1;
1252                         else
1253                                 *bank = 0;
1254
1255                         return 0;
1256                 }
1257                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1258                        "reading flash signature\n");
1259                 /* fall-thru */
1260         default:
1261                 /* set bank to 0 in case flash read fails */
1262                 *bank = 0;
1263
1264                 /* Check bank 0 */
1265                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1266                                                         &sig_byte);
1267                 if (ret_val)
1268                         return ret_val;
1269                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1270                     E1000_ICH_NVM_SIG_VALUE) {
1271                         *bank = 0;
1272                         return 0;
1273                 }
1274
1275                 /* Check bank 1 */
1276                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1277                                                         bank1_offset,
1278                                                         &sig_byte);
1279                 if (ret_val)
1280                         return ret_val;
1281                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1282                     E1000_ICH_NVM_SIG_VALUE) {
1283                         *bank = 1;
1284                         return 0;
1285                 }
1286
1287                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1288                 return -E1000_ERR_NVM;
1289         }
1290
1291         return 0;
1292 }
1293
1294 /**
1295  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1296  *  @hw: pointer to the HW structure
1297  *  @offset: The offset (in bytes) of the word(s) to read.
1298  *  @words: Size of data to read in words
1299  *  @data: Pointer to the word(s) to read at offset.
1300  *
1301  *  Reads a word(s) from the NVM using the flash access registers.
1302  **/
1303 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1304                                   u16 *data)
1305 {
1306         struct e1000_nvm_info *nvm = &hw->nvm;
1307         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1308         u32 act_offset;
1309         s32 ret_val;
1310         u32 bank = 0;
1311         u16 i, word;
1312
1313         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1314             (words == 0)) {
1315                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1316                 return -E1000_ERR_NVM;
1317         }
1318
1319         ret_val = e1000_acquire_swflag_ich8lan(hw);
1320         if (ret_val)
1321                 goto out;
1322
1323         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1324         if (ret_val)
1325                 goto release;
1326
1327         act_offset = (bank) ? nvm->flash_bank_size : 0;
1328         act_offset += offset;
1329
1330         for (i = 0; i < words; i++) {
1331                 if ((dev_spec->shadow_ram) &&
1332                     (dev_spec->shadow_ram[offset+i].modified)) {
1333                         data[i] = dev_spec->shadow_ram[offset+i].value;
1334                 } else {
1335                         ret_val = e1000_read_flash_word_ich8lan(hw,
1336                                                                 act_offset + i,
1337                                                                 &word);
1338                         if (ret_val)
1339                                 break;
1340                         data[i] = word;
1341                 }
1342         }
1343
1344 release:
1345         e1000_release_swflag_ich8lan(hw);
1346
1347 out:
1348         if (ret_val)
1349                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1350
1351         return ret_val;
1352 }
1353
1354 /**
1355  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1356  *  @hw: pointer to the HW structure
1357  *
1358  *  This function does initial flash setup so that a new read/write/erase cycle
1359  *  can be started.
1360  **/
1361 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1362 {
1363         union ich8_hws_flash_status hsfsts;
1364         s32 ret_val = -E1000_ERR_NVM;
1365         s32 i = 0;
1366
1367         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1368
1369         /* Check if the flash descriptor is valid */
1370         if (hsfsts.hsf_status.fldesvalid == 0) {
1371                 hw_dbg(hw, "Flash descriptor invalid.  "
1372                          "SW Sequencing must be used.");
1373                 return -E1000_ERR_NVM;
1374         }
1375
1376         /* Clear FCERR and DAEL in hw status by writing 1 */
1377         hsfsts.hsf_status.flcerr = 1;
1378         hsfsts.hsf_status.dael = 1;
1379
1380         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1381
1382         /*
1383          * Either we should have a hardware SPI cycle in progress
1384          * bit to check against, in order to start a new cycle or
1385          * FDONE bit should be changed in the hardware so that it
1386          * is 1 after hardware reset, which can then be used as an
1387          * indication whether a cycle is in progress or has been
1388          * completed.
1389          */
1390
1391         if (hsfsts.hsf_status.flcinprog == 0) {
1392                 /*
1393                  * There is no cycle running at present,
1394                  * so we can start a cycle
1395                  * Begin by setting Flash Cycle Done.
1396                  */
1397                 hsfsts.hsf_status.flcdone = 1;
1398                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1399                 ret_val = 0;
1400         } else {
1401                 /*
1402                  * otherwise poll for sometime so the current
1403                  * cycle has a chance to end before giving up.
1404                  */
1405                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1406                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1407                         if (hsfsts.hsf_status.flcinprog == 0) {
1408                                 ret_val = 0;
1409                                 break;
1410                         }
1411                         udelay(1);
1412                 }
1413                 if (ret_val == 0) {
1414                         /*
1415                          * Successful in waiting for previous cycle to timeout,
1416                          * now set the Flash Cycle Done.
1417                          */
1418                         hsfsts.hsf_status.flcdone = 1;
1419                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1420                 } else {
1421                         hw_dbg(hw, "Flash controller busy, cannot get access");
1422                 }
1423         }
1424
1425         return ret_val;
1426 }
1427
1428 /**
1429  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1430  *  @hw: pointer to the HW structure
1431  *  @timeout: maximum time to wait for completion
1432  *
1433  *  This function starts a flash cycle and waits for its completion.
1434  **/
1435 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1436 {
1437         union ich8_hws_flash_ctrl hsflctl;
1438         union ich8_hws_flash_status hsfsts;
1439         s32 ret_val = -E1000_ERR_NVM;
1440         u32 i = 0;
1441
1442         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1443         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1444         hsflctl.hsf_ctrl.flcgo = 1;
1445         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1446
1447         /* wait till FDONE bit is set to 1 */
1448         do {
1449                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1450                 if (hsfsts.hsf_status.flcdone == 1)
1451                         break;
1452                 udelay(1);
1453         } while (i++ < timeout);
1454
1455         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1456                 return 0;
1457
1458         return ret_val;
1459 }
1460
1461 /**
1462  *  e1000_read_flash_word_ich8lan - Read word from flash
1463  *  @hw: pointer to the HW structure
1464  *  @offset: offset to data location
1465  *  @data: pointer to the location for storing the data
1466  *
1467  *  Reads the flash word at offset into data.  Offset is converted
1468  *  to bytes before read.
1469  **/
1470 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1471                                          u16 *data)
1472 {
1473         /* Must convert offset into bytes. */
1474         offset <<= 1;
1475
1476         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1477 }
1478
1479 /**
1480  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1481  *  @hw: pointer to the HW structure
1482  *  @offset: The offset of the byte to read.
1483  *  @data: Pointer to a byte to store the value read.
1484  *
1485  *  Reads a single byte from the NVM using the flash access registers.
1486  **/
1487 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1488                                          u8 *data)
1489 {
1490         s32 ret_val;
1491         u16 word = 0;
1492
1493         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1494         if (ret_val)
1495                 return ret_val;
1496
1497         *data = (u8)word;
1498
1499         return 0;
1500 }
1501
1502 /**
1503  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1504  *  @hw: pointer to the HW structure
1505  *  @offset: The offset (in bytes) of the byte or word to read.
1506  *  @size: Size of data to read, 1=byte 2=word
1507  *  @data: Pointer to the word to store the value read.
1508  *
1509  *  Reads a byte or word from the NVM using the flash access registers.
1510  **/
1511 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1512                                          u8 size, u16 *data)
1513 {
1514         union ich8_hws_flash_status hsfsts;
1515         union ich8_hws_flash_ctrl hsflctl;
1516         u32 flash_linear_addr;
1517         u32 flash_data = 0;
1518         s32 ret_val = -E1000_ERR_NVM;
1519         u8 count = 0;
1520
1521         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1522                 return -E1000_ERR_NVM;
1523
1524         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1525                             hw->nvm.flash_base_addr;
1526
1527         do {
1528                 udelay(1);
1529                 /* Steps */
1530                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1531                 if (ret_val != 0)
1532                         break;
1533
1534                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1535                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1536                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1537                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1538                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1539
1540                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1541
1542                 ret_val = e1000_flash_cycle_ich8lan(hw,
1543                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1544
1545                 /*
1546                  * Check if FCERR is set to 1, if set to 1, clear it
1547                  * and try the whole sequence a few more times, else
1548                  * read in (shift in) the Flash Data0, the order is
1549                  * least significant byte first msb to lsb
1550                  */
1551                 if (ret_val == 0) {
1552                         flash_data = er32flash(ICH_FLASH_FDATA0);
1553                         if (size == 1) {
1554                                 *data = (u8)(flash_data & 0x000000FF);
1555                         } else if (size == 2) {
1556                                 *data = (u16)(flash_data & 0x0000FFFF);
1557                         }
1558                         break;
1559                 } else {
1560                         /*
1561                          * If we've gotten here, then things are probably
1562                          * completely hosed, but if the error condition is
1563                          * detected, it won't hurt to give it another try...
1564                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1565                          */
1566                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1567                         if (hsfsts.hsf_status.flcerr == 1) {
1568                                 /* Repeat for some time before giving up. */
1569                                 continue;
1570                         } else if (hsfsts.hsf_status.flcdone == 0) {
1571                                 hw_dbg(hw, "Timeout error - flash cycle "
1572                                          "did not complete.");
1573                                 break;
1574                         }
1575                 }
1576         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1577
1578         return ret_val;
1579 }
1580
1581 /**
1582  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1583  *  @hw: pointer to the HW structure
1584  *  @offset: The offset (in bytes) of the word(s) to write.
1585  *  @words: Size of data to write in words
1586  *  @data: Pointer to the word(s) to write at offset.
1587  *
1588  *  Writes a byte or word to the NVM using the flash access registers.
1589  **/
1590 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1591                                    u16 *data)
1592 {
1593         struct e1000_nvm_info *nvm = &hw->nvm;
1594         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1595         s32 ret_val;
1596         u16 i;
1597
1598         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1599             (words == 0)) {
1600                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1601                 return -E1000_ERR_NVM;
1602         }
1603
1604         ret_val = e1000_acquire_swflag_ich8lan(hw);
1605         if (ret_val)
1606                 return ret_val;
1607
1608         for (i = 0; i < words; i++) {
1609                 dev_spec->shadow_ram[offset+i].modified = 1;
1610                 dev_spec->shadow_ram[offset+i].value = data[i];
1611         }
1612
1613         e1000_release_swflag_ich8lan(hw);
1614
1615         return 0;
1616 }
1617
1618 /**
1619  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1620  *  @hw: pointer to the HW structure
1621  *
1622  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1623  *  which writes the checksum to the shadow ram.  The changes in the shadow
1624  *  ram are then committed to the EEPROM by processing each bank at a time
1625  *  checking for the modified bit and writing only the pending changes.
1626  *  After a successful commit, the shadow ram is cleared and is ready for
1627  *  future writes.
1628  **/
1629 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1630 {
1631         struct e1000_nvm_info *nvm = &hw->nvm;
1632         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1633         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1634         s32 ret_val;
1635         u16 data;
1636
1637         ret_val = e1000e_update_nvm_checksum_generic(hw);
1638         if (ret_val)
1639                 goto out;
1640
1641         if (nvm->type != e1000_nvm_flash_sw)
1642                 goto out;
1643
1644         ret_val = e1000_acquire_swflag_ich8lan(hw);
1645         if (ret_val)
1646                 goto out;
1647
1648         /*
1649          * We're writing to the opposite bank so if we're on bank 1,
1650          * write to bank 0 etc.  We also need to erase the segment that
1651          * is going to be written
1652          */
1653         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1654         if (ret_val) {
1655                 e1000_release_swflag_ich8lan(hw);
1656                 goto out;
1657         }
1658
1659         if (bank == 0) {
1660                 new_bank_offset = nvm->flash_bank_size;
1661                 old_bank_offset = 0;
1662                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1663                 if (ret_val) {
1664                         e1000_release_swflag_ich8lan(hw);
1665                         goto out;
1666                 }
1667         } else {
1668                 old_bank_offset = nvm->flash_bank_size;
1669                 new_bank_offset = 0;
1670                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1671                 if (ret_val) {
1672                         e1000_release_swflag_ich8lan(hw);
1673                         goto out;
1674                 }
1675         }
1676
1677         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1678                 /*
1679                  * Determine whether to write the value stored
1680                  * in the other NVM bank or a modified value stored
1681                  * in the shadow RAM
1682                  */
1683                 if (dev_spec->shadow_ram[i].modified) {
1684                         data = dev_spec->shadow_ram[i].value;
1685                 } else {
1686                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1687                                                                 old_bank_offset,
1688                                                                 &data);
1689                         if (ret_val)
1690                                 break;
1691                 }
1692
1693                 /*
1694                  * If the word is 0x13, then make sure the signature bits
1695                  * (15:14) are 11b until the commit has completed.
1696                  * This will allow us to write 10b which indicates the
1697                  * signature is valid.  We want to do this after the write
1698                  * has completed so that we don't mark the segment valid
1699                  * while the write is still in progress
1700                  */
1701                 if (i == E1000_ICH_NVM_SIG_WORD)
1702                         data |= E1000_ICH_NVM_SIG_MASK;
1703
1704                 /* Convert offset to bytes. */
1705                 act_offset = (i + new_bank_offset) << 1;
1706
1707                 udelay(100);
1708                 /* Write the bytes to the new bank. */
1709                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1710                                                                act_offset,
1711                                                                (u8)data);
1712                 if (ret_val)
1713                         break;
1714
1715                 udelay(100);
1716                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1717                                                           act_offset + 1,
1718                                                           (u8)(data >> 8));
1719                 if (ret_val)
1720                         break;
1721         }
1722
1723         /*
1724          * Don't bother writing the segment valid bits if sector
1725          * programming failed.
1726          */
1727         if (ret_val) {
1728                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1729                 hw_dbg(hw, "Flash commit failed.\n");
1730                 e1000_release_swflag_ich8lan(hw);
1731                 goto out;
1732         }
1733
1734         /*
1735          * Finally validate the new segment by setting bit 15:14
1736          * to 10b in word 0x13 , this can be done without an
1737          * erase as well since these bits are 11 to start with
1738          * and we need to change bit 14 to 0b
1739          */
1740         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1741         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1742         if (ret_val) {
1743                 e1000_release_swflag_ich8lan(hw);
1744                 goto out;
1745         }
1746         data &= 0xBFFF;
1747         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1748                                                        act_offset * 2 + 1,
1749                                                        (u8)(data >> 8));
1750         if (ret_val) {
1751                 e1000_release_swflag_ich8lan(hw);
1752                 goto out;
1753         }
1754
1755         /*
1756          * And invalidate the previously valid segment by setting
1757          * its signature word (0x13) high_byte to 0b. This can be
1758          * done without an erase because flash erase sets all bits
1759          * to 1's. We can write 1's to 0's without an erase
1760          */
1761         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1762         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1763         if (ret_val) {
1764                 e1000_release_swflag_ich8lan(hw);
1765                 goto out;
1766         }
1767
1768         /* Great!  Everything worked, we can now clear the cached entries. */
1769         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1770                 dev_spec->shadow_ram[i].modified = 0;
1771                 dev_spec->shadow_ram[i].value = 0xFFFF;
1772         }
1773
1774         e1000_release_swflag_ich8lan(hw);
1775
1776         /*
1777          * Reload the EEPROM, or else modifications will not appear
1778          * until after the next adapter reset.
1779          */
1780         e1000e_reload_nvm(hw);
1781         msleep(10);
1782
1783 out:
1784         if (ret_val)
1785                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1786
1787         return ret_val;
1788 }
1789
1790 /**
1791  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1792  *  @hw: pointer to the HW structure
1793  *
1794  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1795  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1796  *  calculated, in which case we need to calculate the checksum and set bit 6.
1797  **/
1798 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1799 {
1800         s32 ret_val;
1801         u16 data;
1802
1803         /*
1804          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1805          * needs to be fixed.  This bit is an indication that the NVM
1806          * was prepared by OEM software and did not calculate the
1807          * checksum...a likely scenario.
1808          */
1809         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1810         if (ret_val)
1811                 return ret_val;
1812
1813         if ((data & 0x40) == 0) {
1814                 data |= 0x40;
1815                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1816                 if (ret_val)
1817                         return ret_val;
1818                 ret_val = e1000e_update_nvm_checksum(hw);
1819                 if (ret_val)
1820                         return ret_val;
1821         }
1822
1823         return e1000e_validate_nvm_checksum_generic(hw);
1824 }
1825
1826 /**
1827  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1828  *  @hw: pointer to the HW structure
1829  *
1830  *  To prevent malicious write/erase of the NVM, set it to be read-only
1831  *  so that the hardware ignores all write/erase cycles of the NVM via
1832  *  the flash control registers.  The shadow-ram copy of the NVM will
1833  *  still be updated, however any updates to this copy will not stick
1834  *  across driver reloads.
1835  **/
1836 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1837 {
1838         union ich8_flash_protected_range pr0;
1839         union ich8_hws_flash_status hsfsts;
1840         u32 gfpreg;
1841         s32 ret_val;
1842
1843         ret_val = e1000_acquire_swflag_ich8lan(hw);
1844         if (ret_val)
1845                 return;
1846
1847         gfpreg = er32flash(ICH_FLASH_GFPREG);
1848
1849         /* Write-protect GbE Sector of NVM */
1850         pr0.regval = er32flash(ICH_FLASH_PR0);
1851         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1852         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1853         pr0.range.wpe = true;
1854         ew32flash(ICH_FLASH_PR0, pr0.regval);
1855
1856         /*
1857          * Lock down a subset of GbE Flash Control Registers, e.g.
1858          * PR0 to prevent the write-protection from being lifted.
1859          * Once FLOCKDN is set, the registers protected by it cannot
1860          * be written until FLOCKDN is cleared by a hardware reset.
1861          */
1862         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1863         hsfsts.hsf_status.flockdn = true;
1864         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1865
1866         e1000_release_swflag_ich8lan(hw);
1867 }
1868
1869 /**
1870  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1871  *  @hw: pointer to the HW structure
1872  *  @offset: The offset (in bytes) of the byte/word to read.
1873  *  @size: Size of data to read, 1=byte 2=word
1874  *  @data: The byte(s) to write to the NVM.
1875  *
1876  *  Writes one/two bytes to the NVM using the flash access registers.
1877  **/
1878 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1879                                           u8 size, u16 data)
1880 {
1881         union ich8_hws_flash_status hsfsts;
1882         union ich8_hws_flash_ctrl hsflctl;
1883         u32 flash_linear_addr;
1884         u32 flash_data = 0;
1885         s32 ret_val;
1886         u8 count = 0;
1887
1888         if (size < 1 || size > 2 || data > size * 0xff ||
1889             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1890                 return -E1000_ERR_NVM;
1891
1892         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1893                             hw->nvm.flash_base_addr;
1894
1895         do {
1896                 udelay(1);
1897                 /* Steps */
1898                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1899                 if (ret_val)
1900                         break;
1901
1902                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1903                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1904                 hsflctl.hsf_ctrl.fldbcount = size -1;
1905                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1906                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1907
1908                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1909
1910                 if (size == 1)
1911                         flash_data = (u32)data & 0x00FF;
1912                 else
1913                         flash_data = (u32)data;
1914
1915                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1916
1917                 /*
1918                  * check if FCERR is set to 1 , if set to 1, clear it
1919                  * and try the whole sequence a few more times else done
1920                  */
1921                 ret_val = e1000_flash_cycle_ich8lan(hw,
1922                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1923                 if (!ret_val)
1924                         break;
1925
1926                 /*
1927                  * If we're here, then things are most likely
1928                  * completely hosed, but if the error condition
1929                  * is detected, it won't hurt to give it another
1930                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1931                  */
1932                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1933                 if (hsfsts.hsf_status.flcerr == 1)
1934                         /* Repeat for some time before giving up. */
1935                         continue;
1936                 if (hsfsts.hsf_status.flcdone == 0) {
1937                         hw_dbg(hw, "Timeout error - flash cycle "
1938                                  "did not complete.");
1939                         break;
1940                 }
1941         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1942
1943         return ret_val;
1944 }
1945
1946 /**
1947  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1948  *  @hw: pointer to the HW structure
1949  *  @offset: The index of the byte to read.
1950  *  @data: The byte to write to the NVM.
1951  *
1952  *  Writes a single byte to the NVM using the flash access registers.
1953  **/
1954 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1955                                           u8 data)
1956 {
1957         u16 word = (u16)data;
1958
1959         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1960 }
1961
1962 /**
1963  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1964  *  @hw: pointer to the HW structure
1965  *  @offset: The offset of the byte to write.
1966  *  @byte: The byte to write to the NVM.
1967  *
1968  *  Writes a single byte to the NVM using the flash access registers.
1969  *  Goes through a retry algorithm before giving up.
1970  **/
1971 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1972                                                 u32 offset, u8 byte)
1973 {
1974         s32 ret_val;
1975         u16 program_retries;
1976
1977         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1978         if (!ret_val)
1979                 return ret_val;
1980
1981         for (program_retries = 0; program_retries < 100; program_retries++) {
1982                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1983                 udelay(100);
1984                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1985                 if (!ret_val)
1986                         break;
1987         }
1988         if (program_retries == 100)
1989                 return -E1000_ERR_NVM;
1990
1991         return 0;
1992 }
1993
1994 /**
1995  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1996  *  @hw: pointer to the HW structure
1997  *  @bank: 0 for first bank, 1 for second bank, etc.
1998  *
1999  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2000  *  bank N is 4096 * N + flash_reg_addr.
2001  **/
2002 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2003 {
2004         struct e1000_nvm_info *nvm = &hw->nvm;
2005         union ich8_hws_flash_status hsfsts;
2006         union ich8_hws_flash_ctrl hsflctl;
2007         u32 flash_linear_addr;
2008         /* bank size is in 16bit words - adjust to bytes */
2009         u32 flash_bank_size = nvm->flash_bank_size * 2;
2010         s32 ret_val;
2011         s32 count = 0;
2012         s32 iteration;
2013         s32 sector_size;
2014         s32 j;
2015
2016         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2017
2018         /*
2019          * Determine HW Sector size: Read BERASE bits of hw flash status
2020          * register
2021          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2022          *     consecutive sectors.  The start index for the nth Hw sector
2023          *     can be calculated as = bank * 4096 + n * 256
2024          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2025          *     The start index for the nth Hw sector can be calculated
2026          *     as = bank * 4096
2027          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2028          *     (ich9 only, otherwise error condition)
2029          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2030          */
2031         switch (hsfsts.hsf_status.berasesz) {
2032         case 0:
2033                 /* Hw sector size 256 */
2034                 sector_size = ICH_FLASH_SEG_SIZE_256;
2035                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2036                 break;
2037         case 1:
2038                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2039                 iteration = 1;
2040                 break;
2041         case 2:
2042                 if (hw->mac.type == e1000_ich9lan) {
2043                         sector_size = ICH_FLASH_SEG_SIZE_8K;
2044                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
2045                 } else {
2046                         return -E1000_ERR_NVM;
2047                 }
2048                 break;
2049         case 3:
2050                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2051                 iteration = 1;
2052                 break;
2053         default:
2054                 return -E1000_ERR_NVM;
2055         }
2056
2057         /* Start with the base address, then add the sector offset. */
2058         flash_linear_addr = hw->nvm.flash_base_addr;
2059         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
2060
2061         for (j = 0; j < iteration ; j++) {
2062                 do {
2063                         /* Steps */
2064                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2065                         if (ret_val)
2066                                 return ret_val;
2067
2068                         /*
2069                          * Write a value 11 (block Erase) in Flash
2070                          * Cycle field in hw flash control
2071                          */
2072                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2073                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2074                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2075
2076                         /*
2077                          * Write the last 24 bits of an index within the
2078                          * block into Flash Linear address field in Flash
2079                          * Address.
2080                          */
2081                         flash_linear_addr += (j * sector_size);
2082                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2083
2084                         ret_val = e1000_flash_cycle_ich8lan(hw,
2085                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2086                         if (ret_val == 0)
2087                                 break;
2088
2089                         /*
2090                          * Check if FCERR is set to 1.  If 1,
2091                          * clear it and try the whole sequence
2092                          * a few more times else Done
2093                          */
2094                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2095                         if (hsfsts.hsf_status.flcerr == 1)
2096                                 /* repeat for some time before giving up */
2097                                 continue;
2098                         else if (hsfsts.hsf_status.flcdone == 0)
2099                                 return ret_val;
2100                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2101         }
2102
2103         return 0;
2104 }
2105
2106 /**
2107  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2108  *  @hw: pointer to the HW structure
2109  *  @data: Pointer to the LED settings
2110  *
2111  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2112  *  settings is all 0's or F's, set the LED default to a valid LED default
2113  *  setting.
2114  **/
2115 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2116 {
2117         s32 ret_val;
2118
2119         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2120         if (ret_val) {
2121                 hw_dbg(hw, "NVM Read Error\n");
2122                 return ret_val;
2123         }
2124
2125         if (*data == ID_LED_RESERVED_0000 ||
2126             *data == ID_LED_RESERVED_FFFF)
2127                 *data = ID_LED_DEFAULT_ICH8LAN;
2128
2129         return 0;
2130 }
2131
2132 /**
2133  *  e1000_id_led_init_pchlan - store LED configurations
2134  *  @hw: pointer to the HW structure
2135  *
2136  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2137  *  the PHY LED configuration register.
2138  *
2139  *  PCH also does not have an "always on" or "always off" mode which
2140  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2141  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2142  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2143  *  link based on logic in e1000_led_[on|off]_pchlan().
2144  **/
2145 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2146 {
2147         struct e1000_mac_info *mac = &hw->mac;
2148         s32 ret_val;
2149         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2150         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2151         u16 data, i, temp, shift;
2152
2153         /* Get default ID LED modes */
2154         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2155         if (ret_val)
2156                 goto out;
2157
2158         mac->ledctl_default = er32(LEDCTL);
2159         mac->ledctl_mode1 = mac->ledctl_default;
2160         mac->ledctl_mode2 = mac->ledctl_default;
2161
2162         for (i = 0; i < 4; i++) {
2163                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2164                 shift = (i * 5);
2165                 switch (temp) {
2166                 case ID_LED_ON1_DEF2:
2167                 case ID_LED_ON1_ON2:
2168                 case ID_LED_ON1_OFF2:
2169                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2170                         mac->ledctl_mode1 |= (ledctl_on << shift);
2171                         break;
2172                 case ID_LED_OFF1_DEF2:
2173                 case ID_LED_OFF1_ON2:
2174                 case ID_LED_OFF1_OFF2:
2175                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2176                         mac->ledctl_mode1 |= (ledctl_off << shift);
2177                         break;
2178                 default:
2179                         /* Do nothing */
2180                         break;
2181                 }
2182                 switch (temp) {
2183                 case ID_LED_DEF1_ON2:
2184                 case ID_LED_ON1_ON2:
2185                 case ID_LED_OFF1_ON2:
2186                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2187                         mac->ledctl_mode2 |= (ledctl_on << shift);
2188                         break;
2189                 case ID_LED_DEF1_OFF2:
2190                 case ID_LED_ON1_OFF2:
2191                 case ID_LED_OFF1_OFF2:
2192                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2193                         mac->ledctl_mode2 |= (ledctl_off << shift);
2194                         break;
2195                 default:
2196                         /* Do nothing */
2197                         break;
2198                 }
2199         }
2200
2201 out:
2202         return ret_val;
2203 }
2204
2205 /**
2206  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2207  *  @hw: pointer to the HW structure
2208  *
2209  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2210  *  register, so the the bus width is hard coded.
2211  **/
2212 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2213 {
2214         struct e1000_bus_info *bus = &hw->bus;
2215         s32 ret_val;
2216
2217         ret_val = e1000e_get_bus_info_pcie(hw);
2218
2219         /*
2220          * ICH devices are "PCI Express"-ish.  They have
2221          * a configuration space, but do not contain
2222          * PCI Express Capability registers, so bus width
2223          * must be hardcoded.
2224          */
2225         if (bus->width == e1000_bus_width_unknown)
2226                 bus->width = e1000_bus_width_pcie_x1;
2227
2228         return ret_val;
2229 }
2230
2231 /**
2232  *  e1000_reset_hw_ich8lan - Reset the hardware
2233  *  @hw: pointer to the HW structure
2234  *
2235  *  Does a full reset of the hardware which includes a reset of the PHY and
2236  *  MAC.
2237  **/
2238 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2239 {
2240         u32 ctrl, icr, kab;
2241         s32 ret_val;
2242
2243         /*
2244          * Prevent the PCI-E bus from sticking if there is no TLP connection
2245          * on the last TLP read/write transaction when MAC is reset.
2246          */
2247         ret_val = e1000e_disable_pcie_master(hw);
2248         if (ret_val) {
2249                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2250         }
2251
2252         hw_dbg(hw, "Masking off all interrupts\n");
2253         ew32(IMC, 0xffffffff);
2254
2255         /*
2256          * Disable the Transmit and Receive units.  Then delay to allow
2257          * any pending transactions to complete before we hit the MAC
2258          * with the global reset.
2259          */
2260         ew32(RCTL, 0);
2261         ew32(TCTL, E1000_TCTL_PSP);
2262         e1e_flush();
2263
2264         msleep(10);
2265
2266         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2267         if (hw->mac.type == e1000_ich8lan) {
2268                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2269                 ew32(PBA, E1000_PBA_8K);
2270                 /* Set Packet Buffer Size to 16k. */
2271                 ew32(PBS, E1000_PBS_16K);
2272         }
2273
2274         ctrl = er32(CTRL);
2275
2276         if (!e1000_check_reset_block(hw)) {
2277                 /* Clear PHY Reset Asserted bit */
2278                 if (hw->mac.type >= e1000_pchlan) {
2279                         u32 status = er32(STATUS);
2280                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2281                 }
2282
2283                 /*
2284                  * PHY HW reset requires MAC CORE reset at the same
2285                  * time to make sure the interface between MAC and the
2286                  * external PHY is reset.
2287                  */
2288                 ctrl |= E1000_CTRL_PHY_RST;
2289         }
2290         ret_val = e1000_acquire_swflag_ich8lan(hw);
2291         /* Whether or not the swflag was acquired, we need to reset the part */
2292         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2293         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2294         msleep(20);
2295
2296         if (!ret_val)
2297                 e1000_release_swflag_ich8lan(hw);
2298
2299         if (ctrl & E1000_CTRL_PHY_RST)
2300                 ret_val = hw->phy.ops.get_cfg_done(hw);
2301
2302         if (hw->mac.type >= e1000_ich10lan) {
2303                 e1000_lan_init_done_ich8lan(hw);
2304         } else {
2305                 ret_val = e1000e_get_auto_rd_done(hw);
2306                 if (ret_val) {
2307                         /*
2308                          * When auto config read does not complete, do not
2309                          * return with an error. This can happen in situations
2310                          * where there is no eeprom and prevents getting link.
2311                          */
2312                         hw_dbg(hw, "Auto Read Done did not complete\n");
2313                 }
2314         }
2315
2316         /*
2317          * For PCH, this write will make sure that any noise
2318          * will be detected as a CRC error and be dropped rather than show up
2319          * as a bad packet to the DMA engine.
2320          */
2321         if (hw->mac.type == e1000_pchlan)
2322                 ew32(CRC_OFFSET, 0x65656565);
2323
2324         ew32(IMC, 0xffffffff);
2325         icr = er32(ICR);
2326
2327         kab = er32(KABGTXD);
2328         kab |= E1000_KABGTXD_BGSQLBIAS;
2329         ew32(KABGTXD, kab);
2330
2331         if (hw->mac.type == e1000_pchlan)
2332                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2333
2334         return ret_val;
2335 }
2336
2337 /**
2338  *  e1000_init_hw_ich8lan - Initialize the hardware
2339  *  @hw: pointer to the HW structure
2340  *
2341  *  Prepares the hardware for transmit and receive by doing the following:
2342  *   - initialize hardware bits
2343  *   - initialize LED identification
2344  *   - setup receive address registers
2345  *   - setup flow control
2346  *   - setup transmit descriptors
2347  *   - clear statistics
2348  **/
2349 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2350 {
2351         struct e1000_mac_info *mac = &hw->mac;
2352         u32 ctrl_ext, txdctl, snoop;
2353         s32 ret_val;
2354         u16 i;
2355
2356         e1000_initialize_hw_bits_ich8lan(hw);
2357
2358         /* Initialize identification LED */
2359         ret_val = mac->ops.id_led_init(hw);
2360         if (ret_val) {
2361                 hw_dbg(hw, "Error initializing identification LED\n");
2362                 return ret_val;
2363         }
2364
2365         /* Setup the receive address. */
2366         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2367
2368         /* Zero out the Multicast HASH table */
2369         hw_dbg(hw, "Zeroing the MTA\n");
2370         for (i = 0; i < mac->mta_reg_count; i++)
2371                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2372
2373         /*
2374          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2375          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2376          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2377          */
2378         if (hw->phy.type == e1000_phy_82578) {
2379                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2380                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2381                 if (ret_val)
2382                         return ret_val;
2383         }
2384
2385         /* Setup link and flow control */
2386         ret_val = e1000_setup_link_ich8lan(hw);
2387
2388         /* Set the transmit descriptor write-back policy for both queues */
2389         txdctl = er32(TXDCTL(0));
2390         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2391                  E1000_TXDCTL_FULL_TX_DESC_WB;
2392         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2393                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2394         ew32(TXDCTL(0), txdctl);
2395         txdctl = er32(TXDCTL(1));
2396         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2397                  E1000_TXDCTL_FULL_TX_DESC_WB;
2398         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2399                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2400         ew32(TXDCTL(1), txdctl);
2401
2402         /*
2403          * ICH8 has opposite polarity of no_snoop bits.
2404          * By default, we should use snoop behavior.
2405          */
2406         if (mac->type == e1000_ich8lan)
2407                 snoop = PCIE_ICH8_SNOOP_ALL;
2408         else
2409                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2410         e1000e_set_pcie_no_snoop(hw, snoop);
2411
2412         ctrl_ext = er32(CTRL_EXT);
2413         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2414         ew32(CTRL_EXT, ctrl_ext);
2415
2416         /*
2417          * Clear all of the statistics registers (clear on read).  It is
2418          * important that we do this after we have tried to establish link
2419          * because the symbol error count will increment wildly if there
2420          * is no link.
2421          */
2422         e1000_clear_hw_cntrs_ich8lan(hw);
2423
2424         return 0;
2425 }
2426 /**
2427  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2428  *  @hw: pointer to the HW structure
2429  *
2430  *  Sets/Clears required hardware bits necessary for correctly setting up the
2431  *  hardware for transmit and receive.
2432  **/
2433 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2434 {
2435         u32 reg;
2436
2437         /* Extended Device Control */
2438         reg = er32(CTRL_EXT);
2439         reg |= (1 << 22);
2440         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2441         if (hw->mac.type >= e1000_pchlan)
2442                 reg |= E1000_CTRL_EXT_PHYPDEN;
2443         ew32(CTRL_EXT, reg);
2444
2445         /* Transmit Descriptor Control 0 */
2446         reg = er32(TXDCTL(0));
2447         reg |= (1 << 22);
2448         ew32(TXDCTL(0), reg);
2449
2450         /* Transmit Descriptor Control 1 */
2451         reg = er32(TXDCTL(1));
2452         reg |= (1 << 22);
2453         ew32(TXDCTL(1), reg);
2454
2455         /* Transmit Arbitration Control 0 */
2456         reg = er32(TARC(0));
2457         if (hw->mac.type == e1000_ich8lan)
2458                 reg |= (1 << 28) | (1 << 29);
2459         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2460         ew32(TARC(0), reg);
2461
2462         /* Transmit Arbitration Control 1 */
2463         reg = er32(TARC(1));
2464         if (er32(TCTL) & E1000_TCTL_MULR)
2465                 reg &= ~(1 << 28);
2466         else
2467                 reg |= (1 << 28);
2468         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2469         ew32(TARC(1), reg);
2470
2471         /* Device Status */
2472         if (hw->mac.type == e1000_ich8lan) {
2473                 reg = er32(STATUS);
2474                 reg &= ~(1 << 31);
2475                 ew32(STATUS, reg);
2476         }
2477 }
2478
2479 /**
2480  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2481  *  @hw: pointer to the HW structure
2482  *
2483  *  Determines which flow control settings to use, then configures flow
2484  *  control.  Calls the appropriate media-specific link configuration
2485  *  function.  Assuming the adapter has a valid link partner, a valid link
2486  *  should be established.  Assumes the hardware has previously been reset
2487  *  and the transmitter and receiver are not enabled.
2488  **/
2489 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2490 {
2491         s32 ret_val;
2492
2493         if (e1000_check_reset_block(hw))
2494                 return 0;
2495
2496         /*
2497          * ICH parts do not have a word in the NVM to determine
2498          * the default flow control setting, so we explicitly
2499          * set it to full.
2500          */
2501         if (hw->fc.requested_mode == e1000_fc_default) {
2502                 /* Workaround h/w hang when Tx flow control enabled */
2503                 if (hw->mac.type == e1000_pchlan)
2504                         hw->fc.requested_mode = e1000_fc_rx_pause;
2505                 else
2506                         hw->fc.requested_mode = e1000_fc_full;
2507         }
2508
2509         /*
2510          * Save off the requested flow control mode for use later.  Depending
2511          * on the link partner's capabilities, we may or may not use this mode.
2512          */
2513         hw->fc.current_mode = hw->fc.requested_mode;
2514
2515         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2516                 hw->fc.current_mode);
2517
2518         /* Continue to configure the copper link. */
2519         ret_val = e1000_setup_copper_link_ich8lan(hw);
2520         if (ret_val)
2521                 return ret_val;
2522
2523         ew32(FCTTV, hw->fc.pause_time);
2524         if ((hw->phy.type == e1000_phy_82578) ||
2525             (hw->phy.type == e1000_phy_82577)) {
2526                 ret_val = hw->phy.ops.write_phy_reg(hw,
2527                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2528                                              hw->fc.pause_time);
2529                 if (ret_val)
2530                         return ret_val;
2531         }
2532
2533         return e1000e_set_fc_watermarks(hw);
2534 }
2535
2536 /**
2537  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2538  *  @hw: pointer to the HW structure
2539  *
2540  *  Configures the kumeran interface to the PHY to wait the appropriate time
2541  *  when polling the PHY, then call the generic setup_copper_link to finish
2542  *  configuring the copper link.
2543  **/
2544 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2545 {
2546         u32 ctrl;
2547         s32 ret_val;
2548         u16 reg_data;
2549
2550         ctrl = er32(CTRL);
2551         ctrl |= E1000_CTRL_SLU;
2552         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2553         ew32(CTRL, ctrl);
2554
2555         /*
2556          * Set the mac to wait the maximum time between each iteration
2557          * and increase the max iterations when polling the phy;
2558          * this fixes erroneous timeouts at 10Mbps.
2559          */
2560         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2561         if (ret_val)
2562                 return ret_val;
2563         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2564         if (ret_val)
2565                 return ret_val;
2566         reg_data |= 0x3F;
2567         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2568         if (ret_val)
2569                 return ret_val;
2570
2571         switch (hw->phy.type) {
2572         case e1000_phy_igp_3:
2573                 ret_val = e1000e_copper_link_setup_igp(hw);
2574                 if (ret_val)
2575                         return ret_val;
2576                 break;
2577         case e1000_phy_bm:
2578         case e1000_phy_82578:
2579                 ret_val = e1000e_copper_link_setup_m88(hw);
2580                 if (ret_val)
2581                         return ret_val;
2582                 break;
2583         case e1000_phy_82577:
2584                 ret_val = e1000_copper_link_setup_82577(hw);
2585                 if (ret_val)
2586                         return ret_val;
2587                 break;
2588         case e1000_phy_ife:
2589                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2590                                                &reg_data);
2591                 if (ret_val)
2592                         return ret_val;
2593
2594                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2595
2596                 switch (hw->phy.mdix) {
2597                 case 1:
2598                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2599                         break;
2600                 case 2:
2601                         reg_data |= IFE_PMC_FORCE_MDIX;
2602                         break;
2603                 case 0:
2604                 default:
2605                         reg_data |= IFE_PMC_AUTO_MDIX;
2606                         break;
2607                 }
2608                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2609                                                 reg_data);
2610                 if (ret_val)
2611                         return ret_val;
2612                 break;
2613         default:
2614                 break;
2615         }
2616         return e1000e_setup_copper_link(hw);
2617 }
2618
2619 /**
2620  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2621  *  @hw: pointer to the HW structure
2622  *  @speed: pointer to store current link speed
2623  *  @duplex: pointer to store the current link duplex
2624  *
2625  *  Calls the generic get_speed_and_duplex to retrieve the current link
2626  *  information and then calls the Kumeran lock loss workaround for links at
2627  *  gigabit speeds.
2628  **/
2629 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2630                                           u16 *duplex)
2631 {
2632         s32 ret_val;
2633
2634         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2635         if (ret_val)
2636                 return ret_val;
2637
2638         if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2639                 ret_val = e1000e_write_kmrn_reg(hw,
2640                                                   E1000_KMRNCTRLSTA_K1_CONFIG,
2641                                                   E1000_KMRNCTRLSTA_K1_DISABLE);
2642                 if (ret_val)
2643                         return ret_val;
2644         }
2645
2646         if ((hw->mac.type == e1000_ich8lan) &&
2647             (hw->phy.type == e1000_phy_igp_3) &&
2648             (*speed == SPEED_1000)) {
2649                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2650         }
2651
2652         return ret_val;
2653 }
2654
2655 /**
2656  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2657  *  @hw: pointer to the HW structure
2658  *
2659  *  Work-around for 82566 Kumeran PCS lock loss:
2660  *  On link status change (i.e. PCI reset, speed change) and link is up and
2661  *  speed is gigabit-
2662  *    0) if workaround is optionally disabled do nothing
2663  *    1) wait 1ms for Kumeran link to come up
2664  *    2) check Kumeran Diagnostic register PCS lock loss bit
2665  *    3) if not set the link is locked (all is good), otherwise...
2666  *    4) reset the PHY
2667  *    5) repeat up to 10 times
2668  *  Note: this is only called for IGP3 copper when speed is 1gb.
2669  **/
2670 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2671 {
2672         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2673         u32 phy_ctrl;
2674         s32 ret_val;
2675         u16 i, data;
2676         bool link;
2677
2678         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2679                 return 0;
2680
2681         /*
2682          * Make sure link is up before proceeding.  If not just return.
2683          * Attempting this while link is negotiating fouled up link
2684          * stability
2685          */
2686         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2687         if (!link)
2688                 return 0;
2689
2690         for (i = 0; i < 10; i++) {
2691                 /* read once to clear */
2692                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2693                 if (ret_val)
2694                         return ret_val;
2695                 /* and again to get new status */
2696                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2697                 if (ret_val)
2698                         return ret_val;
2699
2700                 /* check for PCS lock */
2701                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2702                         return 0;
2703
2704                 /* Issue PHY reset */
2705                 e1000_phy_hw_reset(hw);
2706                 mdelay(5);
2707         }
2708         /* Disable GigE link negotiation */
2709         phy_ctrl = er32(PHY_CTRL);
2710         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2711                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2712         ew32(PHY_CTRL, phy_ctrl);
2713
2714         /*
2715          * Call gig speed drop workaround on Gig disable before accessing
2716          * any PHY registers
2717          */
2718         e1000e_gig_downshift_workaround_ich8lan(hw);
2719
2720         /* unable to acquire PCS lock */
2721         return -E1000_ERR_PHY;
2722 }
2723
2724 /**
2725  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2726  *  @hw: pointer to the HW structure
2727  *  @state: boolean value used to set the current Kumeran workaround state
2728  *
2729  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2730  *  /disabled - FALSE).
2731  **/
2732 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2733                                                  bool state)
2734 {
2735         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2736
2737         if (hw->mac.type != e1000_ich8lan) {
2738                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2739                 return;
2740         }
2741
2742         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2743 }
2744
2745 /**
2746  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2747  *  @hw: pointer to the HW structure
2748  *
2749  *  Workaround for 82566 power-down on D3 entry:
2750  *    1) disable gigabit link
2751  *    2) write VR power-down enable
2752  *    3) read it back
2753  *  Continue if successful, else issue LCD reset and repeat
2754  **/
2755 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2756 {
2757         u32 reg;
2758         u16 data;
2759         u8  retry = 0;
2760
2761         if (hw->phy.type != e1000_phy_igp_3)
2762                 return;
2763
2764         /* Try the workaround twice (if needed) */
2765         do {
2766                 /* Disable link */
2767                 reg = er32(PHY_CTRL);
2768                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2769                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2770                 ew32(PHY_CTRL, reg);
2771
2772                 /*
2773                  * Call gig speed drop workaround on Gig disable before
2774                  * accessing any PHY registers
2775                  */
2776                 if (hw->mac.type == e1000_ich8lan)
2777                         e1000e_gig_downshift_workaround_ich8lan(hw);
2778
2779                 /* Write VR power-down enable */
2780                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2781                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2782                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2783
2784                 /* Read it back and test */
2785                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2786                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2787                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2788                         break;
2789
2790                 /* Issue PHY reset and repeat at most one more time */
2791                 reg = er32(CTRL);
2792                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2793                 retry++;
2794         } while (retry);
2795 }
2796
2797 /**
2798  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2799  *  @hw: pointer to the HW structure
2800  *
2801  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2802  *  LPLU, Gig disable, MDIC PHY reset):
2803  *    1) Set Kumeran Near-end loopback
2804  *    2) Clear Kumeran Near-end loopback
2805  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2806  **/
2807 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2808 {
2809         s32 ret_val;
2810         u16 reg_data;
2811
2812         if ((hw->mac.type != e1000_ich8lan) ||
2813             (hw->phy.type != e1000_phy_igp_3))
2814                 return;
2815
2816         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2817                                       &reg_data);
2818         if (ret_val)
2819                 return;
2820         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2821         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2822                                        reg_data);
2823         if (ret_val)
2824                 return;
2825         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2826         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2827                                        reg_data);
2828 }
2829
2830 /**
2831  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2832  *  @hw: pointer to the HW structure
2833  *
2834  *  During S0 to Sx transition, it is possible the link remains at gig
2835  *  instead of negotiating to a lower speed.  Before going to Sx, set
2836  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2837  *  to a lower speed.
2838  *
2839  *  Should only be called for applicable parts.
2840  **/
2841 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2842 {
2843         u32 phy_ctrl;
2844
2845         switch (hw->mac.type) {
2846         case e1000_ich9lan:
2847         case e1000_ich10lan:
2848         case e1000_pchlan:
2849                 phy_ctrl = er32(PHY_CTRL);
2850                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2851                             E1000_PHY_CTRL_GBE_DISABLE;
2852                 ew32(PHY_CTRL, phy_ctrl);
2853
2854                 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2855                 if (hw->mac.type == e1000_pchlan)
2856                         udelay(500);
2857         default:
2858                 break;
2859         }
2860
2861         return;
2862 }
2863
2864 /**
2865  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2866  *  @hw: pointer to the HW structure
2867  *
2868  *  Return the LED back to the default configuration.
2869  **/
2870 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2871 {
2872         if (hw->phy.type == e1000_phy_ife)
2873                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2874
2875         ew32(LEDCTL, hw->mac.ledctl_default);
2876         return 0;
2877 }
2878
2879 /**
2880  *  e1000_led_on_ich8lan - Turn LEDs on
2881  *  @hw: pointer to the HW structure
2882  *
2883  *  Turn on the LEDs.
2884  **/
2885 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2886 {
2887         if (hw->phy.type == e1000_phy_ife)
2888                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2889                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2890
2891         ew32(LEDCTL, hw->mac.ledctl_mode2);
2892         return 0;
2893 }
2894
2895 /**
2896  *  e1000_led_off_ich8lan - Turn LEDs off
2897  *  @hw: pointer to the HW structure
2898  *
2899  *  Turn off the LEDs.
2900  **/
2901 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2902 {
2903         if (hw->phy.type == e1000_phy_ife)
2904                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2905                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2906
2907         ew32(LEDCTL, hw->mac.ledctl_mode1);
2908         return 0;
2909 }
2910
2911 /**
2912  *  e1000_setup_led_pchlan - Configures SW controllable LED
2913  *  @hw: pointer to the HW structure
2914  *
2915  *  This prepares the SW controllable LED for use.
2916  **/
2917 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2918 {
2919         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2920                                         (u16)hw->mac.ledctl_mode1);
2921 }
2922
2923 /**
2924  *  e1000_cleanup_led_pchlan - Restore the default LED operation
2925  *  @hw: pointer to the HW structure
2926  *
2927  *  Return the LED back to the default configuration.
2928  **/
2929 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2930 {
2931         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2932                                         (u16)hw->mac.ledctl_default);
2933 }
2934
2935 /**
2936  *  e1000_led_on_pchlan - Turn LEDs on
2937  *  @hw: pointer to the HW structure
2938  *
2939  *  Turn on the LEDs.
2940  **/
2941 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2942 {
2943         u16 data = (u16)hw->mac.ledctl_mode2;
2944         u32 i, led;
2945
2946         /*
2947          * If no link, then turn LED on by setting the invert bit
2948          * for each LED that's mode is "link_up" in ledctl_mode2.
2949          */
2950         if (!(er32(STATUS) & E1000_STATUS_LU)) {
2951                 for (i = 0; i < 3; i++) {
2952                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2953                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2954                             E1000_LEDCTL_MODE_LINK_UP)
2955                                 continue;
2956                         if (led & E1000_PHY_LED0_IVRT)
2957                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2958                         else
2959                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2960                 }
2961         }
2962
2963         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2964 }
2965
2966 /**
2967  *  e1000_led_off_pchlan - Turn LEDs off
2968  *  @hw: pointer to the HW structure
2969  *
2970  *  Turn off the LEDs.
2971  **/
2972 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2973 {
2974         u16 data = (u16)hw->mac.ledctl_mode1;
2975         u32 i, led;
2976
2977         /*
2978          * If no link, then turn LED off by clearing the invert bit
2979          * for each LED that's mode is "link_up" in ledctl_mode1.
2980          */
2981         if (!(er32(STATUS) & E1000_STATUS_LU)) {
2982                 for (i = 0; i < 3; i++) {
2983                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2984                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2985                             E1000_LEDCTL_MODE_LINK_UP)
2986                                 continue;
2987                         if (led & E1000_PHY_LED0_IVRT)
2988                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2989                         else
2990                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2991                 }
2992         }
2993
2994         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2995 }
2996
2997 /**
2998  *  e1000_get_cfg_done_ich8lan - Read config done bit
2999  *  @hw: pointer to the HW structure
3000  *
3001  *  Read the management control register for the config done bit for
3002  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3003  *  to read the config done bit, so an error is *ONLY* logged and returns
3004  *  0.  If we were to return with error, EEPROM-less silicon
3005  *  would not be able to be reset or change link.
3006  **/
3007 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3008 {
3009         u32 bank = 0;
3010
3011         if (hw->mac.type >= e1000_pchlan) {
3012                 u32 status = er32(STATUS);
3013
3014                 if (status & E1000_STATUS_PHYRA)
3015                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3016                 else
3017                         hw_dbg(hw,
3018                                "PHY Reset Asserted not set - needs delay\n");
3019         }
3020
3021         e1000e_get_cfg_done(hw);
3022
3023         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3024         if ((hw->mac.type != e1000_ich10lan) &&
3025             (hw->mac.type != e1000_pchlan)) {
3026                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3027                     (hw->phy.type == e1000_phy_igp_3)) {
3028                         e1000e_phy_init_script_igp3(hw);
3029                 }
3030         } else {
3031                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3032                         /* Maybe we should do a basic PHY config */
3033                         hw_dbg(hw, "EEPROM not present\n");
3034                         return -E1000_ERR_CONFIG;
3035                 }
3036         }
3037
3038         return 0;
3039 }
3040
3041 /**
3042  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3043  *  @hw: pointer to the HW structure
3044  *
3045  *  Clears hardware counters specific to the silicon family and calls
3046  *  clear_hw_cntrs_generic to clear all general purpose counters.
3047  **/
3048 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3049 {
3050         u32 temp;
3051         u16 phy_data;
3052
3053         e1000e_clear_hw_cntrs_base(hw);
3054
3055         temp = er32(ALGNERRC);
3056         temp = er32(RXERRC);
3057         temp = er32(TNCRS);
3058         temp = er32(CEXTERR);
3059         temp = er32(TSCTC);
3060         temp = er32(TSCTFC);
3061
3062         temp = er32(MGTPRC);
3063         temp = er32(MGTPDC);
3064         temp = er32(MGTPTC);
3065
3066         temp = er32(IAC);
3067         temp = er32(ICRXOC);
3068
3069         /* Clear PHY statistics registers */
3070         if ((hw->phy.type == e1000_phy_82578) ||
3071             (hw->phy.type == e1000_phy_82577)) {
3072                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3073                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3074                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3075                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3076                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3077                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3078                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3079                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3080                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3081                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3082                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3083                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3084                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3085                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3086         }
3087 }
3088
3089 static struct e1000_mac_operations ich8_mac_ops = {
3090         .id_led_init            = e1000e_id_led_init,
3091         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3092         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3093         /* cleanup_led dependent on mac type */
3094         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3095         .get_bus_info           = e1000_get_bus_info_ich8lan,
3096         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3097         /* led_on dependent on mac type */
3098         /* led_off dependent on mac type */
3099         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3100         .reset_hw               = e1000_reset_hw_ich8lan,
3101         .init_hw                = e1000_init_hw_ich8lan,
3102         .setup_link             = e1000_setup_link_ich8lan,
3103         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3104         /* id_led_init dependent on mac type */
3105 };
3106
3107 static struct e1000_phy_operations ich8_phy_ops = {
3108         .acquire_phy            = e1000_acquire_swflag_ich8lan,
3109         .check_reset_block      = e1000_check_reset_block_ich8lan,
3110         .commit_phy             = NULL,
3111         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3112         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3113         .get_cable_length       = e1000e_get_cable_length_igp_2,
3114         .get_phy_info           = e1000_get_phy_info_ich8lan,
3115         .read_phy_reg           = e1000e_read_phy_reg_igp,
3116         .release_phy            = e1000_release_swflag_ich8lan,
3117         .reset_phy              = e1000_phy_hw_reset_ich8lan,
3118         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3119         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3120         .write_phy_reg          = e1000e_write_phy_reg_igp,
3121 };
3122
3123 static struct e1000_nvm_operations ich8_nvm_ops = {
3124         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
3125         .read_nvm               = e1000_read_nvm_ich8lan,
3126         .release_nvm            = e1000_release_swflag_ich8lan,
3127         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
3128         .valid_led_default      = e1000_valid_led_default_ich8lan,
3129         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
3130         .write_nvm              = e1000_write_nvm_ich8lan,
3131 };
3132
3133 struct e1000_info e1000_ich8_info = {
3134         .mac                    = e1000_ich8lan,
3135         .flags                  = FLAG_HAS_WOL
3136                                   | FLAG_IS_ICH
3137                                   | FLAG_RX_CSUM_ENABLED
3138                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3139                                   | FLAG_HAS_AMT
3140                                   | FLAG_HAS_FLASH
3141                                   | FLAG_APME_IN_WUC,
3142         .pba                    = 8,
3143         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3144         .get_variants           = e1000_get_variants_ich8lan,
3145         .mac_ops                = &ich8_mac_ops,
3146         .phy_ops                = &ich8_phy_ops,
3147         .nvm_ops                = &ich8_nvm_ops,
3148 };
3149
3150 struct e1000_info e1000_ich9_info = {
3151         .mac                    = e1000_ich9lan,
3152         .flags                  = FLAG_HAS_JUMBO_FRAMES
3153                                   | FLAG_IS_ICH
3154                                   | FLAG_HAS_WOL
3155                                   | FLAG_RX_CSUM_ENABLED
3156                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3157                                   | FLAG_HAS_AMT
3158                                   | FLAG_HAS_ERT
3159                                   | FLAG_HAS_FLASH
3160                                   | FLAG_APME_IN_WUC,
3161         .pba                    = 10,
3162         .max_hw_frame_size      = DEFAULT_JUMBO,
3163         .get_variants           = e1000_get_variants_ich8lan,
3164         .mac_ops                = &ich8_mac_ops,
3165         .phy_ops                = &ich8_phy_ops,
3166         .nvm_ops                = &ich8_nvm_ops,
3167 };
3168
3169 struct e1000_info e1000_ich10_info = {
3170         .mac                    = e1000_ich10lan,
3171         .flags                  = FLAG_HAS_JUMBO_FRAMES
3172                                   | FLAG_IS_ICH
3173                                   | FLAG_HAS_WOL
3174                                   | FLAG_RX_CSUM_ENABLED
3175                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3176                                   | FLAG_HAS_AMT
3177                                   | FLAG_HAS_ERT
3178                                   | FLAG_HAS_FLASH
3179                                   | FLAG_APME_IN_WUC,
3180         .pba                    = 10,
3181         .max_hw_frame_size      = DEFAULT_JUMBO,
3182         .get_variants           = e1000_get_variants_ich8lan,
3183         .mac_ops                = &ich8_mac_ops,
3184         .phy_ops                = &ich8_phy_ops,
3185         .nvm_ops                = &ich8_nvm_ops,
3186 };
3187
3188 struct e1000_info e1000_pch_info = {
3189         .mac                    = e1000_pchlan,
3190         .flags                  = FLAG_IS_ICH
3191                                   | FLAG_HAS_WOL
3192                                   | FLAG_RX_CSUM_ENABLED
3193                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3194                                   | FLAG_HAS_AMT
3195                                   | FLAG_HAS_FLASH
3196                                   | FLAG_HAS_JUMBO_FRAMES
3197                                   | FLAG_APME_IN_WUC,
3198         .pba                    = 26,
3199         .max_hw_frame_size      = 4096,
3200         .get_variants           = e1000_get_variants_ich8lan,
3201         .mac_ops                = &ich8_mac_ops,
3202         .phy_ops                = &ich8_phy_ops,
3203         .nvm_ops                = &ich8_nvm_ops,
3204 };