ARM: OMAP: Use linux/delay.h not asm/delay.h
[linux-2.6] / arch / arm / plat-omap / mcbsp.c
1 /*
2  * linux/arch/arm/plat-omap/mcbsp.c
3  *
4  * Copyright (C) 2004 Nokia Corporation
5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6  *
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * Multichannel mode not supported.
13  */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/wait.h>
19 #include <linux/completion.h>
20 #include <linux/interrupt.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #include <asm/arch/dma.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/irqs.h>
31 #include <asm/arch/dsp_common.h>
32 #include <asm/arch/mcbsp.h>
33
34 #ifdef CONFIG_MCBSP_DEBUG
35 #define DBG(x...)       printk(x)
36 #else
37 #define DBG(x...)                       do { } while (0)
38 #endif
39
40 struct omap_mcbsp {
41         u32                          io_base;
42         u8                           id;
43         u8                           free;
44         omap_mcbsp_word_length       rx_word_length;
45         omap_mcbsp_word_length       tx_word_length;
46
47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
48         /* IRQ based TX/RX */
49         int                          rx_irq;
50         int                          tx_irq;
51
52         /* DMA stuff */
53         u8                           dma_rx_sync;
54         short                        dma_rx_lch;
55         u8                           dma_tx_sync;
56         short                        dma_tx_lch;
57
58         /* Completion queues */
59         struct completion            tx_irq_completion;
60         struct completion            rx_irq_completion;
61         struct completion            tx_dma_completion;
62         struct completion            rx_dma_completion;
63
64         spinlock_t                   lock;
65 };
66
67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
68 #ifdef CONFIG_ARCH_OMAP1
69 static struct clk *mcbsp_dsp_ck = 0;
70 static struct clk *mcbsp_api_ck = 0;
71 static struct clk *mcbsp_dspxor_ck = 0;
72 #endif
73 #ifdef CONFIG_ARCH_OMAP2
74 static struct clk *mcbsp1_ick = 0;
75 static struct clk *mcbsp1_fck = 0;
76 static struct clk *mcbsp2_ick = 0;
77 static struct clk *mcbsp2_fck = 0;
78 #endif
79
80 static void omap_mcbsp_dump_reg(u8 id)
81 {
82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
96         DBG("***********************\n");
97 }
98
99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
100 {
101         struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
102
103         DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
104
105         complete(&mcbsp_tx->tx_irq_completion);
106         return IRQ_HANDLED;
107 }
108
109 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
110 {
111         struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
112
113         DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
114
115         complete(&mcbsp_rx->rx_irq_completion);
116         return IRQ_HANDLED;
117 }
118
119 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
120 {
121         struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
122
123         DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
124
125         /* We can free the channels */
126         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
127         mcbsp_dma_tx->dma_tx_lch = -1;
128
129         complete(&mcbsp_dma_tx->tx_dma_completion);
130 }
131
132 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
133 {
134         struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
135
136         DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
137
138         /* We can free the channels */
139         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
140         mcbsp_dma_rx->dma_rx_lch = -1;
141
142         complete(&mcbsp_dma_rx->rx_dma_completion);
143 }
144
145
146 /*
147  * omap_mcbsp_config simply write a config to the
148  * appropriate McBSP.
149  * You either call this function or set the McBSP registers
150  * by yourself before calling omap_mcbsp_start().
151  */
152
153 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
154 {
155         u32 io_base = mcbsp[id].io_base;
156
157         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
158
159         /* We write the given config */
160         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
161         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
162         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
163         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
164         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
165         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
166         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
167         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
168         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
169         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
170         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
171 }
172
173
174
175 static int omap_mcbsp_check(unsigned int id)
176 {
177         if (cpu_is_omap730()) {
178                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
179                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
180                        return -1;
181                 }
182                 return 0;
183         }
184
185         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
186                 if (id > OMAP_MAX_MCBSP_COUNT) {
187                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
188                         return -1;
189                 }
190                 return 0;
191         }
192
193         return -1;
194 }
195
196 #ifdef CONFIG_ARCH_OMAP1
197 static void omap_mcbsp_dsp_request(void)
198 {
199         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
200                 clk_enable(mcbsp_dsp_ck);
201                 clk_enable(mcbsp_api_ck);
202
203                 /* enable 12MHz clock to mcbsp 1 & 3 */
204                 clk_enable(mcbsp_dspxor_ck);
205
206                 /*
207                  * DSP external peripheral reset
208                  * FIXME: This should be moved to dsp code
209                  */
210                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
211                              DSP_RSTCT2);
212         }
213 }
214
215 static void omap_mcbsp_dsp_free(void)
216 {
217         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
218                 clk_disable(mcbsp_dspxor_ck);
219                 clk_disable(mcbsp_dsp_ck);
220                 clk_disable(mcbsp_api_ck);
221         }
222 }
223 #endif
224
225 #ifdef CONFIG_ARCH_OMAP2
226 static void omap2_mcbsp2_mux_setup(void)
227 {
228         omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
229         omap_cfg_reg(R14_24XX_MCBSP2_FSX);
230         omap_cfg_reg(W15_24XX_MCBSP2_DR);
231         omap_cfg_reg(V15_24XX_MCBSP2_DX);
232         omap_cfg_reg(V14_24XX_GPIO117);
233 }
234 #endif
235
236 /*
237  * We can choose between IRQ based or polled IO.
238  * This needs to be called before omap_mcbsp_request().
239  */
240 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
241 {
242         if (omap_mcbsp_check(id) < 0)
243                 return -EINVAL;
244
245         spin_lock(&mcbsp[id].lock);
246
247         if (!mcbsp[id].free) {
248                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
249                 spin_unlock(&mcbsp[id].lock);
250                 return -EINVAL;
251         }
252
253         mcbsp[id].io_type = io_type;
254
255         spin_unlock(&mcbsp[id].lock);
256
257         return 0;
258 }
259
260 int omap_mcbsp_request(unsigned int id)
261 {
262         int err;
263
264         if (omap_mcbsp_check(id) < 0)
265                 return -EINVAL;
266
267 #ifdef CONFIG_ARCH_OMAP1
268         /*
269          * On 1510, 1610 and 1710, McBSP1 and McBSP3
270          * are DSP public peripherals.
271          */
272         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
273                 omap_mcbsp_dsp_request();
274 #endif
275
276 #ifdef CONFIG_ARCH_OMAP2
277         if (cpu_is_omap24xx()) {
278                 if (id == OMAP_MCBSP1) {
279                         clk_enable(mcbsp1_ick);
280                         clk_enable(mcbsp1_fck);
281                 } else {
282                         clk_enable(mcbsp2_ick);
283                         clk_enable(mcbsp2_fck);
284                 }
285         }
286 #endif
287
288         spin_lock(&mcbsp[id].lock);
289         if (!mcbsp[id].free) {
290                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
291                 spin_unlock(&mcbsp[id].lock);
292                 return -1;
293         }
294
295         mcbsp[id].free = 0;
296         spin_unlock(&mcbsp[id].lock);
297
298         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
299                 /* We need to get IRQs here */
300                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
301                                   "McBSP",
302                                   (void *) (&mcbsp[id]));
303                 if (err != 0) {
304                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
305                                mcbsp[id].tx_irq, mcbsp[id].id);
306                         return err;
307                 }
308
309                 init_completion(&(mcbsp[id].tx_irq_completion));
310
311
312                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
313                                   "McBSP",
314                                   (void *) (&mcbsp[id]));
315                 if (err != 0) {
316                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
317                                mcbsp[id].rx_irq, mcbsp[id].id);
318                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
319                         return err;
320                 }
321
322                 init_completion(&(mcbsp[id].rx_irq_completion));
323         }
324
325         return 0;
326
327 }
328
329 void omap_mcbsp_free(unsigned int id)
330 {
331         if (omap_mcbsp_check(id) < 0)
332                 return;
333
334 #ifdef CONFIG_ARCH_OMAP1
335         if (cpu_class_is_omap1()) {
336                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
337                         omap_mcbsp_dsp_free();
338         }
339 #endif
340
341 #ifdef CONFIG_ARCH_OMAP2
342         if (cpu_is_omap24xx()) {
343                 if (id == OMAP_MCBSP1) {
344                         clk_disable(mcbsp1_ick);
345                         clk_disable(mcbsp1_fck);
346                 } else {
347                         clk_disable(mcbsp2_ick);
348                         clk_disable(mcbsp2_fck);
349                 }
350         }
351 #endif
352
353         spin_lock(&mcbsp[id].lock);
354         if (mcbsp[id].free) {
355                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
356                 spin_unlock(&mcbsp[id].lock);
357                 return;
358         }
359
360         mcbsp[id].free = 1;
361         spin_unlock(&mcbsp[id].lock);
362
363         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
364                 /* Free IRQs */
365                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
366                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
367         }
368 }
369
370 /*
371  * Here we start the McBSP, by enabling the sample
372  * generator, both transmitter and receivers,
373  * and the frame sync.
374  */
375 void omap_mcbsp_start(unsigned int id)
376 {
377         u32 io_base;
378         u16 w;
379
380         if (omap_mcbsp_check(id) < 0)
381                 return;
382
383         io_base = mcbsp[id].io_base;
384
385         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
386         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
387
388         /* Start the sample generator */
389         w = OMAP_MCBSP_READ(io_base, SPCR2);
390         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
391
392         /* Enable transmitter and receiver */
393         w = OMAP_MCBSP_READ(io_base, SPCR2);
394         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
395
396         w = OMAP_MCBSP_READ(io_base, SPCR1);
397         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
398
399         udelay(100);
400
401         /* Start frame sync */
402         w = OMAP_MCBSP_READ(io_base, SPCR2);
403         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
404
405         /* Dump McBSP Regs */
406         omap_mcbsp_dump_reg(id);
407
408 }
409
410 void omap_mcbsp_stop(unsigned int id)
411 {
412         u32 io_base;
413         u16 w;
414
415         if (omap_mcbsp_check(id) < 0)
416                 return;
417
418         io_base = mcbsp[id].io_base;
419
420         /* Reset transmitter */
421         w = OMAP_MCBSP_READ(io_base, SPCR2);
422         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
423
424         /* Reset receiver */
425         w = OMAP_MCBSP_READ(io_base, SPCR1);
426         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
427
428         /* Reset the sample rate generator */
429         w = OMAP_MCBSP_READ(io_base, SPCR2);
430         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
431 }
432
433
434 /* polled mcbsp i/o operations */
435 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
436 {
437         u32 base = mcbsp[id].io_base;
438         writew(buf, base + OMAP_MCBSP_REG_DXR1);
439         /* if frame sync error - clear the error */
440         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
441                 /* clear error */
442                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
443                        base + OMAP_MCBSP_REG_SPCR2);
444                 /* resend */
445                 return -1;
446         } else {
447                 /* wait for transmit confirmation */
448                 int attemps = 0;
449                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
450                         if (attemps++ > 1000) {
451                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
452                                        (~XRST),
453                                        base + OMAP_MCBSP_REG_SPCR2);
454                                 udelay(10);
455                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
456                                        (XRST),
457                                        base + OMAP_MCBSP_REG_SPCR2);
458                                 udelay(10);
459                                 printk(KERN_ERR
460                                        " Could not write to McBSP Register\n");
461                                 return -2;
462                         }
463                 }
464         }
465         return 0;
466 }
467
468 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
469 {
470         u32 base = mcbsp[id].io_base;
471         /* if frame sync error - clear the error */
472         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
473                 /* clear error */
474                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
475                        base + OMAP_MCBSP_REG_SPCR1);
476                 /* resend */
477                 return -1;
478         } else {
479                 /* wait for recieve confirmation */
480                 int attemps = 0;
481                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
482                         if (attemps++ > 1000) {
483                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
484                                        (~RRST),
485                                        base + OMAP_MCBSP_REG_SPCR1);
486                                 udelay(10);
487                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
488                                        (RRST),
489                                        base + OMAP_MCBSP_REG_SPCR1);
490                                 udelay(10);
491                                 printk(KERN_ERR
492                                        " Could not read from McBSP Register\n");
493                                 return -2;
494                         }
495                 }
496         }
497         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
498         return 0;
499 }
500
501 /*
502  * IRQ based word transmission.
503  */
504 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
505 {
506         u32 io_base;
507         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
508
509         if (omap_mcbsp_check(id) < 0)
510                 return;
511
512         io_base = mcbsp[id].io_base;
513
514         wait_for_completion(&(mcbsp[id].tx_irq_completion));
515
516         if (word_length > OMAP_MCBSP_WORD_16)
517                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
518         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
519 }
520
521 u32 omap_mcbsp_recv_word(unsigned int id)
522 {
523         u32 io_base;
524         u16 word_lsb, word_msb = 0;
525         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
526
527         if (omap_mcbsp_check(id) < 0)
528                 return -EINVAL;
529
530         io_base = mcbsp[id].io_base;
531
532         wait_for_completion(&(mcbsp[id].rx_irq_completion));
533
534         if (word_length > OMAP_MCBSP_WORD_16)
535                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
536         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
537
538         return (word_lsb | (word_msb << 16));
539 }
540
541
542 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
543 {
544         u32 io_base = mcbsp[id].io_base;
545         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
546         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
547         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
548
549         if (tx_word_length != rx_word_length)
550                 return -EINVAL;
551
552         /* First we wait for the transmitter to be ready */
553         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
554         while (!(spcr2 & XRDY)) {
555                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
556                 if (attempts++ > 1000) {
557                         /* We must reset the transmitter */
558                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
559                         udelay(10);
560                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
561                         udelay(10);
562                         printk("McBSP transmitter not ready\n");
563                         return -EAGAIN;
564                 }
565         }
566
567         /* Now we can push the data */
568         if (tx_word_length > OMAP_MCBSP_WORD_16)
569                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
570         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
571
572         /* We wait for the receiver to be ready */
573         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
574         while (!(spcr1 & RRDY)) {
575                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
576                 if (attempts++ > 1000) {
577                         /* We must reset the receiver */
578                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
579                         udelay(10);
580                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
581                         udelay(10);
582                         printk("McBSP receiver not ready\n");
583                         return -EAGAIN;
584                 }
585         }
586
587         /* Receiver is ready, let's read the dummy data */
588         if (rx_word_length > OMAP_MCBSP_WORD_16)
589                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
590         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
591
592         return 0;
593 }
594
595 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
596 {
597         u32 io_base = mcbsp[id].io_base, clock_word = 0;
598         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
599         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
600         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
601
602         if (tx_word_length != rx_word_length)
603                 return -EINVAL;
604
605         /* First we wait for the transmitter to be ready */
606         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
607         while (!(spcr2 & XRDY)) {
608                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
609                 if (attempts++ > 1000) {
610                         /* We must reset the transmitter */
611                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
612                         udelay(10);
613                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
614                         udelay(10);
615                         printk("McBSP transmitter not ready\n");
616                         return -EAGAIN;
617                 }
618         }
619
620         /* We first need to enable the bus clock */
621         if (tx_word_length > OMAP_MCBSP_WORD_16)
622                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
623         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
624
625         /* We wait for the receiver to be ready */
626         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
627         while (!(spcr1 & RRDY)) {
628                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
629                 if (attempts++ > 1000) {
630                         /* We must reset the receiver */
631                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
632                         udelay(10);
633                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
634                         udelay(10);
635                         printk("McBSP receiver not ready\n");
636                         return -EAGAIN;
637                 }
638         }
639
640         /* Receiver is ready, there is something for us */
641         if (rx_word_length > OMAP_MCBSP_WORD_16)
642                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
643         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
644
645         word[0] = (word_lsb | (word_msb << 16));
646
647         return 0;
648 }
649
650
651 /*
652  * Simple DMA based buffer rx/tx routines.
653  * Nothing fancy, just a single buffer tx/rx through DMA.
654  * The DMA resources are released once the transfer is done.
655  * For anything fancier, you should use your own customized DMA
656  * routines and callbacks.
657  */
658 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
659 {
660         int dma_tx_ch;
661         int src_port = 0;
662         int dest_port = 0;
663         int sync_dev = 0;
664
665         if (omap_mcbsp_check(id) < 0)
666                 return -EINVAL;
667
668         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
669                              &mcbsp[id],
670                              &dma_tx_ch)) {
671                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
672                 return -EAGAIN;
673         }
674         mcbsp[id].dma_tx_lch = dma_tx_ch;
675
676         DBG("TX DMA on channel %d\n", dma_tx_ch);
677
678         init_completion(&(mcbsp[id].tx_dma_completion));
679
680         if (cpu_class_is_omap1()) {
681                 src_port = OMAP_DMA_PORT_TIPB;
682                 dest_port = OMAP_DMA_PORT_EMIFF;
683         }
684         if (cpu_is_omap24xx())
685                 sync_dev = mcbsp[id].dma_tx_sync;
686
687         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
688                                      OMAP_DMA_DATA_TYPE_S16,
689                                      length >> 1, 1,
690                                      OMAP_DMA_SYNC_ELEMENT,
691          sync_dev, 0);
692
693         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
694                                  src_port,
695                                  OMAP_DMA_AMODE_CONSTANT,
696                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
697                                  0, 0);
698
699         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
700                                 dest_port,
701                                 OMAP_DMA_AMODE_POST_INC,
702                                 buffer,
703                                 0, 0);
704
705         omap_start_dma(mcbsp[id].dma_tx_lch);
706         wait_for_completion(&(mcbsp[id].tx_dma_completion));
707         return 0;
708 }
709
710
711 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
712 {
713         int dma_rx_ch;
714         int src_port = 0;
715         int dest_port = 0;
716         int sync_dev = 0;
717
718         if (omap_mcbsp_check(id) < 0)
719                 return -EINVAL;
720
721         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
722                              &mcbsp[id],
723                              &dma_rx_ch)) {
724                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
725                 return -EAGAIN;
726         }
727         mcbsp[id].dma_rx_lch = dma_rx_ch;
728
729         DBG("RX DMA on channel %d\n", dma_rx_ch);
730
731         init_completion(&(mcbsp[id].rx_dma_completion));
732
733         if (cpu_class_is_omap1()) {
734                 src_port = OMAP_DMA_PORT_TIPB;
735                 dest_port = OMAP_DMA_PORT_EMIFF;
736         }
737         if (cpu_is_omap24xx())
738                 sync_dev = mcbsp[id].dma_rx_sync;
739
740         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
741                                      OMAP_DMA_DATA_TYPE_S16,
742                                      length >> 1, 1,
743                                      OMAP_DMA_SYNC_ELEMENT,
744          sync_dev, 0);
745
746         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
747                                 src_port,
748                                 OMAP_DMA_AMODE_CONSTANT,
749                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
750                                 0, 0);
751
752         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
753                                  dest_port,
754                                  OMAP_DMA_AMODE_POST_INC,
755                                  buffer,
756                                  0, 0);
757
758         omap_start_dma(mcbsp[id].dma_rx_lch);
759         wait_for_completion(&(mcbsp[id].rx_dma_completion));
760         return 0;
761 }
762
763
764 /*
765  * SPI wrapper.
766  * Since SPI setup is much simpler than the generic McBSP one,
767  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
768  * Once this is done, you can call omap_mcbsp_start().
769  */
770 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
771 {
772         struct omap_mcbsp_reg_cfg mcbsp_cfg;
773
774         if (omap_mcbsp_check(id) < 0)
775                 return;
776
777         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
778
779         /* SPI has only one frame */
780         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
781         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
782
783         /* Clock stop mode */
784         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
785                 mcbsp_cfg.spcr1 |= (1 << 12);
786         else
787                 mcbsp_cfg.spcr1 |= (3 << 11);
788
789         /* Set clock parities */
790         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
791                 mcbsp_cfg.pcr0 |= CLKRP;
792         else
793                 mcbsp_cfg.pcr0 &= ~CLKRP;
794
795         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
796                 mcbsp_cfg.pcr0 &= ~CLKXP;
797         else
798                 mcbsp_cfg.pcr0 |= CLKXP;
799
800         /* Set SCLKME to 0 and CLKSM to 1 */
801         mcbsp_cfg.pcr0 &= ~SCLKME;
802         mcbsp_cfg.srgr2 |= CLKSM;
803
804         /* Set FSXP */
805         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
806                 mcbsp_cfg.pcr0 &= ~FSXP;
807         else
808                 mcbsp_cfg.pcr0 |= FSXP;
809
810         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
811                 mcbsp_cfg.pcr0 |= CLKXM;
812                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
813                 mcbsp_cfg.pcr0 |= FSXM;
814                 mcbsp_cfg.srgr2 &= ~FSGM;
815                 mcbsp_cfg.xcr2 |= XDATDLY(1);
816                 mcbsp_cfg.rcr2 |= RDATDLY(1);
817         }
818         else {
819                 mcbsp_cfg.pcr0 &= ~CLKXM;
820                 mcbsp_cfg.srgr1 |= CLKGDV(1);
821                 mcbsp_cfg.pcr0 &= ~FSXM;
822                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
823                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
824         }
825
826         mcbsp_cfg.xcr2 &= ~XPHASE;
827         mcbsp_cfg.rcr2 &= ~RPHASE;
828
829         omap_mcbsp_config(id, &mcbsp_cfg);
830 }
831
832
833 /*
834  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
835  * 730 has only 2 McBSP, and both of them are MPU peripherals.
836  */
837 struct omap_mcbsp_info {
838         u32 virt_base;
839         u8 dma_rx_sync, dma_tx_sync;
840         u16 rx_irq, tx_irq;
841 };
842
843 #ifdef CONFIG_ARCH_OMAP730
844 static const struct omap_mcbsp_info mcbsp_730[] = {
845         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
846                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
847                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
848                 .rx_irq = INT_730_McBSP1RX,
849                 .tx_irq = INT_730_McBSP1TX },
850         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
851                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
852                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
853                 .rx_irq = INT_730_McBSP2RX,
854                 .tx_irq = INT_730_McBSP2TX },
855 };
856 #endif
857
858 #ifdef CONFIG_ARCH_OMAP15XX
859 static const struct omap_mcbsp_info mcbsp_1510[] = {
860         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
861                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
862                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
863                 .rx_irq = INT_McBSP1RX,
864                 .tx_irq = INT_McBSP1TX },
865         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
866                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
867                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
868                 .rx_irq = INT_1510_SPI_RX,
869                 .tx_irq = INT_1510_SPI_TX },
870         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
871                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
872                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
873                 .rx_irq = INT_McBSP3RX,
874                 .tx_irq = INT_McBSP3TX },
875 };
876 #endif
877
878 #if defined(CONFIG_ARCH_OMAP16XX)
879 static const struct omap_mcbsp_info mcbsp_1610[] = {
880         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
881                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
882                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
883                 .rx_irq = INT_McBSP1RX,
884                 .tx_irq = INT_McBSP1TX },
885         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
886                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
887                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
888                 .rx_irq = INT_1610_McBSP2_RX,
889                 .tx_irq = INT_1610_McBSP2_TX },
890         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
891                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
892                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
893                 .rx_irq = INT_McBSP3RX,
894                 .tx_irq = INT_McBSP3TX },
895 };
896 #endif
897
898 #if defined(CONFIG_ARCH_OMAP24XX)
899 static const struct omap_mcbsp_info mcbsp_24xx[] = {
900         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
901                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
902                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
903                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
904                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
905                 },
906         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
907                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
908                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
909                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
910                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
911                 },
912 };
913 #endif
914
915 static int __init omap_mcbsp_init(void)
916 {
917         int mcbsp_count = 0, i;
918         static const struct omap_mcbsp_info *mcbsp_info;
919
920         printk("Initializing OMAP McBSP system\n");
921
922 #ifdef CONFIG_ARCH_OMAP1
923         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
924         if (IS_ERR(mcbsp_dsp_ck)) {
925                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
926                 return PTR_ERR(mcbsp_dsp_ck);
927         }
928         mcbsp_api_ck = clk_get(0, "api_ck");
929         if (IS_ERR(mcbsp_api_ck)) {
930                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
931                 return PTR_ERR(mcbsp_api_ck);
932         }
933         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
934         if (IS_ERR(mcbsp_dspxor_ck)) {
935                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
936                 return PTR_ERR(mcbsp_dspxor_ck);
937         }
938 #endif
939 #ifdef CONFIG_ARCH_OMAP2
940         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
941         if (IS_ERR(mcbsp1_ick)) {
942                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
943                 return PTR_ERR(mcbsp1_ick);
944         }
945         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
946         if (IS_ERR(mcbsp1_fck)) {
947                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
948                 return PTR_ERR(mcbsp1_fck);
949         }
950         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
951         if (IS_ERR(mcbsp2_ick)) {
952                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
953                 return PTR_ERR(mcbsp2_ick);
954         }
955         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
956         if (IS_ERR(mcbsp2_fck)) {
957                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
958                 return PTR_ERR(mcbsp2_fck);
959         }
960 #endif
961
962 #ifdef CONFIG_ARCH_OMAP730
963         if (cpu_is_omap730()) {
964                 mcbsp_info = mcbsp_730;
965                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
966         }
967 #endif
968 #ifdef CONFIG_ARCH_OMAP15XX
969         if (cpu_is_omap15xx()) {
970                 mcbsp_info = mcbsp_1510;
971                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
972         }
973 #endif
974 #if defined(CONFIG_ARCH_OMAP16XX)
975         if (cpu_is_omap16xx()) {
976                 mcbsp_info = mcbsp_1610;
977                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
978         }
979 #endif
980 #if defined(CONFIG_ARCH_OMAP24XX)
981         if (cpu_is_omap24xx()) {
982                 mcbsp_info = mcbsp_24xx;
983                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
984                 omap2_mcbsp2_mux_setup();
985         }
986 #endif
987         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
988                 if (i >= mcbsp_count) {
989                         mcbsp[i].io_base = 0;
990                         mcbsp[i].free = 0;
991                         continue;
992                 }
993                 mcbsp[i].id = i + 1;
994                 mcbsp[i].free = 1;
995                 mcbsp[i].dma_tx_lch = -1;
996                 mcbsp[i].dma_rx_lch = -1;
997
998                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
999                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1000                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1001                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1002                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1003                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1004                 spin_lock_init(&mcbsp[i].lock);
1005         }
1006
1007         return 0;
1008 }
1009
1010 arch_initcall(omap_mcbsp_init);
1011
1012 EXPORT_SYMBOL(omap_mcbsp_config);
1013 EXPORT_SYMBOL(omap_mcbsp_request);
1014 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1015 EXPORT_SYMBOL(omap_mcbsp_free);
1016 EXPORT_SYMBOL(omap_mcbsp_start);
1017 EXPORT_SYMBOL(omap_mcbsp_stop);
1018 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1019 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1020 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1021 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1022 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1023 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1024 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);