git.oblomov.eu Git - linux-2.6/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/stddef.h>
  18
  19 #include <asm/bugs.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         local_irq_disable();
  43         if (!need_resched())
  44                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  45         local_irq_enable();
  46 }
  47
  48 /*
  49  * There is a race when WAIT instruction executed with interrupt
  50  * enabled.
  51  * But it is implementation-dependent wheter the pipelie restarts when
  52  * a non-enabled interrupt is requested.
  53  */
  54 static void r4k_wait(void)
  55 {
  56         __asm__("       .set    mips3                   \n"
  57                 "       wait                            \n"
  58                 "       .set    mips0                   \n");
  59 }
  60
  61 /*
  62  * This variant is preferable as it allows testing need_resched and going to
  63  * sleep depending on the outcome atomically.  Unfortunately the "It is
  64  * implementation-dependent whether the pipeline restarts when a non-enabled
  65  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  66  * using this version a gamble.
  67  */
  68 static void r4k_wait_irqoff(void)
  69 {
  70         local_irq_disable();
  71         if (!need_resched())
  72                 __asm__("       .set    mips3           \n"
  73                         "       wait                    \n"
  74                         "       .set    mips0           \n");
  75         local_irq_enable();
  76 }
  77
  78 /* The Au1xxx wait is available only if using 32khz counter or
  79  * external timer source, but specifically not CP0 Counter. */
  80 int allow_au1k_wait;
  81
  82 static void au1k_wait(void)
  83 {
  84         /* using the wait instruction makes CP0 counter unusable */
  85         __asm__("       .set    mips3                   \n"
  86                 "       cache   0x14, 0(%0)             \n"
  87                 "       cache   0x14, 32(%0)            \n"
  88                 "       sync                            \n"
  89                 "       nop                             \n"
  90                 "       wait                            \n"
  91                 "       nop                             \n"
  92                 "       nop                             \n"
  93                 "       nop                             \n"
  94                 "       nop                             \n"
  95                 "       .set    mips0                   \n"
  96                 : : "r" (au1k_wait));
  97 }
  98
  99 static int __initdata nowait = 0;
 100
 101 static int __init wait_disable(char *s)
 102 {
 103         nowait = 1;
 104
 105         return 1;
 106 }
 107
 108 __setup("nowait", wait_disable);
 109
 110 static inline void check_wait(void)
 111 {
 112         struct cpuinfo_mips *c = &current_cpu_data;
 113
 114         if (nowait) {
 115                 printk("Wait instruction disabled.\n");
 116                 return;
 117         }
 118
 119         switch (c->cputype) {
 120         case CPU_R3081:
 121         case CPU_R3081E:
 122                 cpu_wait = r3081_wait;
 123                 break;
 124         case CPU_TX3927:
 125                 cpu_wait = r39xx_wait;
 126                 break;
 127         case CPU_R4200:
 128 /*      case CPU_R4300: */
 129         case CPU_R4600:
 130         case CPU_R4640:
 131         case CPU_R4650:
 132         case CPU_R4700:
 133         case CPU_R5000:
 134         case CPU_NEVADA:
 135         case CPU_RM7000:
 136         case CPU_4KC:
 137         case CPU_4KEC:
 138         case CPU_4KSC:
 139         case CPU_5KC:
 140 /*      case CPU_20KC:*/
 141         case CPU_24K:
 142         case CPU_25KF:
 143         case CPU_34K:
 144         case CPU_74K:
 145         case CPU_PR4450:
 146                 cpu_wait = r4k_wait;
 147                 break;
 148         case CPU_TX49XX:
 149                 cpu_wait = r4k_wait_irqoff;
 150                 break;
 151         case CPU_AU1000:
 152         case CPU_AU1100:
 153         case CPU_AU1500:
 154         case CPU_AU1550:
 155         case CPU_AU1200:
 156                 if (allow_au1k_wait)
 157                         cpu_wait = au1k_wait;
 158                 break;
 159         case CPU_RM9000:
 160                 if ((c->processor_id & 0x00ff) >= 0x40)
 161                         cpu_wait = r4k_wait;
 162                 break;
 163         default:
 164                 break;
 165         }
 166 }
 167
 168 void __init check_bugs32(void)
 169 {
 170         check_wait();
 171 }
 172
 173 /*
 174  * Probe whether cpu has config register by trying to play with
 175  * alternate cache bit and see whether it matters.
 176  * It's used by cpu_probe to distinguish between R3000A and R3081.
 177  */
 178 static inline int cpu_has_confreg(void)
 179 {
 180 #ifdef CONFIG_CPU_R3000
 181         extern unsigned long r3k_cache_size(unsigned long);
 182         unsigned long size1, size2;
 183         unsigned long cfg = read_c0_conf();
 184
 185         size1 = r3k_cache_size(ST0_ISC);
 186         write_c0_conf(cfg ^ R30XX_CONF_AC);
 187         size2 = r3k_cache_size(ST0_ISC);
 188         write_c0_conf(cfg);
 189         return size1 != size2;
 190 #else
 191         return 0;
 192 #endif
 193 }
 194
 195 /*
 196  * Get the FPU Implementation/Revision.
 197  */
 198 static inline unsigned long cpu_get_fpu_id(void)
 199 {
 200         unsigned long tmp, fpu_id;
 201
 202         tmp = read_c0_status();
 203         __enable_fpu();
 204         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 205         write_c0_status(tmp);
 206         return fpu_id;
 207 }
 208
 209 /*
 210  * Check the CPU has an FPU the official way.
 211  */
 212 static inline int __cpu_has_fpu(void)
 213 {
 214         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 215 }
 216
 217 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 218                 | MIPS_CPU_COUNTER)
 219
 220 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 221 {
 222         switch (c->processor_id & 0xff00) {
 223         case PRID_IMP_R2000:
 224                 c->cputype = CPU_R2000;
 225                 c->isa_level = MIPS_CPU_ISA_I;
 226                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 227                              MIPS_CPU_NOFPUEX;
 228                 if (__cpu_has_fpu())
 229                         c->options |= MIPS_CPU_FPU;
 230                 c->tlbsize = 64;
 231                 break;
 232         case PRID_IMP_R3000:
 233                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 234                         if (cpu_has_confreg())
 235                                 c->cputype = CPU_R3081E;
 236                         else
 237                                 c->cputype = CPU_R3000A;
 238                 else
 239                         c->cputype = CPU_R3000;
 240                 c->isa_level = MIPS_CPU_ISA_I;
 241                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 242                              MIPS_CPU_NOFPUEX;
 243                 if (__cpu_has_fpu())
 244                         c->options |= MIPS_CPU_FPU;
 245                 c->tlbsize = 64;
 246                 break;
 247         case PRID_IMP_R4000:
 248                 if (read_c0_config() & CONF_SC) {
 249                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 250                                 c->cputype = CPU_R4400PC;
 251                         else
 252                                 c->cputype = CPU_R4000PC;
 253                 } else {
 254                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 255                                 c->cputype = CPU_R4400SC;
 256                         else
 257                                 c->cputype = CPU_R4000SC;
 258                 }
 259
 260                 c->isa_level = MIPS_CPU_ISA_III;
 261                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 262                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 263                              MIPS_CPU_LLSC;
 264                 c->tlbsize = 48;
 265                 break;
 266         case PRID_IMP_VR41XX:
 267                 switch (c->processor_id & 0xf0) {
 268                 case PRID_REV_VR4111:
 269                         c->cputype = CPU_VR4111;
 270                         break;
 271                 case PRID_REV_VR4121:
 272                         c->cputype = CPU_VR4121;
 273                         break;
 274                 case PRID_REV_VR4122:
 275                         if ((c->processor_id & 0xf) < 0x3)
 276                                 c->cputype = CPU_VR4122;
 277                         else
 278                                 c->cputype = CPU_VR4181A;
 279                         break;
 280                 case PRID_REV_VR4130:
 281                         if ((c->processor_id & 0xf) < 0x4)
 282                                 c->cputype = CPU_VR4131;
 283                         else
 284                                 c->cputype = CPU_VR4133;
 285                         break;
 286                 default:
 287                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 288                         c->cputype = CPU_VR41XX;
 289                         break;
 290                 }
 291                 c->isa_level = MIPS_CPU_ISA_III;
 292                 c->options = R4K_OPTS;
 293                 c->tlbsize = 32;
 294                 break;
 295         case PRID_IMP_R4300:
 296                 c->cputype = CPU_R4300;
 297                 c->isa_level = MIPS_CPU_ISA_III;
 298                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 299                              MIPS_CPU_LLSC;
 300                 c->tlbsize = 32;
 301                 break;
 302         case PRID_IMP_R4600:
 303                 c->cputype = CPU_R4600;
 304                 c->isa_level = MIPS_CPU_ISA_III;
 305                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 306                              MIPS_CPU_LLSC;
 307                 c->tlbsize = 48;
 308                 break;
 309         #if 0
 310         case PRID_IMP_R4650:
 311                 /*
 312                  * This processor doesn't have an MMU, so it's not
 313                  * "real easy" to run Linux on it. It is left purely
 314                  * for documentation.  Commented out because it shares
 315                  * it's c0_prid id number with the TX3900.
 316                  */
 317                 c->cputype = CPU_R4650;
 318                 c->isa_level = MIPS_CPU_ISA_III;
 319                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 320                 c->tlbsize = 48;
 321                 break;
 322         #endif
 323         case PRID_IMP_TX39:
 324                 c->isa_level = MIPS_CPU_ISA_I;
 325                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 326
 327                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 328                         c->cputype = CPU_TX3927;
 329                         c->tlbsize = 64;
 330                 } else {
 331                         switch (c->processor_id & 0xff) {
 332                         case PRID_REV_TX3912:
 333                                 c->cputype = CPU_TX3912;
 334                                 c->tlbsize = 32;
 335                                 break;
 336                         case PRID_REV_TX3922:
 337                                 c->cputype = CPU_TX3922;
 338                                 c->tlbsize = 64;
 339                                 break;
 340                         default:
 341                                 c->cputype = CPU_UNKNOWN;
 342                                 break;
 343                         }
 344                 }
 345                 break;
 346         case PRID_IMP_R4700:
 347                 c->cputype = CPU_R4700;
 348                 c->isa_level = MIPS_CPU_ISA_III;
 349                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 350                              MIPS_CPU_LLSC;
 351                 c->tlbsize = 48;
 352                 break;
 353         case PRID_IMP_TX49:
 354                 c->cputype = CPU_TX49XX;
 355                 c->isa_level = MIPS_CPU_ISA_III;
 356                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 357                 if (!(c->processor_id & 0x08))
 358                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 359                 c->tlbsize = 48;
 360                 break;
 361         case PRID_IMP_R5000:
 362                 c->cputype = CPU_R5000;
 363                 c->isa_level = MIPS_CPU_ISA_IV;
 364                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 365                              MIPS_CPU_LLSC;
 366                 c->tlbsize = 48;
 367                 break;
 368         case PRID_IMP_R5432:
 369                 c->cputype = CPU_R5432;
 370                 c->isa_level = MIPS_CPU_ISA_IV;
 371                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 372                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 373                 c->tlbsize = 48;
 374                 break;
 375         case PRID_IMP_R5500:
 376                 c->cputype = CPU_R5500;
 377                 c->isa_level = MIPS_CPU_ISA_IV;
 378                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 379                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 380                 c->tlbsize = 48;
 381                 break;
 382         case PRID_IMP_NEVADA:
 383                 c->cputype = CPU_NEVADA;
 384                 c->isa_level = MIPS_CPU_ISA_IV;
 385                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 386                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 387                 c->tlbsize = 48;
 388                 break;
 389         case PRID_IMP_R6000:
 390                 c->cputype = CPU_R6000;
 391                 c->isa_level = MIPS_CPU_ISA_II;
 392                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 393                              MIPS_CPU_LLSC;
 394                 c->tlbsize = 32;
 395                 break;
 396         case PRID_IMP_R6000A:
 397                 c->cputype = CPU_R6000A;
 398                 c->isa_level = MIPS_CPU_ISA_II;
 399                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 400                              MIPS_CPU_LLSC;
 401                 c->tlbsize = 32;
 402                 break;
 403         case PRID_IMP_RM7000:
 404                 c->cputype = CPU_RM7000;
 405                 c->isa_level = MIPS_CPU_ISA_IV;
 406                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 407                              MIPS_CPU_LLSC;
 408                 /*
 409                  * Undocumented RM7000:  Bit 29 in the info register of
 410                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 411                  * entries.
 412                  *
 413                  * 29      1 =>    64 entry JTLB
 414                  *         0 =>    48 entry JTLB
 415                  */
 416                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 417                 break;
 418         case PRID_IMP_RM9000:
 419                 c->cputype = CPU_RM9000;
 420                 c->isa_level = MIPS_CPU_ISA_IV;
 421                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 422                              MIPS_CPU_LLSC;
 423                 /*
 424                  * Bit 29 in the info register of the RM9000
 425                  * indicates if the TLB has 48 or 64 entries.
 426                  *
 427                  * 29      1 =>    64 entry JTLB
 428                  *         0 =>    48 entry JTLB
 429                  */
 430                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 431                 break;
 432         case PRID_IMP_R8000:
 433                 c->cputype = CPU_R8000;
 434                 c->isa_level = MIPS_CPU_ISA_IV;
 435                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 436                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 437                              MIPS_CPU_LLSC;
 438                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 439                 break;
 440         case PRID_IMP_R10000:
 441                 c->cputype = CPU_R10000;
 442                 c->isa_level = MIPS_CPU_ISA_IV;
 443                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 444                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 445                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 446                              MIPS_CPU_LLSC;
 447                 c->tlbsize = 64;
 448                 break;
 449         case PRID_IMP_R12000:
 450                 c->cputype = CPU_R12000;
 451                 c->isa_level = MIPS_CPU_ISA_IV;
 452                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 453                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 454                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 455                              MIPS_CPU_LLSC;
 456                 c->tlbsize = 64;
 457                 break;
 458         case PRID_IMP_R14000:
 459                 c->cputype = CPU_R14000;
 460                 c->isa_level = MIPS_CPU_ISA_IV;
 461                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 462                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 463                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 464                              MIPS_CPU_LLSC;
 465                 c->tlbsize = 64;
 466                 break;
 467         }
 468 }
 469
 470 static char unknown_isa[] __initdata = KERN_ERR \
 471         "Unsupported ISA type, c0.config0: %d.";
 472
 473 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 474 {
 475         unsigned int config0;
 476         int isa;
 477
 478         config0 = read_c0_config();
 479
 480         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 481                 c->options |= MIPS_CPU_TLB;
 482         isa = (config0 & MIPS_CONF_AT) >> 13;
 483         switch (isa) {
 484         case 0:
 485                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 486                 case 0:
 487                         c->isa_level = MIPS_CPU_ISA_M32R1;
 488                         break;
 489                 case 1:
 490                         c->isa_level = MIPS_CPU_ISA_M32R2;
 491                         break;
 492                 default:
 493                         goto unknown;
 494                 }
 495                 break;
 496         case 2:
 497                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 498                 case 0:
 499                         c->isa_level = MIPS_CPU_ISA_M64R1;
 500                         break;
 501                 case 1:
 502                         c->isa_level = MIPS_CPU_ISA_M64R2;
 503                         break;
 504                 default:
 505                         goto unknown;
 506                 }
 507                 break;
 508         default:
 509                 goto unknown;
 510         }
 511
 512         return config0 & MIPS_CONF_M;
 513
 514 unknown:
 515         panic(unknown_isa, config0);
 516 }
 517
 518 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 519 {
 520         unsigned int config1;
 521
 522         config1 = read_c0_config1();
 523
 524         if (config1 & MIPS_CONF1_MD)
 525                 c->ases |= MIPS_ASE_MDMX;
 526         if (config1 & MIPS_CONF1_WR)
 527                 c->options |= MIPS_CPU_WATCH;
 528         if (config1 & MIPS_CONF1_CA)
 529                 c->ases |= MIPS_ASE_MIPS16;
 530         if (config1 & MIPS_CONF1_EP)
 531                 c->options |= MIPS_CPU_EJTAG;
 532         if (config1 & MIPS_CONF1_FP) {
 533                 c->options |= MIPS_CPU_FPU;
 534                 c->options |= MIPS_CPU_32FPR;
 535         }
 536         if (cpu_has_tlb)
 537                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 538
 539         return config1 & MIPS_CONF_M;
 540 }
 541
 542 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 543 {
 544         unsigned int config2;
 545
 546         config2 = read_c0_config2();
 547
 548         if (config2 & MIPS_CONF2_SL)
 549                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 550
 551         return config2 & MIPS_CONF_M;
 552 }
 553
 554 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 555 {
 556         unsigned int config3;
 557
 558         config3 = read_c0_config3();
 559
 560         if (config3 & MIPS_CONF3_SM)
 561                 c->ases |= MIPS_ASE_SMARTMIPS;
 562         if (config3 & MIPS_CONF3_DSP)
 563                 c->ases |= MIPS_ASE_DSP;
 564         if (config3 & MIPS_CONF3_VINT)
 565                 c->options |= MIPS_CPU_VINT;
 566         if (config3 & MIPS_CONF3_VEIC)
 567                 c->options |= MIPS_CPU_VEIC;
 568         if (config3 & MIPS_CONF3_MT)
 569                 c->ases |= MIPS_ASE_MIPSMT;
 570
 571         return config3 & MIPS_CONF_M;
 572 }
 573
 574 static void __init decode_configs(struct cpuinfo_mips *c)
 575 {
 576         /* MIPS32 or MIPS64 compliant CPU.  */
 577         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 578                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 579
 580         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 581
 582         /* Read Config registers.  */
 583         if (!decode_config0(c))
 584                 return;                 /* actually worth a panic() */
 585         if (!decode_config1(c))
 586                 return;
 587         if (!decode_config2(c))
 588                 return;
 589         if (!decode_config3(c))
 590                 return;
 591 }
 592
 593 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 594 {
 595         decode_configs(c);
 596         switch (c->processor_id & 0xff00) {
 597         case PRID_IMP_4KC:
 598                 c->cputype = CPU_4KC;
 599                 break;
 600         case PRID_IMP_4KEC:
 601                 c->cputype = CPU_4KEC;
 602                 break;
 603         case PRID_IMP_4KECR2:
 604                 c->cputype = CPU_4KEC;
 605                 break;
 606         case PRID_IMP_4KSC:
 607         case PRID_IMP_4KSD:
 608                 c->cputype = CPU_4KSC;
 609                 break;
 610         case PRID_IMP_5KC:
 611                 c->cputype = CPU_5KC;
 612                 break;
 613         case PRID_IMP_20KC:
 614                 c->cputype = CPU_20KC;
 615                 break;
 616         case PRID_IMP_24K:
 617         case PRID_IMP_24KE:
 618                 c->cputype = CPU_24K;
 619                 break;
 620         case PRID_IMP_25KF:
 621                 c->cputype = CPU_25KF;
 622                 break;
 623         case PRID_IMP_34K:
 624                 c->cputype = CPU_34K;
 625                 break;
 626         case PRID_IMP_74K:
 627                 c->cputype = CPU_74K;
 628                 break;
 629         }
 630 }
 631
 632 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 633 {
 634         decode_configs(c);
 635         switch (c->processor_id & 0xff00) {
 636         case PRID_IMP_AU1_REV1:
 637         case PRID_IMP_AU1_REV2:
 638                 switch ((c->processor_id >> 24) & 0xff) {
 639                 case 0:
 640                         c->cputype = CPU_AU1000;
 641                         break;
 642                 case 1:
 643                         c->cputype = CPU_AU1500;
 644                         break;
 645                 case 2:
 646                         c->cputype = CPU_AU1100;
 647                         break;
 648                 case 3:
 649                         c->cputype = CPU_AU1550;
 650                         break;
 651                 case 4:
 652                         c->cputype = CPU_AU1200;
 653                         break;
 654                 default:
 655                         panic("Unknown Au Core!");
 656                         break;
 657                 }
 658                 break;
 659         }
 660 }
 661
 662 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 663 {
 664         decode_configs(c);
 665
 666         /*
 667          * For historical reasons the SB1 comes with it's own variant of
 668          * cache code which eventually will be folded into c-r4k.c.  Until
 669          * then we pretend it's got it's own cache architecture.
 670          */
 671         c->options &= ~MIPS_CPU_4K_CACHE;
 672         c->options |= MIPS_CPU_SB1_CACHE;
 673
 674         switch (c->processor_id & 0xff00) {
 675         case PRID_IMP_SB1:
 676                 c->cputype = CPU_SB1;
 677                 /* FPU in pass1 is known to have issues. */
 678                 if ((c->processor_id & 0xff) < 0x02)
 679                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 680                 break;
 681         case PRID_IMP_SB1A:
 682                 c->cputype = CPU_SB1A;
 683                 break;
 684         }
 685 }
 686
 687 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 688 {
 689         decode_configs(c);
 690         switch (c->processor_id & 0xff00) {
 691         case PRID_IMP_SR71000:
 692                 c->cputype = CPU_SR71000;
 693                 c->scache.ways = 8;
 694                 c->tlbsize = 64;
 695                 break;
 696         }
 697 }
 698
 699 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 700 {
 701         decode_configs(c);
 702         switch (c->processor_id & 0xff00) {
 703         case PRID_IMP_PR4450:
 704                 c->cputype = CPU_PR4450;
 705                 c->isa_level = MIPS_CPU_ISA_M32R1;
 706                 break;
 707         default:
 708                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 709                 break;
 710         }
 711 }
 712
 713
 714 __init void cpu_probe(void)
 715 {
 716         struct cpuinfo_mips *c = &current_cpu_data;
 717
 718         c->processor_id = PRID_IMP_UNKNOWN;
 719         c->fpu_id       = FPIR_IMP_NONE;
 720         c->cputype      = CPU_UNKNOWN;
 721
 722         c->processor_id = read_c0_prid();
 723         switch (c->processor_id & 0xff0000) {
 724         case PRID_COMP_LEGACY:
 725                 cpu_probe_legacy(c);
 726                 break;
 727         case PRID_COMP_MIPS:
 728                 cpu_probe_mips(c);
 729                 break;
 730         case PRID_COMP_ALCHEMY:
 731                 cpu_probe_alchemy(c);
 732                 break;
 733         case PRID_COMP_SIBYTE:
 734                 cpu_probe_sibyte(c);
 735                 break;
 736         case PRID_COMP_SANDCRAFT:
 737                 cpu_probe_sandcraft(c);
 738                 break;
 739         case PRID_COMP_PHILIPS:
 740                 cpu_probe_philips(c);
 741                 break;
 742         default:
 743                 c->cputype = CPU_UNKNOWN;
 744         }
 745         if (c->options & MIPS_CPU_FPU) {
 746                 c->fpu_id = cpu_get_fpu_id();
 747
 748                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 749                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 750                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 751                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 752                         if (c->fpu_id & MIPS_FPIR_3D)
 753                                 c->ases |= MIPS_ASE_MIPS3D;
 754                 }
 755         }
 756 }
 757
 758 __init void cpu_report(void)
 759 {
 760         struct cpuinfo_mips *c = &current_cpu_data;
 761
 762         printk("CPU revision is: %08x\n", c->processor_id);
 763         if (c->options & MIPS_CPU_FPU)
 764                 printk("FPU revision is: %08x\n", c->fpu_id);
 765 }