git.oblomov.eu Git - linux-2.6/blob - drivers/message/fusion/lsi/mpi_cnfg.h

   1 /*
   2  *  Copyright (c) 2000-2007 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi_cnfg.h
   6  *          Title:  MPI Config message, structures, and Pages
   7  *  Creation Date:  July 27, 2000
   8  *
   9  *    mpi_cnfg.h Version:  01.05.15
  10  *
  11  *  Version History
  12  *  ---------------
  13  *
  14  *  Date      Version   Description
  15  *  --------  --------  ------------------------------------------------------
  16  *  05-08-00  00.10.01  Original release for 0.10 spec dated 4/26/2000.
  17  *  06-06-00  01.00.01  Update version number for 1.0 release.
  18  *  06-08-00  01.00.02  Added _PAGEVERSION definitions for all pages.
  19  *                      Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
  20  *                      fields to FC_DEVICE_0 page, updated the page version.
  21  *                      Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
  22  *                      SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
  23  *                      and updated the page versions.
  24  *                      Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
  25  *                      page and updated the page version.
  26  *                      Added Information field and _INFO_PARAMS_NEGOTIATED
  27  *                      definitionto SCSI_DEVICE_0 page.
  28  *  06-22-00  01.00.03  Removed batch controls from LAN_0 page and updated the
  29  *                      page version.
  30  *                      Added BucketsRemaining to LAN_1 page, redefined the
  31  *                      state values, and updated the page version.
  32  *                      Revised bus width definitions in SCSI_PORT_0,
  33  *                      SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
  34  *  06-30-00  01.00.04  Added MaxReplySize to LAN_1 page and updated the page
  35  *                      version.
  36  *                      Moved FC_DEVICE_0 PageAddress description to spec.
  37  *  07-27-00  01.00.05  Corrected the SubsystemVendorID and SubsystemID field
  38  *                      widths in IOC_0 page and updated the page version.
  39  *  11-02-00  01.01.01  Original release for post 1.0 work
  40  *                      Added Manufacturing pages, IO Unit Page 2, SCSI SPI
  41  *                      Port Page 2, FC Port Page 4, FC Port Page 5
  42  *  11-15-00  01.01.02  Interim changes to match proposals
  43  *  12-04-00  01.01.03  Config page changes to match MPI rev 1.00.01.
  44  *  12-05-00  01.01.04  Modified config page actions.
  45  *  01-09-01  01.01.05  Added defines for page address formats.
  46  *                      Data size for Manufacturing pages 2 and 3 no longer
  47  *                      defined here.
  48  *                      Io Unit Page 2 size is fixed at 4 adapters and some
  49  *                      flags were changed.
  50  *                      SCSI Port Page 2 Device Settings modified.
  51  *                      New fields added to FC Port Page 0 and some flags
  52  *                      cleaned up.
  53  *                      Removed impedance flash from FC Port Page 1.
  54  *                      Added FC Port pages 6 and 7.
  55  *  01-25-01  01.01.06  Added MaxInitiators field to FcPortPage0.
  56  *  01-29-01  01.01.07  Changed some defines to make them 32 character unique.
  57  *                      Added some LinkType defines for FcPortPage0.
  58  *  02-20-01  01.01.08  Started using MPI_POINTER.
  59  *  02-27-01  01.01.09  Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
  60  *                      MPI_CONFIG_PAGETYPE_RAID_VOLUME.
  61  *                      Added definitions and structures for IOC Page 2 and
  62  *                      RAID Volume Page 2.
  63  *  03-27-01  01.01.10  Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
  64  *                      CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
  65  *                      Added VendorId and ProductRevLevel fields to
  66  *                      RAIDVOL2_IM_PHYS_ID struct.
  67  *                      Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
  68  *                      defines to make them compatible to MPI version 1.0.
  69  *                      Added structure offset comments.
  70  *  04-09-01  01.01.11  Added some new defines for the PageAddress field and
  71  *                      removed some obsolete ones.
  72  *                      Added IO Unit Page 3.
  73  *                      Modified defines for Scsi Port Page 2.
  74  *                      Modified RAID Volume Pages.
  75  *  08-08-01  01.02.01  Original release for v1.2 work.
  76  *                      Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
  77  *                      Added defines for the SEP bits in RVP2 VolumeSettings.
  78  *                      Modified the DeviceSettings field in RVP2 to use the
  79  *                      proper structure.
  80  *                      Added defines for SES, SAF-TE, and cross channel for
  81  *                      IOCPage2 CapabilitiesFlags.
  82  *                      Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
  83  *                      Removed define for
  84  *                      MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
  85  *                      Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
  86  *  08-29-01 01.02.02   Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
  87  *                      Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
  88  *                      and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
  89  *                      Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
  90  *                      MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
  91  *                      MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
  92  *                      MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
  93  *                      Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
  94  *                      and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
  95  *                      Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
  96  *                      Added rejected bits to SCSI Device Page 0 Information.
  97  *                      Increased size of ALPA array in FC Port Page 2 by one
  98  *                      and removed a one byte reserved field.
  99  *  09-28-01 01.02.03   Swapped NegWireSpeedLow and NegWireSpeedLow in
 100  *                      CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
 101  *                      Added structures for Manufacturing Page 4, IO Unit
 102  *                      Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
 103  *                      RAID PhysDisk Page 0.
 104  *  10-04-01 01.02.04   Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
 105  *                      Modified some of the new defines to make them 32
 106  *                      character unique.
 107  *                      Modified how variable length pages (arrays) are defined.
 108  *                      Added generic defines for hot spare pools and RAID
 109  *                      volume types.
 110  *  11-01-01 01.02.05   Added define for MPI_IOUNITPAGE1_DISABLE_IR.
 111  *  03-14-02 01.02.06   Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
 112  *                      related define, and bumped the page version define.
 113  *  05-31-02 01.02.07   Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
 114  *                      reserved byte and added a define.
 115  *                      Added define for
 116  *                      MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
 117  *                      Added new config page: CONFIG_PAGE_IOC_5.
 118  *                      Added MaxAliases, MaxHardAliases, and NumCurrentAliases
 119  *                      fields to CONFIG_PAGE_FC_PORT_0.
 120  *                      Added AltConnector and NumRequestedAliases fields to
 121  *                      CONFIG_PAGE_FC_PORT_1.
 122  *                      Added new config page: CONFIG_PAGE_FC_PORT_10.
 123  *  07-12-02 01.02.08   Added more MPI_MANUFACTPAGE_DEVID_ defines.
 124  *                      Added additional MPI_SCSIDEVPAGE0_NP_ defines.
 125  *                      Added more MPI_SCSIDEVPAGE1_RP_ defines.
 126  *                      Added define for
 127  *                      MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
 128  *                      Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
 129  *                      Modified MPI_FCPORTPAGE5_FLAGS_ defines.
 130  *  09-16-02 01.02.09   Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
 131  *  11-15-02 01.02.10   Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
 132  *                      Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
 133  *                      Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
 134  *  04-01-03 01.02.11   Added RR_TOV field and additional Flags defines for
 135  *                      CONFIG_PAGE_FC_PORT_1.
 136  *                      Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
 137  *                      an alias.
 138  *                      Added more device id defines.
 139  *  06-26-03 01.02.12   Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
 140  *                      Added TargetConfig and IDConfig fields to
 141  *                      CONFIG_PAGE_SCSI_PORT_1.
 142  *                      Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
 143  *                      to control DV.
 144  *                      Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
 145  *                      In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
 146  *                      with ADISCHardALPA.
 147  *                      Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
 148  *  01-16-04 01.02.13   Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
 149  *                      fields and related defines to CONFIG_PAGE_FC_PORT_1.
 150  *                      Added define for
 151  *                      MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
 152  *                      Added new fields to the substructures of
 153  *                      CONFIG_PAGE_FC_PORT_10.
 154  *  04-29-04 01.02.14   Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
 155  *                      CONFIG_PAGE_SCSI_DEVICE_0, and
 156  *                      CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
 157  *                      these pages.
 158  *  05-11-04 01.03.01   Added structure for CONFIG_PAGE_INBAND_0.
 159  *  08-19-04 01.05.01   Modified MSG_CONFIG request to support extended config
 160  *                      pages.
 161  *                      Added a new structure for extended config page header.
 162  *                      Added new extended config pages types and structures for
 163  *                      SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
 164  *                      Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
 165  *                      to add a Flags field.
 166  *                      Two new Manufacturing config pages (5 and 6).
 167  *                      Two new bits defined for IO Unit Page 1 Flags field.
 168  *                      Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
 169  *                      to specify the BIOS boot device.
 170  *                      Four new Flags bits defined for IO Unit Page 2.
 171  *                      Added IO Unit Page 4.
 172  *                      Added EEDP Flags settings to IOC Page 1.
 173  *                      Added new BIOS Page 1 config page.
 174  *  10-05-04 01.05.02   Added define for
 175  *                      MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
 176  *                      Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
 177  *                      associated defines.
 178  *                      Added more defines for SAS IO Unit Page 0
 179  *                      DiscoveryStatus field.
 180  *                      Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
 181  *                      and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
 182  *                      Added defines for Physical Mapping Modes to SAS IO Unit
 183  *                      Page 2.
 184  *                      Added define for
 185  *                      MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
 186  *  10-27-04 01.05.03   Added defines for new SAS PHY page addressing mode.
 187  *                      Added defines for MaxTargetSpinUp to BIOS Page 1.
 188  *                      Added 5 new ControlFlags defines for SAS IO Unit
 189  *                      Page 1.
 190  *                      Added MaxNumPhysicalMappedIDs field to SAS IO Unit
 191  *                      Page 2.
 192  *                      Added AccessStatus field to SAS Device Page 0 and added
 193  *                      new Flags bits for supported SATA features.
 194  *  12-07-04  01.05.04  Added config page structures for BIOS Page 2, RAID
 195  *                      Volume Page 1, and RAID Physical Disk Page 1.
 196  *                      Replaced IO Unit Page 1 BootTargetID,BootBus, and
 197  *                      BootAdapterNum with reserved field.
 198  *                      Added DataScrubRate and ResyncRate to RAID Volume
 199  *                      Page 0.
 200  *                      Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
 201  *                      define.
 202  *  12-09-04  01.05.05  Added Target Mode Large CDB Enable to FC Port Page 1
 203  *                      Flags field.
 204  *                      Added Auto Port Config flag define for SAS IOUNIT
 205  *                      Page 1 ControlFlags.
 206  *                      Added Disabled bad Phy define to Expander Page 1
 207  *                      Discovery Info field.
 208  *                      Added SAS/SATA device support to SAS IOUnit Page 1
 209  *                      ControlFlags.
 210  *                      Added Unsupported device to SAS Dev Page 0 Flags field
 211  *                      Added disable use SATA Hash Address for SAS IOUNIT
 212  *                      page 1 in ControlFields.
 213  *  01-15-05  01.05.06  Added defaults for data scrub rate and resync rate to
 214  *                      Manufacturing Page 4.
 215  *                      Added new defines for BIOS Page 1 IOCSettings field.
 216  *                      Added ExtDiskIdentifier field to RAID Physical Disk
 217  *                      Page 0.
 218  *                      Added new defines for SAS IO Unit Page 1 ControlFlags
 219  *                      and to SAS Device Page 0 Flags to control SATA devices.
 220  *                      Added defines and structures for the new Log Page 0, a
 221  *                      new type of configuration page.
 222  *  02-09-05  01.05.07  Added InactiveStatus field to RAID Volume Page 0.
 223  *                      Added WWID field to RAID Volume Page 1.
 224  *                      Added PhysicalPort field to SAS Expander pages 0 and 1.
 225  *  03-11-05  01.05.08  Removed the EEDP flags from IOC Page 1.
 226  *                      Added Enclosure/Slot boot device format to BIOS Page 2.
 227  *                      New status value for RAID Volume Page 0 VolumeStatus
 228  *                      (VolumeState subfield).
 229  *                      New value for RAID Physical Page 0 InactiveStatus.
 230  *                      Added Inactive Volume Member flag RAID Physical Disk
 231  *                      Page 0 PhysDiskStatus field.
 232  *                      New physical mapping mode in SAS IO Unit Page 2.
 233  *                      Added CONFIG_PAGE_SAS_ENCLOSURE_0.
 234  *                      Added Slot and Enclosure fields to SAS Device Page 0.
 235  *  06-24-05  01.05.09  Added EEDP defines to IOC Page 1.
 236  *                      Added more RAID type defines to IOC Page 2.
 237  *                      Added Port Enable Delay settings to BIOS Page 1.
 238  *                      Added Bad Block Table Full define to RAID Volume Page 0.
 239  *                      Added Previous State defines to RAID Physical Disk
 240  *                      Page 0.
 241  *                      Added Max Sata Targets define for DiscoveryStatus field
 242  *                      of SAS IO Unit Page 0.
 243  *                      Added Device Self Test to Control Flags of SAS IO Unit
 244  *                      Page 1.
 245  *                      Added Direct Attach Starting Slot Number define for SAS
 246  *                      IO Unit Page 2.
 247  *                      Added new fields in SAS Device Page 2 for enclosure
 248  *                      mapping.
 249  *                      Added OwnerDevHandle and Flags field to SAS PHY Page 0.
 250  *                      Added IOC GPIO Flags define to SAS Enclosure Page 0.
 251  *                      Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
 252  *  08-03-05  01.05.10  Removed ISDataScrubRate and ISResyncRate from
 253  *                      Manufacturing Page 4.
 254  *                      Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
 255  *                      Added NumDevsPerEnclosure field to SAS IO Unit page 2.
 256  *                      Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
 257  *                      define.
 258  *                      Added EnclosureHandle field to SAS Expander page 0.
 259  *                      Removed redundant NumTableEntriesProg field from SAS
 260  *                      Expander Page 1.
 261  *  08-30-05  01.05.11  Added DeviceID for FC949E and changed the DeviceID for
 262  *                      SAS1078.
 263  *                      Added more defines for Manufacturing Page 4 Flags field.
 264  *                      Added more defines for IOCSettings and added
 265  *                      ExpanderSpinup field to Bios Page 1.
 266  *                      Added postpone SATA Init bit to SAS IO Unit Page 1
 267  *                      ControlFlags.
 268  *                      Changed LogEntry format for Log Page 0.
 269  *  03-27-06  01.05.12  Added two new Flags defines for Manufacturing Page 4.
 270  *                      Added Manufacturing Page 7.
 271  *                      Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.
 272  *                      Added IOC Page 6.
 273  *                      Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.
 274  *                      Added MaxLBAHigh field to RAID Volume Page 0.
 275  *                      Added Nvdata version fields to SAS IO Unit Page 0.
 276  *                      Added AdditionalControlFlags, MaxTargetPortConnectTime,
 277  *                      ReportDeviceMissingDelay, and IODeviceMissingDelay
 278  *                      fields to SAS IO Unit Page 1.
 279  *  10-11-06  01.05.13  Added NumForceWWID field and ForceWWID array to
 280  *                      Manufacturing Page 5.
 281  *                      Added Manufacturing pages 8 through 10.
 282  *                      Added defines for supported metadata size bits in
 283  *                      CapabilitiesFlags field of IOC Page 6.
 284  *                      Added defines for metadata size bits in VolumeSettings
 285  *                      field of RAID Volume Page 0.
 286  *                      Added SATA Link Reset settings, Enable SATA Asynchronous
 287  *                      Notification bit, and HideNonZeroAttachedPhyIdentifiers
 288  *                      bit to AdditionalControlFlags field of SAS IO Unit
 289  *                      Page 1.
 290  *                      Added defines for Enclosure Devices Unmapped and
 291  *                      Device Limit Exceeded bits in Status field of SAS IO
 292  *                      Unit Page 2.
 293  *                      Added more AccessStatus values for SAS Device Page 0.
 294  *                      Added bit for SATA Asynchronous Notification Support in
 295  *                      Flags field of SAS Device Page 0.
 296  *  02-28-07  01.05.14  Added ExtFlags field to Manufacturing Page 4.
 297  *                      Added Disable SMART Polling for CapabilitiesFlags of
 298  *                      IOC Page 6.
 299  *                      Added Disable SMART Polling to DeviceSettings of BIOS
 300  *                      Page 1.
 301  *                      Added Multi-Port Domain bit for DiscoveryStatus field
 302  *                      of SAS IO Unit Page.
 303  *                      Added Multi-Port Domain Illegal flag for SAS IO Unit
 304  *                      Page 1 AdditionalControlFlags field.
 305  *  05-24-07  01.05.15  Added Hide Physical Disks with Non-Integrated RAID
 306  *                      Metadata bit to Manufacturing Page 4 ExtFlags field.
 307  *                      Added Internal Connector to End Device Present bit to
 308  *                      Expander Page 0 Flags field.
 309  *                      Fixed define for
 310  *                      MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED.
 311  *  --------------------------------------------------------------------------
 312  */
 313
 314 #ifndef MPI_CNFG_H
 315 #define MPI_CNFG_H
 316
 317
 318 /*****************************************************************************
 319 *
 320 *       C o n f i g    M e s s a g e    a n d    S t r u c t u r e s
 321 *
 322 *****************************************************************************/
 323
 324 typedef struct _CONFIG_PAGE_HEADER
 325 {
 326     U8                      PageVersion;                /* 00h */
 327     U8                      PageLength;                 /* 01h */
 328     U8                      PageNumber;                 /* 02h */
 329     U8                      PageType;                   /* 03h */
 330 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
 331   ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
 332
 333 typedef union _CONFIG_PAGE_HEADER_UNION
 334 {
 335    ConfigPageHeader_t  Struct;
 336    U8                  Bytes[4];
 337    U16                 Word16[2];
 338    U32                 Word32;
 339 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
 340   CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
 341
 342 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
 343 {
 344     U8                  PageVersion;                /* 00h */
 345     U8                  Reserved1;                  /* 01h */
 346     U8                  PageNumber;                 /* 02h */
 347     U8                  PageType;                   /* 03h */
 348     U16                 ExtPageLength;              /* 04h */
 349     U8                  ExtPageType;                /* 06h */
 350     U8                  Reserved2;                  /* 07h */
 351 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
 352   ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
 353
 354
 355
 356 /****************************************************************************
 357 *   PageType field values
 358 ****************************************************************************/
 359 #define MPI_CONFIG_PAGEATTR_READ_ONLY               (0x00)
 360 #define MPI_CONFIG_PAGEATTR_CHANGEABLE              (0x10)
 361 #define MPI_CONFIG_PAGEATTR_PERSISTENT              (0x20)
 362 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT           (0x30)
 363 #define MPI_CONFIG_PAGEATTR_MASK                    (0xF0)
 364
 365 #define MPI_CONFIG_PAGETYPE_IO_UNIT                 (0x00)
 366 #define MPI_CONFIG_PAGETYPE_IOC                     (0x01)
 367 #define MPI_CONFIG_PAGETYPE_BIOS                    (0x02)
 368 #define MPI_CONFIG_PAGETYPE_SCSI_PORT               (0x03)
 369 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE             (0x04)
 370 #define MPI_CONFIG_PAGETYPE_FC_PORT                 (0x05)
 371 #define MPI_CONFIG_PAGETYPE_FC_DEVICE               (0x06)
 372 #define MPI_CONFIG_PAGETYPE_LAN                     (0x07)
 373 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME             (0x08)
 374 #define MPI_CONFIG_PAGETYPE_MANUFACTURING           (0x09)
 375 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK           (0x0A)
 376 #define MPI_CONFIG_PAGETYPE_INBAND                  (0x0B)
 377 #define MPI_CONFIG_PAGETYPE_EXTENDED                (0x0F)
 378 #define MPI_CONFIG_PAGETYPE_MASK                    (0x0F)
 379
 380 #define MPI_CONFIG_TYPENUM_MASK                     (0x0FFF)
 381
 382
 383 /****************************************************************************
 384 *   ExtPageType field values
 385 ****************************************************************************/
 386 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT          (0x10)
 387 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER         (0x11)
 388 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE           (0x12)
 389 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY              (0x13)
 390 #define MPI_CONFIG_EXTPAGETYPE_LOG                  (0x14)
 391 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE            (0x15)
 392
 393
 394 /****************************************************************************
 395 *   PageAddress field values
 396 ****************************************************************************/
 397 #define MPI_SCSI_PORT_PGAD_PORT_MASK                (0x000000FF)
 398
 399 #define MPI_SCSI_DEVICE_FORM_MASK                   (0xF0000000)
 400 #define MPI_SCSI_DEVICE_FORM_BUS_TID                (0x00000000)
 401 #define MPI_SCSI_DEVICE_TARGET_ID_MASK              (0x000000FF)
 402 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT             (0)
 403 #define MPI_SCSI_DEVICE_BUS_MASK                    (0x0000FF00)
 404 #define MPI_SCSI_DEVICE_BUS_SHIFT                   (8)
 405 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE            (0x10000000)
 406 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK          (0x000000FF)
 407 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT         (0)
 408 #define MPI_SCSI_DEVICE_TM_BUS_MASK                 (0x0000FF00)
 409 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT                (8)
 410 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK             (0x00FF0000)
 411 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT            (16)
 412
 413 #define MPI_FC_PORT_PGAD_PORT_MASK                  (0xF0000000)
 414 #define MPI_FC_PORT_PGAD_PORT_SHIFT                 (28)
 415 #define MPI_FC_PORT_PGAD_FORM_MASK                  (0x0F000000)
 416 #define MPI_FC_PORT_PGAD_FORM_INDEX                 (0x01000000)
 417 #define MPI_FC_PORT_PGAD_INDEX_MASK                 (0x0000FFFF)
 418 #define MPI_FC_PORT_PGAD_INDEX_SHIFT                (0)
 419
 420 #define MPI_FC_DEVICE_PGAD_PORT_MASK                (0xF0000000)
 421 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT               (28)
 422 #define MPI_FC_DEVICE_PGAD_FORM_MASK                (0x0F000000)
 423 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID            (0x00000000)
 424 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK             (0xF0000000)
 425 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT            (28)
 426 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK              (0x00FFFFFF)
 427 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT             (0)
 428 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID             (0x01000000)
 429 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK              (0x0000FF00)
 430 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT             (8)
 431 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK              (0x000000FF)
 432 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT             (0)
 433
 434 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK          (0x000000FF)
 435 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT         (0)
 436
 437 #define MPI_SAS_EXPAND_PGAD_FORM_MASK             (0xF0000000)
 438 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT            (28)
 439 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
 440 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM   (0x00000001)
 441 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE           (0x00000002)
 442 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE       (0x0000FFFF)
 443 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE      (0)
 444 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY          (0x00FF0000)
 445 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY         (16)
 446 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE       (0x0000FFFF)
 447 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE      (0)
 448 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE         (0x0000FFFF)
 449 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE        (0)
 450
 451 #define MPI_SAS_DEVICE_PGAD_FORM_MASK               (0xF0000000)
 452 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT              (28)
 453 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE    (0x00000000)
 454 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID      (0x00000001)
 455 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE             (0x00000002)
 456 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK         (0x0000FFFF)
 457 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT        (0)
 458 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK             (0x0000FF00)
 459 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT            (8)
 460 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK             (0x000000FF)
 461 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT            (0)
 462 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK           (0x0000FFFF)
 463 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT          (0)
 464
 465 #define MPI_SAS_PHY_PGAD_FORM_MASK                  (0xF0000000)
 466 #define MPI_SAS_PHY_PGAD_FORM_SHIFT                 (28)
 467 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER            (0x0)
 468 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX         (0x1)
 469 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK            (0x000000FF)
 470 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT           (0)
 471 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK         (0x0000FFFF)
 472 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT        (0)
 473
 474 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK               (0xF0000000)
 475 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT              (28)
 476 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE    (0x00000000)
 477 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE             (0x00000001)
 478 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK         (0x0000FFFF)
 479 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT        (0)
 480 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK           (0x0000FFFF)
 481 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT          (0)
 482
 483
 484
 485 /****************************************************************************
 486 *   Config Request Message
 487 ****************************************************************************/
 488 typedef struct _MSG_CONFIG
 489 {
 490     U8                      Action;                     /* 00h */
 491     U8                      Reserved;                   /* 01h */
 492     U8                      ChainOffset;                /* 02h */
 493     U8                      Function;                   /* 03h */
 494     U16                     ExtPageLength;              /* 04h */
 495     U8                      ExtPageType;                /* 06h */
 496     U8                      MsgFlags;                   /* 07h */
 497     U32                     MsgContext;                 /* 08h */
 498     U8                      Reserved2[8];               /* 0Ch */
 499     CONFIG_PAGE_HEADER      Header;                     /* 14h */
 500     U32                     PageAddress;                /* 18h */
 501     SGE_IO_UNION            PageBufferSGE;              /* 1Ch */
 502 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
 503   Config_t, MPI_POINTER pConfig_t;
 504
 505
 506 /****************************************************************************
 507 *   Action field values
 508 ****************************************************************************/
 509 #define MPI_CONFIG_ACTION_PAGE_HEADER               (0x00)
 510 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT         (0x01)
 511 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT        (0x02)
 512 #define MPI_CONFIG_ACTION_PAGE_DEFAULT              (0x03)
 513 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM          (0x04)
 514 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT         (0x05)
 515 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM           (0x06)
 516
 517
 518 /* Config Reply Message */
 519 typedef struct _MSG_CONFIG_REPLY
 520 {
 521     U8                      Action;                     /* 00h */
 522     U8                      Reserved;                   /* 01h */
 523     U8                      MsgLength;                  /* 02h */
 524     U8                      Function;                   /* 03h */
 525     U16                     ExtPageLength;              /* 04h */
 526     U8                      ExtPageType;                /* 06h */
 527     U8                      MsgFlags;                   /* 07h */
 528     U32                     MsgContext;                 /* 08h */
 529     U8                      Reserved2[2];               /* 0Ch */
 530     U16                     IOCStatus;                  /* 0Eh */
 531     U32                     IOCLogInfo;                 /* 10h */
 532     CONFIG_PAGE_HEADER      Header;                     /* 14h */
 533 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
 534   ConfigReply_t, MPI_POINTER pConfigReply_t;
 535
 536
 537
 538 /*****************************************************************************
 539 *
 540 *               C o n f i g u r a t i o n    P a g e s
 541 *
 542 *****************************************************************************/
 543
 544 /****************************************************************************
 545 *   Manufacturing Config pages
 546 ****************************************************************************/
 547 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC          (0x1000)
 548 /* Fibre Channel */
 549 #define MPI_MANUFACTPAGE_DEVICEID_FC909             (0x0621)
 550 #define MPI_MANUFACTPAGE_DEVICEID_FC919             (0x0624)
 551 #define MPI_MANUFACTPAGE_DEVICEID_FC929             (0x0622)
 552 #define MPI_MANUFACTPAGE_DEVICEID_FC919X            (0x0628)
 553 #define MPI_MANUFACTPAGE_DEVICEID_FC929X            (0x0626)
 554 #define MPI_MANUFACTPAGE_DEVICEID_FC939X            (0x0642)
 555 #define MPI_MANUFACTPAGE_DEVICEID_FC949X            (0x0640)
 556 #define MPI_MANUFACTPAGE_DEVICEID_FC949E            (0x0646)
 557 /* SCSI */
 558 #define MPI_MANUFACTPAGE_DEVID_53C1030              (0x0030)
 559 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC            (0x0031)
 560 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035         (0x0032)
 561 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035       (0x0033)
 562 #define MPI_MANUFACTPAGE_DEVID_53C1035              (0x0040)
 563 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC            (0x0041)
 564 /* SAS */
 565 #define MPI_MANUFACTPAGE_DEVID_SAS1064              (0x0050)
 566 #define MPI_MANUFACTPAGE_DEVID_SAS1064A             (0x005C)
 567 #define MPI_MANUFACTPAGE_DEVID_SAS1064E             (0x0056)
 568 #define MPI_MANUFACTPAGE_DEVID_SAS1066              (0x005E)
 569 #define MPI_MANUFACTPAGE_DEVID_SAS1066E             (0x005A)
 570 #define MPI_MANUFACTPAGE_DEVID_SAS1068              (0x0054)
 571 #define MPI_MANUFACTPAGE_DEVID_SAS1068E             (0x0058)
 572 #define MPI_MANUFACTPAGE_DEVID_SAS1078              (0x0062)
 573
 574
 575 typedef struct _CONFIG_PAGE_MANUFACTURING_0
 576 {
 577     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 578     U8                      ChipName[16];               /* 04h */
 579     U8                      ChipRevision[8];            /* 14h */
 580     U8                      BoardName[16];              /* 1Ch */
 581     U8                      BoardAssembly[16];          /* 2Ch */
 582     U8                      BoardTracerNumber[16];      /* 3Ch */
 583
 584 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
 585   ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
 586
 587 #define MPI_MANUFACTURING0_PAGEVERSION                 (0x00)
 588
 589
 590 typedef struct _CONFIG_PAGE_MANUFACTURING_1
 591 {
 592     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 593     U8                      VPD[256];                   /* 04h */
 594 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
 595   ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
 596
 597 #define MPI_MANUFACTURING1_PAGEVERSION                 (0x00)
 598
 599
 600 typedef struct _MPI_CHIP_REVISION_ID
 601 {
 602     U16 DeviceID;                                       /* 00h */
 603     U8  PCIRevisionID;                                  /* 02h */
 604     U8  Reserved;                                       /* 03h */
 605 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
 606   MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
 607
 608
 609 /*
 610  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 611  * one and check Header.PageLength at runtime.
 612  */
 613 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
 614 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS    (1)
 615 #endif
 616
 617 typedef struct _CONFIG_PAGE_MANUFACTURING_2
 618 {
 619     CONFIG_PAGE_HEADER      Header;                                 /* 00h */
 620     MPI_CHIP_REVISION_ID    ChipId;                                 /* 04h */
 621     U32                     HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
 622 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
 623   ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
 624
 625 #define MPI_MANUFACTURING2_PAGEVERSION                  (0x00)
 626
 627
 628 /*
 629  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 630  * one and check Header.PageLength at runtime.
 631  */
 632 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
 633 #define MPI_MAN_PAGE_3_INFO_WORDS           (1)
 634 #endif
 635
 636 typedef struct _CONFIG_PAGE_MANUFACTURING_3
 637 {
 638     CONFIG_PAGE_HEADER                  Header;                     /* 00h */
 639     MPI_CHIP_REVISION_ID                ChipId;                     /* 04h */
 640     U32                                 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
 641 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
 642   ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
 643
 644 #define MPI_MANUFACTURING3_PAGEVERSION                  (0x00)
 645
 646
 647 typedef struct _CONFIG_PAGE_MANUFACTURING_4
 648 {
 649     CONFIG_PAGE_HEADER              Header;             /* 00h */
 650     U32                             Reserved1;          /* 04h */
 651     U8                              InfoOffset0;        /* 08h */
 652     U8                              InfoSize0;          /* 09h */
 653     U8                              InfoOffset1;        /* 0Ah */
 654     U8                              InfoSize1;          /* 0Bh */
 655     U8                              InquirySize;        /* 0Ch */
 656     U8                              Flags;              /* 0Dh */
 657     U16                             ExtFlags;           /* 0Eh */
 658     U8                              InquiryData[56];    /* 10h */
 659     U32                             ISVolumeSettings;   /* 48h */
 660     U32                             IMEVolumeSettings;  /* 4Ch */
 661     U32                             IMVolumeSettings;   /* 50h */
 662     U32                             Reserved3;          /* 54h */
 663     U32                             Reserved4;          /* 58h */
 664     U32                             Reserved5;          /* 5Ch */
 665     U8                              IMEDataScrubRate;   /* 60h */
 666     U8                              IMEResyncRate;      /* 61h */
 667     U16                             Reserved6;          /* 62h */
 668     U8                              IMDataScrubRate;    /* 64h */
 669     U8                              IMResyncRate;       /* 65h */
 670     U16                             Reserved7;          /* 66h */
 671     U32                             Reserved8;          /* 68h */
 672     U32                             Reserved9;          /* 6Ch */
 673 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
 674   ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
 675
 676 #define MPI_MANUFACTURING4_PAGEVERSION                  (0x05)
 677
 678 /* defines for the Flags field */
 679 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE              (0x80)
 680 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER             (0x40)
 681 #define MPI_MANPAGE4_IME_DISABLE                        (0x20)
 682 #define MPI_MANPAGE4_IM_DISABLE                         (0x10)
 683 #define MPI_MANPAGE4_IS_DISABLE                         (0x08)
 684 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE               (0x04)
 685 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE             (0x02)
 686 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA                 (0x01)
 687
 688 /* defines for the ExtFlags field */
 689 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA      (0x0008)
 690 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE         (0x0004)
 691 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE        (0x0002)
 692 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE               (0x0001)
 693
 694
 695 #ifndef MPI_MANPAGE5_NUM_FORCEWWID
 696 #define MPI_MANPAGE5_NUM_FORCEWWID      (1)
 697 #endif
 698
 699 typedef struct _CONFIG_PAGE_MANUFACTURING_5
 700 {
 701     CONFIG_PAGE_HEADER              Header;             /* 00h */
 702     U64                             BaseWWID;           /* 04h */
 703     U8                              Flags;              /* 0Ch */
 704     U8                              NumForceWWID;       /* 0Dh */
 705     U16                             Reserved2;          /* 0Eh */
 706     U32                             Reserved3;          /* 10h */
 707     U32                             Reserved4;          /* 14h */
 708     U64                             ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */
 709 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
 710   ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
 711
 712 #define MPI_MANUFACTURING5_PAGEVERSION                  (0x02)
 713
 714 /* defines for the Flags field */
 715 #define MPI_MANPAGE5_TWO_WWID_PER_PHY                   (0x01)
 716
 717
 718 typedef struct _CONFIG_PAGE_MANUFACTURING_6
 719 {
 720     CONFIG_PAGE_HEADER              Header;             /* 00h */
 721     U32                             ProductSpecificInfo;/* 04h */
 722 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
 723   ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
 724
 725 #define MPI_MANUFACTURING6_PAGEVERSION                  (0x00)
 726
 727
 728 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO
 729 {
 730     U32                         Pinout;                 /* 00h */
 731     U8                          Connector[16];          /* 04h */
 732     U8                          Location;               /* 14h */
 733     U8                          Reserved1;              /* 15h */
 734     U16                         Slot;                   /* 16h */
 735     U32                         Reserved2;              /* 18h */
 736 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,
 737   MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;
 738
 739 /* defines for the Pinout field */
 740 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4                 (0x00080000)
 741 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3                 (0x00040000)
 742 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2                 (0x00020000)
 743 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1                 (0x00010000)
 744 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4                 (0x00000800)
 745 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3                 (0x00000400)
 746 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2                 (0x00000200)
 747 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1                 (0x00000100)
 748 #define MPI_MANPAGE7_PINOUT_SFF_8482                    (0x00000002)
 749 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN          (0x00000001)
 750
 751 /* defines for the Location field */
 752 #define MPI_MANPAGE7_LOCATION_UNKNOWN                   (0x01)
 753 #define MPI_MANPAGE7_LOCATION_INTERNAL                  (0x02)
 754 #define MPI_MANPAGE7_LOCATION_EXTERNAL                  (0x04)
 755 #define MPI_MANPAGE7_LOCATION_SWITCHABLE                (0x08)
 756 #define MPI_MANPAGE7_LOCATION_AUTO                      (0x10)
 757 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT               (0x20)
 758 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED             (0x80)
 759
 760 /*
 761  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 762  * one and check NumPhys at runtime.
 763  */
 764 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX
 765 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX   (1)
 766 #endif
 767
 768 typedef struct _CONFIG_PAGE_MANUFACTURING_7
 769 {
 770     CONFIG_PAGE_HEADER          Header;                 /* 00h */
 771     U32                         Reserved1;              /* 04h */
 772     U32                         Reserved2;              /* 08h */
 773     U32                         Flags;                  /* 0Ch */
 774     U8                          EnclosureName[16];      /* 10h */
 775     U8                          NumPhys;                /* 20h */
 776     U8                          Reserved3;              /* 21h */
 777     U16                         Reserved4;              /* 22h */
 778     MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
 779 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,
 780   ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;
 781
 782 #define MPI_MANUFACTURING7_PAGEVERSION                  (0x00)
 783
 784 /* defines for the Flags field */
 785 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO                 (0x00000001)
 786
 787
 788 typedef struct _CONFIG_PAGE_MANUFACTURING_8
 789 {
 790     CONFIG_PAGE_HEADER              Header;             /* 00h */
 791     U32                             ProductSpecificInfo;/* 04h */
 792 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8,
 793   ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;
 794
 795 #define MPI_MANUFACTURING8_PAGEVERSION                  (0x00)
 796
 797
 798 typedef struct _CONFIG_PAGE_MANUFACTURING_9
 799 {
 800     CONFIG_PAGE_HEADER              Header;             /* 00h */
 801     U32                             ProductSpecificInfo;/* 04h */
 802 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9,
 803   ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;
 804
 805 #define MPI_MANUFACTURING9_PAGEVERSION                  (0x00)
 806
 807
 808 typedef struct _CONFIG_PAGE_MANUFACTURING_10
 809 {
 810     CONFIG_PAGE_HEADER              Header;             /* 00h */
 811     U32                             ProductSpecificInfo;/* 04h */
 812 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10,
 813   ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;
 814
 815 #define MPI_MANUFACTURING10_PAGEVERSION                 (0x00)
 816
 817
 818 /****************************************************************************
 819 *   IO Unit Config Pages
 820 ****************************************************************************/
 821
 822 typedef struct _CONFIG_PAGE_IO_UNIT_0
 823 {
 824     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 825     U64                     UniqueValue;                /* 04h */
 826 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
 827   IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
 828
 829 #define MPI_IOUNITPAGE0_PAGEVERSION                     (0x00)
 830
 831
 832 typedef struct _CONFIG_PAGE_IO_UNIT_1
 833 {
 834     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 835     U32                     Flags;                      /* 04h */
 836 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
 837   IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
 838
 839 #define MPI_IOUNITPAGE1_PAGEVERSION                     (0x02)
 840
 841 /* IO Unit Page 1 Flags defines */
 842 #define MPI_IOUNITPAGE1_MULTI_FUNCTION                  (0x00000000)
 843 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION                 (0x00000001)
 844 #define MPI_IOUNITPAGE1_MULTI_PATHING                   (0x00000002)
 845 #define MPI_IOUNITPAGE1_SINGLE_PATHING                  (0x00000000)
 846 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID         (0x00000004)
 847 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING     (0x00000020)
 848 #define MPI_IOUNITPAGE1_DISABLE_IR                      (0x00000040)
 849 #define MPI_IOUNITPAGE1_FORCE_32                        (0x00000080)
 850 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE        (0x00000100)
 851 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE        (0x00000200)
 852
 853 typedef struct _MPI_ADAPTER_INFO
 854 {
 855     U8      PciBusNumber;                               /* 00h */
 856     U8      PciDeviceAndFunctionNumber;                 /* 01h */
 857     U16     AdapterFlags;                               /* 02h */
 858 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
 859   MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
 860
 861 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED                 (0x0001)
 862 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS              (0x0002)
 863
 864 typedef struct _CONFIG_PAGE_IO_UNIT_2
 865 {
 866     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 867     U32                     Flags;                      /* 04h */
 868     U32                     BiosVersion;                /* 08h */
 869     MPI_ADAPTER_INFO        AdapterOrder[4];            /* 0Ch */
 870     U32                     Reserved1;                  /* 1Ch */
 871 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
 872   IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
 873
 874 #define MPI_IOUNITPAGE2_PAGEVERSION                     (0x02)
 875
 876 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR            (0x00000002)
 877 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE            (0x00000004)
 878 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE       (0x00000008)
 879 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40          (0x00000010)
 880
 881 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK     (0x000000E0)
 882 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY     (0x00000000)
 883 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY           (0x00000020)
 884 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY       (0x00000040)
 885
 886
 887 /*
 888  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 889  * one and check Header.PageLength at runtime.
 890  */
 891 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
 892 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX     (1)
 893 #endif
 894
 895 typedef struct _CONFIG_PAGE_IO_UNIT_3
 896 {
 897     CONFIG_PAGE_HEADER      Header;                                   /* 00h */
 898     U8                      GPIOCount;                                /* 04h */
 899     U8                      Reserved1;                                /* 05h */
 900     U16                     Reserved2;                                /* 06h */
 901     U16                     GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
 902 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
 903   IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
 904
 905 #define MPI_IOUNITPAGE3_PAGEVERSION                     (0x01)
 906
 907 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK              (0xFC)
 908 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT             (2)
 909 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF                (0x00)
 910 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON                 (0x01)
 911
 912
 913 typedef struct _CONFIG_PAGE_IO_UNIT_4
 914 {
 915     CONFIG_PAGE_HEADER      Header;                                   /* 00h */
 916     U32                     Reserved1;                                /* 04h */
 917     SGE_SIMPLE_UNION        FWImageSGE;                               /* 08h */
 918 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
 919   IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
 920
 921 #define MPI_IOUNITPAGE4_PAGEVERSION                     (0x00)
 922
 923
 924 /****************************************************************************
 925 *   IOC Config Pages
 926 ****************************************************************************/
 927
 928 typedef struct _CONFIG_PAGE_IOC_0
 929 {
 930     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 931     U32                     TotalNVStore;               /* 04h */
 932     U32                     FreeNVStore;                /* 08h */
 933     U16                     VendorID;                   /* 0Ch */
 934     U16                     DeviceID;                   /* 0Eh */
 935     U8                      RevisionID;                 /* 10h */
 936     U8                      Reserved[3];                /* 11h */
 937     U32                     ClassCode;                  /* 14h */
 938     U16                     SubsystemVendorID;          /* 18h */
 939     U16                     SubsystemID;                /* 1Ah */
 940 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
 941   IOCPage0_t, MPI_POINTER pIOCPage0_t;
 942
 943 #define MPI_IOCPAGE0_PAGEVERSION                        (0x01)
 944
 945
 946 typedef struct _CONFIG_PAGE_IOC_1
 947 {
 948     CONFIG_PAGE_HEADER      Header;                     /* 00h */
 949     U32                     Flags;                      /* 04h */
 950     U32                     CoalescingTimeout;          /* 08h */
 951     U8                      CoalescingDepth;            /* 0Ch */
 952     U8                      PCISlotNum;                 /* 0Dh */
 953     U8                      Reserved[2];                /* 0Eh */
 954 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
 955   IOCPage1_t, MPI_POINTER pIOCPage1_t;
 956
 957 #define MPI_IOCPAGE1_PAGEVERSION                        (0x03)
 958
 959 /* defines for the Flags field */
 960 #define MPI_IOCPAGE1_EEDP_MODE_MASK                     (0x07000000)
 961 #define MPI_IOCPAGE1_EEDP_MODE_OFF                      (0x00000000)
 962 #define MPI_IOCPAGE1_EEDP_MODE_T10                      (0x01000000)
 963 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1                    (0x02000000)
 964 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE    (0x00000010)
 965 #define MPI_IOCPAGE1_REPLY_COALESCING                   (0x00000001)
 966
 967 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN                 (0xFF)
 968
 969
 970 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
 971 {
 972     U8                          VolumeID;               /* 00h */
 973     U8                          VolumeBus;              /* 01h */
 974     U8                          VolumeIOC;              /* 02h */
 975     U8                          VolumePageNumber;       /* 03h */
 976     U8                          VolumeType;             /* 04h */
 977     U8                          Flags;                  /* 05h */
 978     U16                         Reserved3;              /* 06h */
 979 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
 980   ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
 981
 982 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
 983
 984 #define MPI_RAID_VOL_TYPE_IS                        (0x00)
 985 #define MPI_RAID_VOL_TYPE_IME                       (0x01)
 986 #define MPI_RAID_VOL_TYPE_IM                        (0x02)
 987 #define MPI_RAID_VOL_TYPE_RAID_5                    (0x03)
 988 #define MPI_RAID_VOL_TYPE_RAID_6                    (0x04)
 989 #define MPI_RAID_VOL_TYPE_RAID_10                   (0x05)
 990 #define MPI_RAID_VOL_TYPE_RAID_50                   (0x06)
 991 #define MPI_RAID_VOL_TYPE_UNKNOWN                   (0xFF)
 992
 993 /* IOC Page 2 Volume Flags values */
 994
 995 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE           (0x08)
 996
 997 /*
 998  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 999  * one and check Header.PageLength at runtime.
1000  */
1001 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
1002 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX      (1)
1003 #endif
1004
1005 typedef struct _CONFIG_PAGE_IOC_2
1006 {
1007     CONFIG_PAGE_HEADER          Header;                              /* 00h */
1008     U32                         CapabilitiesFlags;                   /* 04h */
1009     U8                          NumActiveVolumes;                    /* 08h */
1010     U8                          MaxVolumes;                          /* 09h */
1011     U8                          NumActivePhysDisks;                  /* 0Ah */
1012     U8                          MaxPhysDisks;                        /* 0Bh */
1013     CONFIG_PAGE_IOC_2_RAID_VOL  RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
1014 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
1015   IOCPage2_t, MPI_POINTER pIOCPage2_t;
1016
1017 #define MPI_IOCPAGE2_PAGEVERSION                        (0x04)
1018
1019 /* IOC Page 2 Capabilities flags */
1020
1021 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT               (0x00000001)
1022 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT              (0x00000002)
1023 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT               (0x00000004)
1024 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT           (0x00000008)
1025 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT           (0x00000010)
1026 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT          (0x00000020)
1027 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT          (0x00000040)
1028 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING   (0x10000000)
1029 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT              (0x20000000)
1030 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT            (0x40000000)
1031 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT    (0x80000000)
1032
1033
1034 typedef struct _IOC_3_PHYS_DISK
1035 {
1036     U8                          PhysDiskID;             /* 00h */
1037     U8                          PhysDiskBus;            /* 01h */
1038     U8                          PhysDiskIOC;            /* 02h */
1039     U8                          PhysDiskNum;            /* 03h */
1040 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
1041   Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
1042
1043 /*
1044  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1045  * one and check Header.PageLength at runtime.
1046  */
1047 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
1048 #define MPI_IOC_PAGE_3_PHYSDISK_MAX         (1)
1049 #endif
1050
1051 typedef struct _CONFIG_PAGE_IOC_3
1052 {
1053     CONFIG_PAGE_HEADER          Header;                                /* 00h */
1054     U8                          NumPhysDisks;                          /* 04h */
1055     U8                          Reserved1;                             /* 05h */
1056     U16                         Reserved2;                             /* 06h */
1057     IOC_3_PHYS_DISK             PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
1058 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
1059   IOCPage3_t, MPI_POINTER pIOCPage3_t;
1060
1061 #define MPI_IOCPAGE3_PAGEVERSION                        (0x00)
1062
1063
1064 typedef struct _IOC_4_SEP
1065 {
1066     U8                          SEPTargetID;            /* 00h */
1067     U8                          SEPBus;                 /* 01h */
1068     U16                         Reserved;               /* 02h */
1069 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
1070   Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
1071
1072 /*
1073  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1074  * one and check Header.PageLength at runtime.
1075  */
1076 #ifndef MPI_IOC_PAGE_4_SEP_MAX
1077 #define MPI_IOC_PAGE_4_SEP_MAX              (1)
1078 #endif
1079
1080 typedef struct _CONFIG_PAGE_IOC_4
1081 {
1082     CONFIG_PAGE_HEADER          Header;                         /* 00h */
1083     U8                          ActiveSEP;                      /* 04h */
1084     U8                          MaxSEP;                         /* 05h */
1085     U16                         Reserved1;                      /* 06h */
1086     IOC_4_SEP                   SEP[MPI_IOC_PAGE_4_SEP_MAX];    /* 08h */
1087 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
1088   IOCPage4_t, MPI_POINTER pIOCPage4_t;
1089
1090 #define MPI_IOCPAGE4_PAGEVERSION                        (0x00)
1091
1092
1093 typedef struct _IOC_5_HOT_SPARE
1094 {
1095     U8                          PhysDiskNum;            /* 00h */
1096     U8                          Reserved;               /* 01h */
1097     U8                          HotSparePool;           /* 02h */
1098     U8                          Flags;                   /* 03h */
1099 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
1100   Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
1101
1102 /* IOC Page 5 HotSpare Flags */
1103 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE                 (0x01)
1104
1105 /*
1106  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1107  * one and check Header.PageLength at runtime.
1108  */
1109 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
1110 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX        (1)
1111 #endif
1112
1113 typedef struct _CONFIG_PAGE_IOC_5
1114 {
1115     CONFIG_PAGE_HEADER          Header;                         /* 00h */
1116     U32                         Reserved1;                      /* 04h */
1117     U8                          NumHotSpares;                   /* 08h */
1118     U8                          Reserved2;                      /* 09h */
1119     U16                         Reserved3;                      /* 0Ah */
1120     IOC_5_HOT_SPARE             HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
1121 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
1122   IOCPage5_t, MPI_POINTER pIOCPage5_t;
1123
1124 #define MPI_IOCPAGE5_PAGEVERSION                        (0x00)
1125
1126 typedef struct _CONFIG_PAGE_IOC_6
1127 {
1128     CONFIG_PAGE_HEADER          Header;                         /* 00h */
1129     U32                         CapabilitiesFlags;              /* 04h */
1130     U8                          MaxDrivesIS;                    /* 08h */
1131     U8                          MaxDrivesIM;                    /* 09h */
1132     U8                          MaxDrivesIME;                   /* 0Ah */
1133     U8                          Reserved1;                      /* 0Bh */
1134     U8                          MinDrivesIS;                    /* 0Ch */
1135     U8                          MinDrivesIM;                    /* 0Dh */
1136     U8                          MinDrivesIME;                   /* 0Eh */
1137     U8                          Reserved2;                      /* 0Fh */
1138     U8                          MaxGlobalHotSpares;             /* 10h */
1139     U8                          Reserved3;                      /* 11h */
1140     U16                         Reserved4;                      /* 12h */
1141     U32                         Reserved5;                      /* 14h */
1142     U32                         SupportedStripeSizeMapIS;       /* 18h */
1143     U32                         SupportedStripeSizeMapIME;      /* 1Ch */
1144     U32                         Reserved6;                      /* 20h */
1145     U8                          MetadataSize;                   /* 24h */
1146     U8                          Reserved7;                      /* 25h */
1147     U16                         Reserved8;                      /* 26h */
1148     U16                         MaxBadBlockTableEntries;        /* 28h */
1149     U16                         Reserved9;                      /* 2Ah */
1150     U16                         IRNvsramUsage;                  /* 2Ch */
1151     U16                         Reserved10;                     /* 2Eh */
1152     U32                         IRNvsramVersion;                /* 30h */
1153     U32                         Reserved11;                     /* 34h */
1154     U32                         Reserved12;                     /* 38h */
1155 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,
1156   IOCPage6_t, MPI_POINTER pIOCPage6_t;
1157
1158 #define MPI_IOCPAGE6_PAGEVERSION                        (0x01)
1159
1160 /* IOC Page 6 Capabilities Flags */
1161
1162 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING    (0x00000008)
1163
1164 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE       (0x00000006)
1165 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE       (0x00000000)
1166 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE      (0x00000002)
1167
1168 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE         (0x00000001)
1169
1170
1171 /****************************************************************************
1172 *   BIOS Config Pages
1173 ****************************************************************************/
1174
1175 typedef struct _CONFIG_PAGE_BIOS_1
1176 {
1177     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1178     U32                     BiosOptions;                /* 04h */
1179     U32                     IOCSettings;                /* 08h */
1180     U32                     Reserved1;                  /* 0Ch */
1181     U32                     DeviceSettings;             /* 10h */
1182     U16                     NumberOfDevices;            /* 14h */
1183     U8                      ExpanderSpinup;             /* 16h */
1184     U8                      Reserved2;                  /* 17h */
1185     U16                     IOTimeoutBlockDevicesNonRM; /* 18h */
1186     U16                     IOTimeoutSequential;        /* 1Ah */
1187     U16                     IOTimeoutOther;             /* 1Ch */
1188     U16                     IOTimeoutBlockDevicesRM;    /* 1Eh */
1189 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
1190   BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1191
1192 #define MPI_BIOSPAGE1_PAGEVERSION                       (0x03)
1193
1194 /* values for the BiosOptions field */
1195 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE                (0x00000400)
1196 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE                 (0x00000200)
1197 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE                (0x00000100)
1198 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS              (0x00000001)
1199
1200 /* values for the IOCSettings field */
1201 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY  (0x0F000000)
1202 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1203
1204 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY     (0x00F00000)
1205 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY    (20)
1206
1207 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE           (0x00080000)
1208 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE  (0x00040000)
1209
1210 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE       (0x00030000)
1211 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT        (0x00000000)
1212 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT           (0x00010000)
1213
1214 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP    (0x0000F000)
1215 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP   (12)
1216
1217 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY          (0x00000F00)
1218 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY         (8)
1219
1220 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING            (0x000000C0)
1221 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING            (0x00000000)
1222 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING            (0x00000040)
1223 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING           (0x00000080)
1224
1225 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT       (0x00000030)
1226 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT                 (0x00000000)
1227 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT               (0x00000010)
1228 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT                 (0x00000020)
1229 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT                (0x00000030)
1230
1231 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS              (0x00000008)
1232
1233 /* values for the DeviceSettings field */
1234 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING      (0x00000010)
1235 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN            (0x00000008)
1236 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN             (0x00000004)
1237 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN         (0x00000002)
1238 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN          (0x00000001)
1239
1240 /* defines for the ExpanderSpinup field */
1241 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET         (0xF0)
1242 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET        (4)
1243 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY              (0x0F)
1244
1245 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1246 {
1247     U32         Reserved1;                              /* 00h */
1248     U32         Reserved2;                              /* 04h */
1249     U32         Reserved3;                              /* 08h */
1250     U32         Reserved4;                              /* 0Ch */
1251     U32         Reserved5;                              /* 10h */
1252     U32         Reserved6;                              /* 14h */
1253     U32         Reserved7;                              /* 18h */
1254     U32         Reserved8;                              /* 1Ch */
1255     U32         Reserved9;                              /* 20h */
1256     U32         Reserved10;                             /* 24h */
1257     U32         Reserved11;                             /* 28h */
1258     U32         Reserved12;                             /* 2Ch */
1259     U32         Reserved13;                             /* 30h */
1260     U32         Reserved14;                             /* 34h */
1261     U32         Reserved15;                             /* 38h */
1262     U32         Reserved16;                             /* 3Ch */
1263     U32         Reserved17;                             /* 40h */
1264 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1265
1266 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1267 {
1268     U8          TargetID;                               /* 00h */
1269     U8          Bus;                                    /* 01h */
1270     U8          AdapterNumber;                          /* 02h */
1271     U8          Reserved1;                              /* 03h */
1272     U32         Reserved2;                              /* 04h */
1273     U32         Reserved3;                              /* 08h */
1274     U32         Reserved4;                              /* 0Ch */
1275     U8          LUN[8];                                 /* 10h */
1276     U32         Reserved5;                              /* 18h */
1277     U32         Reserved6;                              /* 1Ch */
1278     U32         Reserved7;                              /* 20h */
1279     U32         Reserved8;                              /* 24h */
1280     U32         Reserved9;                              /* 28h */
1281     U32         Reserved10;                             /* 2Ch */
1282     U32         Reserved11;                             /* 30h */
1283     U32         Reserved12;                             /* 34h */
1284     U32         Reserved13;                             /* 38h */
1285     U32         Reserved14;                             /* 3Ch */
1286     U32         Reserved15;                             /* 40h */
1287 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1288
1289 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1290 {
1291     U8          TargetID;                               /* 00h */
1292     U8          Bus;                                    /* 01h */
1293     U16         PCIAddress;                             /* 02h */
1294     U32         Reserved1;                              /* 04h */
1295     U32         Reserved2;                              /* 08h */
1296     U32         Reserved3;                              /* 0Ch */
1297     U8          LUN[8];                                 /* 10h */
1298     U32         Reserved4;                              /* 18h */
1299     U32         Reserved5;                              /* 1Ch */
1300     U32         Reserved6;                              /* 20h */
1301     U32         Reserved7;                              /* 24h */
1302     U32         Reserved8;                              /* 28h */
1303     U32         Reserved9;                              /* 2Ch */
1304     U32         Reserved10;                             /* 30h */
1305     U32         Reserved11;                             /* 34h */
1306     U32         Reserved12;                             /* 38h */
1307     U32         Reserved13;                             /* 3Ch */
1308     U32         Reserved14;                             /* 40h */
1309 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1310
1311 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1312 {
1313     U8          TargetID;                               /* 00h */
1314     U8          Bus;                                    /* 01h */
1315     U8          PCISlotNumber;                          /* 02h */
1316     U8          Reserved1;                              /* 03h */
1317     U32         Reserved2;                              /* 04h */
1318     U32         Reserved3;                              /* 08h */
1319     U32         Reserved4;                              /* 0Ch */
1320     U8          LUN[8];                                 /* 10h */
1321     U32         Reserved5;                              /* 18h */
1322     U32         Reserved6;                              /* 1Ch */
1323     U32         Reserved7;                              /* 20h */
1324     U32         Reserved8;                              /* 24h */
1325     U32         Reserved9;                              /* 28h */
1326     U32         Reserved10;                             /* 2Ch */
1327     U32         Reserved11;                             /* 30h */
1328     U32         Reserved12;                             /* 34h */
1329     U32         Reserved13;                             /* 38h */
1330     U32         Reserved14;                             /* 3Ch */
1331     U32         Reserved15;                             /* 40h */
1332 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1333
1334 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1335 {
1336     U64         WWPN;                                   /* 00h */
1337     U32         Reserved1;                              /* 08h */
1338     U32         Reserved2;                              /* 0Ch */
1339     U8          LUN[8];                                 /* 10h */
1340     U32         Reserved3;                              /* 18h */
1341     U32         Reserved4;                              /* 1Ch */
1342     U32         Reserved5;                              /* 20h */
1343     U32         Reserved6;                              /* 24h */
1344     U32         Reserved7;                              /* 28h */
1345     U32         Reserved8;                              /* 2Ch */
1346     U32         Reserved9;                              /* 30h */
1347     U32         Reserved10;                             /* 34h */
1348     U32         Reserved11;                             /* 38h */
1349     U32         Reserved12;                             /* 3Ch */
1350     U32         Reserved13;                             /* 40h */
1351 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1352
1353 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1354 {
1355     U64         SASAddress;                             /* 00h */
1356     U32         Reserved1;                              /* 08h */
1357     U32         Reserved2;                              /* 0Ch */
1358     U8          LUN[8];                                 /* 10h */
1359     U32         Reserved3;                              /* 18h */
1360     U32         Reserved4;                              /* 1Ch */
1361     U32         Reserved5;                              /* 20h */
1362     U32         Reserved6;                              /* 24h */
1363     U32         Reserved7;                              /* 28h */
1364     U32         Reserved8;                              /* 2Ch */
1365     U32         Reserved9;                              /* 30h */
1366     U32         Reserved10;                             /* 34h */
1367     U32         Reserved11;                             /* 38h */
1368     U32         Reserved12;                             /* 3Ch */
1369     U32         Reserved13;                             /* 40h */
1370 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1371
1372 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1373 {
1374     U64         EnclosureLogicalID;                     /* 00h */
1375     U32         Reserved1;                              /* 08h */
1376     U32         Reserved2;                              /* 0Ch */
1377     U8          LUN[8];                                 /* 10h */
1378     U16         SlotNumber;                             /* 18h */
1379     U16         Reserved3;                              /* 1Ah */
1380     U32         Reserved4;                              /* 1Ch */
1381     U32         Reserved5;                              /* 20h */
1382     U32         Reserved6;                              /* 24h */
1383     U32         Reserved7;                              /* 28h */
1384     U32         Reserved8;                              /* 2Ch */
1385     U32         Reserved9;                              /* 30h */
1386     U32         Reserved10;                             /* 34h */
1387     U32         Reserved11;                             /* 38h */
1388     U32         Reserved12;                             /* 3Ch */
1389     U32         Reserved13;                             /* 40h */
1390 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1391   MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1392
1393 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1394 {
1395     MPI_BOOT_DEVICE_ADAPTER_ORDER   AdapterOrder;
1396     MPI_BOOT_DEVICE_ADAPTER_NUMBER  AdapterNumber;
1397     MPI_BOOT_DEVICE_PCI_ADDRESS     PCIAddress;
1398     MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1399     MPI_BOOT_DEVICE_FC_WWN          FcWwn;
1400     MPI_BOOT_DEVICE_SAS_WWN         SasWwn;
1401     MPI_BOOT_DEVICE_ENCLOSURE_SLOT  EnclosureSlot;
1402 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1403
1404 typedef struct _CONFIG_PAGE_BIOS_2
1405 {
1406     CONFIG_PAGE_HEADER          Header;                 /* 00h */
1407     U32                         Reserved1;              /* 04h */
1408     U32                         Reserved2;              /* 08h */
1409     U32                         Reserved3;              /* 0Ch */
1410     U32                         Reserved4;              /* 10h */
1411     U32                         Reserved5;              /* 14h */
1412     U32                         Reserved6;              /* 18h */
1413     U8                          BootDeviceForm;         /* 1Ch */
1414     U8                          PrevBootDeviceForm;     /* 1Ch */
1415     U16                         Reserved8;              /* 1Eh */
1416     MPI_BIOSPAGE2_BOOT_DEVICE   BootDevice;             /* 20h */
1417 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1418   BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1419
1420 #define MPI_BIOSPAGE2_PAGEVERSION                       (0x02)
1421
1422 #define MPI_BIOSPAGE2_FORM_MASK                         (0x0F)
1423 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER                (0x00)
1424 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER               (0x01)
1425 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS                  (0x02)
1426 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER              (0x03)
1427 #define MPI_BIOSPAGE2_FORM_FC_WWN                       (0x04)
1428 #define MPI_BIOSPAGE2_FORM_SAS_WWN                      (0x05)
1429 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT               (0x06)
1430
1431
1432 /****************************************************************************
1433 *   SCSI Port Config Pages
1434 ****************************************************************************/
1435
1436 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1437 {
1438     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1439     U32                     Capabilities;               /* 04h */
1440     U32                     PhysicalInterface;          /* 08h */
1441 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1442   SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1443
1444 #define MPI_SCSIPORTPAGE0_PAGEVERSION                   (0x02)
1445
1446 #define MPI_SCSIPORTPAGE0_CAP_IU                        (0x00000001)
1447 #define MPI_SCSIPORTPAGE0_CAP_DT                        (0x00000002)
1448 #define MPI_SCSIPORTPAGE0_CAP_QAS                       (0x00000004)
1449 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK      (0x0000FF00)
1450 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC                    (0x00)
1451 #define MPI_SCSIPORTPAGE0_SYNC_5                        (0x32)
1452 #define MPI_SCSIPORTPAGE0_SYNC_10                       (0x19)
1453 #define MPI_SCSIPORTPAGE0_SYNC_20                       (0x0C)
1454 #define MPI_SCSIPORTPAGE0_SYNC_33_33                    (0x0B)
1455 #define MPI_SCSIPORTPAGE0_SYNC_40                       (0x0A)
1456 #define MPI_SCSIPORTPAGE0_SYNC_80                       (0x09)
1457 #define MPI_SCSIPORTPAGE0_SYNC_160                      (0x08)
1458 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN                  (0xFF)
1459
1460 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD     (8)
1461 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap)      \
1462     (  ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
1463     >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD          \
1464     )
1465 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK      (0x00FF0000)
1466 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET     (16)
1467 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap)      \
1468     (  ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
1469     >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET          \
1470     )
1471 #define MPI_SCSIPORTPAGE0_CAP_IDP                       (0x08000000)
1472 #define MPI_SCSIPORTPAGE0_CAP_WIDE                      (0x20000000)
1473 #define MPI_SCSIPORTPAGE0_CAP_AIP                       (0x80000000)
1474
1475 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK          (0x00000003)
1476 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD                (0x01)
1477 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE                 (0x02)
1478 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD                (0x03)
1479 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID         (0xFF000000)
1480 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID        (24)
1481 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID     (0xFE)
1482 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID      (0xFF)
1483
1484
1485 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1486 {
1487     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1488     U32                     Configuration;              /* 04h */
1489     U32                     OnBusTimerValue;            /* 08h */
1490     U8                      TargetConfig;               /* 0Ch */
1491     U8                      Reserved1;                  /* 0Dh */
1492     U16                     IDConfig;                   /* 0Eh */
1493 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1494   SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1495
1496 #define MPI_SCSIPORTPAGE1_PAGEVERSION                   (0x03)
1497
1498 /* Configuration values */
1499 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK         (0x000000FF)
1500 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK     (0xFFFF0000)
1501 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID    (16)
1502
1503 /* TargetConfig values */
1504 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY        (0x01)
1505 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG        (0x02)
1506
1507
1508 typedef struct _MPI_DEVICE_INFO
1509 {
1510     U8      Timeout;                                    /* 00h */
1511     U8      SyncFactor;                                 /* 01h */
1512     U16     DeviceFlags;                                /* 02h */
1513 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1514   MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1515
1516 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1517 {
1518     CONFIG_PAGE_HEADER  Header;                         /* 00h */
1519     U32                 PortFlags;                      /* 04h */
1520     U32                 PortSettings;                   /* 08h */
1521     MPI_DEVICE_INFO     DeviceSettings[16];             /* 0Ch */
1522 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1523   SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1524
1525 #define MPI_SCSIPORTPAGE2_PAGEVERSION                       (0x02)
1526
1527 /* PortFlags values */
1528 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW       (0x00000001)
1529 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET       (0x00000004)
1530 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS          (0x00000008)
1531 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE    (0x00000010)
1532
1533 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK                (0x00000060)
1534 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV                (0x00000000)
1535 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY          (0x00000020)
1536 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV                 (0x00000060)
1537
1538
1539 /* PortSettings values */
1540 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK                 (0x0000000F)
1541 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA                (0x00000030)
1542 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA             (0x00000000)
1543 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA                (0x00000010)
1544 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA                  (0x00000020)
1545 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA             (0x00000030)
1546 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA              (0x000000C0)
1547 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE                      (0x00000000)
1548 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY                 (0x00000040)
1549 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA                (0x00000080)
1550 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK            (0x00000F00)
1551 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY           (8)
1552 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS    (0x00003000)
1553 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS         (0x00000000)
1554 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS         (0x00001000)
1555 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS          (0x00003000)
1556
1557 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE          (0x0001)
1558 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE             (0x0002)
1559 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE            (0x0004)
1560 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE           (0x0008)
1561 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE               (0x0010)
1562 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE                (0x0020)
1563
1564
1565 /****************************************************************************
1566 *   SCSI Target Device Config Pages
1567 ****************************************************************************/
1568
1569 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1570 {
1571     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1572     U32                     NegotiatedParameters;       /* 04h */
1573     U32                     Information;                /* 08h */
1574 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1575   SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1576
1577 #define MPI_SCSIDEVPAGE0_PAGEVERSION                    (0x04)
1578
1579 #define MPI_SCSIDEVPAGE0_NP_IU                          (0x00000001)
1580 #define MPI_SCSIDEVPAGE0_NP_DT                          (0x00000002)
1581 #define MPI_SCSIDEVPAGE0_NP_QAS                         (0x00000004)
1582 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS                    (0x00000008)
1583 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW                     (0x00000010)
1584 #define MPI_SCSIDEVPAGE0_NP_RD_STRM                     (0x00000020)
1585 #define MPI_SCSIDEVPAGE0_NP_RTI                         (0x00000040)
1586 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN                    (0x00000080)
1587 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK        (0x0000FF00)
1588 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD           (8)
1589 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK        (0x00FF0000)
1590 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET           (16)
1591 #define MPI_SCSIDEVPAGE0_NP_IDP                         (0x08000000)
1592 #define MPI_SCSIDEVPAGE0_NP_WIDE                        (0x20000000)
1593 #define MPI_SCSIDEVPAGE0_NP_AIP                         (0x80000000)
1594
1595 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED         (0x00000001)
1596 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED             (0x00000002)
1597 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED             (0x00000004)
1598 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED              (0x00000008)
1599
1600
1601 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1602 {
1603     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1604     U32                     RequestedParameters;        /* 04h */
1605     U32                     Reserved;                   /* 08h */
1606     U32                     Configuration;              /* 0Ch */
1607 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1608   SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1609
1610 #define MPI_SCSIDEVPAGE1_PAGEVERSION                    (0x05)
1611
1612 #define MPI_SCSIDEVPAGE1_RP_IU                          (0x00000001)
1613 #define MPI_SCSIDEVPAGE1_RP_DT                          (0x00000002)
1614 #define MPI_SCSIDEVPAGE1_RP_QAS                         (0x00000004)
1615 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS                    (0x00000008)
1616 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW                     (0x00000010)
1617 #define MPI_SCSIDEVPAGE1_RP_RD_STRM                     (0x00000020)
1618 #define MPI_SCSIDEVPAGE1_RP_RTI                         (0x00000040)
1619 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN                    (0x00000080)
1620 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK        (0x0000FF00)
1621 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD       (8)
1622 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK        (0x00FF0000)
1623 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET       (16)
1624 #define MPI_SCSIDEVPAGE1_RP_IDP                         (0x08000000)
1625 #define MPI_SCSIDEVPAGE1_RP_WIDE                        (0x20000000)
1626 #define MPI_SCSIDEVPAGE1_RP_AIP                         (0x80000000)
1627
1628 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED           (0x00000002)
1629 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED           (0x00000004)
1630 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE    (0x00000008)
1631 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG             (0x00000010)
1632
1633
1634 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1635 {
1636     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1637     U32                     DomainValidation;           /* 04h */
1638     U32                     ParityPipeSelect;           /* 08h */
1639     U32                     DataPipeSelect;             /* 0Ch */
1640 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1641   SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1642
1643 #define MPI_SCSIDEVPAGE2_PAGEVERSION                    (0x01)
1644
1645 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE                  (0x00000010)
1646 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE     (0x00000020)
1647 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL              (0x00000380)
1648 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL         (0x00001C00)
1649 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL       (0x0000E000)
1650 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST                    (0x10000000)
1651 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST                    (0x20000000)
1652 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT                    (0x40000000)
1653 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT                    (0x80000000)
1654
1655 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK                   (0x00000003)
1656
1657 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK       (0x00000003)
1658 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK       (0x0000000C)
1659 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK       (0x00000030)
1660 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK       (0x000000C0)
1661 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK       (0x00000300)
1662 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK       (0x00000C00)
1663 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK       (0x00003000)
1664 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK       (0x0000C000)
1665 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK       (0x00030000)
1666 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK       (0x000C0000)
1667 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK      (0x00300000)
1668 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK      (0x00C00000)
1669 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK      (0x03000000)
1670 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK      (0x0C000000)
1671 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK      (0x30000000)
1672 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK      (0xC0000000)
1673
1674
1675 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1676 {
1677     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1678     U16                     MsgRejectCount;             /* 04h */
1679     U16                     PhaseErrorCount;            /* 06h */
1680     U16                     ParityErrorCount;           /* 08h */
1681     U16                     Reserved;                   /* 0Ah */
1682 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1683   SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1684
1685 #define MPI_SCSIDEVPAGE3_PAGEVERSION                    (0x00)
1686
1687 #define MPI_SCSIDEVPAGE3_MAX_COUNTER                    (0xFFFE)
1688 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER            (0xFFFF)
1689
1690
1691 /****************************************************************************
1692 *   FC Port Config Pages
1693 ****************************************************************************/
1694
1695 typedef struct _CONFIG_PAGE_FC_PORT_0
1696 {
1697     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1698     U32                     Flags;                      /* 04h */
1699     U8                      MPIPortNumber;              /* 08h */
1700     U8                      LinkType;                   /* 09h */
1701     U8                      PortState;                  /* 0Ah */
1702     U8                      Reserved;                   /* 0Bh */
1703     U32                     PortIdentifier;             /* 0Ch */
1704     U64                     WWNN;                       /* 10h */
1705     U64                     WWPN;                       /* 18h */
1706     U32                     SupportedServiceClass;      /* 20h */
1707     U32                     SupportedSpeeds;            /* 24h */
1708     U32                     CurrentSpeed;               /* 28h */
1709     U32                     MaxFrameSize;               /* 2Ch */
1710     U64                     FabricWWNN;                 /* 30h */
1711     U64                     FabricWWPN;                 /* 38h */
1712     U32                     DiscoveredPortsCount;       /* 40h */
1713     U32                     MaxInitiators;              /* 44h */
1714     U8                      MaxAliasesSupported;        /* 48h */
1715     U8                      MaxHardAliasesSupported;    /* 49h */
1716     U8                      NumCurrentAliases;          /* 4Ah */
1717     U8                      Reserved1;                  /* 4Bh */
1718 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1719   FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1720
1721 #define MPI_FCPORTPAGE0_PAGEVERSION                     (0x02)
1722
1723 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK                 (0x0000000F)
1724 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT             (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1725 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG             (MPI_PORTFACTS_PROTOCOL_TARGET)
1726 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN                  (MPI_PORTFACTS_PROTOCOL_LAN)
1727 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR           (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1728
1729 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED      (0x00000010)
1730 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED       (0x00000020)
1731 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID          (0x00000040)
1732
1733 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK          (0x00000F00)
1734 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT            (0x00000000)
1735 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT     (0x00000100)
1736 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP       (0x00000200)
1737 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT      (0x00000400)
1738 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP        (0x00000800)
1739
1740 #define MPI_FCPORTPAGE0_LTYPE_RESERVED                  (0x00)
1741 #define MPI_FCPORTPAGE0_LTYPE_OTHER                     (0x01)
1742 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN                   (0x02)
1743 #define MPI_FCPORTPAGE0_LTYPE_COPPER                    (0x03)
1744 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300               (0x04)
1745 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500               (0x05)
1746 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI            (0x06)
1747 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI              (0x07)
1748 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI            (0x08)
1749 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI              (0x09)
1750 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE           (0x0A)
1751 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE          (0x0B)
1752 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE          (0x0C)
1753 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE            (0x0D)
1754 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE            (0x0E)
1755 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE            (0x0F)
1756
1757 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN               (0x01)      /*(SNIA)HBA_PORTSTATE_UNKNOWN       1 Unknown */
1758 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE                (0x02)      /*(SNIA)HBA_PORTSTATE_ONLINE        2 Operational */
1759 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE               (0x03)      /*(SNIA)HBA_PORTSTATE_OFFLINE       3 User Offline */
1760 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED              (0x04)      /*(SNIA)HBA_PORTSTATE_BYPASSED      4 Bypassed */
1761 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST              (0x05)      /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS   5 In diagnostics mode */
1762 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN              (0x06)      /*(SNIA)HBA_PORTSTATE_LINKDOWN      6 Link Down */
1763 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR                 (0x07)      /*(SNIA)HBA_PORTSTATE_ERROR         7 Port Error */
1764 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK              (0x08)      /*(SNIA)HBA_PORTSTATE_LOOPBACK      8 Loopback */
1765
1766 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1                 (0x00000001)
1767 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2                 (0x00000002)
1768 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3                 (0x00000004)
1769
1770 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN            (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0   Unknown - transceiver incapable of reporting */
1771 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED             (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT   1   1 GBit/sec */
1772 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED             (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT   2   2 GBit/sec */
1773 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED            (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT  4  10 GBit/sec */
1774 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED             (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT   8   4 GBit/sec */
1775
1776 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN            MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1777 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT             MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1778 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT             MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1779 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT            MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1780 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT             MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1781 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED    (0x00008000)        /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1782
1783
1784 typedef struct _CONFIG_PAGE_FC_PORT_1
1785 {
1786     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1787     U32                     Flags;                      /* 04h */
1788     U64                     NoSEEPROMWWNN;              /* 08h */
1789     U64                     NoSEEPROMWWPN;              /* 10h */
1790     U8                      HardALPA;                   /* 18h */
1791     U8                      LinkConfig;                 /* 19h */
1792     U8                      TopologyConfig;             /* 1Ah */
1793     U8                      AltConnector;               /* 1Bh */
1794     U8                      NumRequestedAliases;        /* 1Ch */
1795     U8                      RR_TOV;                     /* 1Dh */
1796     U8                      InitiatorDeviceTimeout;     /* 1Eh */
1797     U8                      InitiatorIoPendTimeout;     /* 1Fh */
1798 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1799   FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1800
1801 #define MPI_FCPORTPAGE1_PAGEVERSION                     (0x06)
1802
1803 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN         (0x08000000)
1804 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY     (0x04000000)
1805 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS  (0x02000000)
1806 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS     (0x01000000)
1807 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID          (0x00800000)
1808 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE              (0x00400000)
1809 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK        (0x00200000)
1810 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE   (0x00000080)
1811 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS         (0x00000070)
1812 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG         (0x00000008)
1813 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO             (0x00000004)
1814 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS           (0x00000002)
1815 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID               (0x00000001)
1816 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN               (0x00000000)
1817
1818 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK                 (0xF0000000)
1819 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT                (28)
1820 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT             ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1821 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG             ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1822 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN                  ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1823 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR           ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1824
1825 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS         (0x00000000)
1826 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS   (0x00000010)
1827 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS        (0x00000030)
1828 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS          (0x00000050)
1829
1830 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED              (0xFF)
1831
1832 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK              (0x0F)
1833 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG              (0x00)
1834 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG              (0x01)
1835 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG              (0x02)
1836 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG             (0x03)
1837 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO              (0x0F)
1838
1839 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK                   (0x0F)
1840 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT                 (0x01)
1841 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT                  (0x02)
1842 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO                   (0x0F)
1843
1844 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN                (0x00)
1845
1846 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK      (0x7F)
1847 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16           (0x80)
1848
1849
1850 typedef struct _CONFIG_PAGE_FC_PORT_2
1851 {
1852     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1853     U8                      NumberActive;               /* 04h */
1854     U8                      ALPA[127];                  /* 05h */
1855 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1856   FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1857
1858 #define MPI_FCPORTPAGE2_PAGEVERSION                     (0x01)
1859
1860
1861 typedef struct _WWN_FORMAT
1862 {
1863     U64                     WWNN;                       /* 00h */
1864     U64                     WWPN;                       /* 08h */
1865 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1866   WWNFormat, MPI_POINTER pWWNFormat;
1867
1868 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1869 {
1870     WWN_FORMAT              WWN;
1871     U32                     Did;
1872 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1873   PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1874
1875 typedef struct _FC_PORT_PERSISTENT
1876 {
1877     FC_PORT_PERSISTENT_PHYSICAL_ID  PhysicalIdentifier; /* 00h */
1878     U8                              TargetID;           /* 10h */
1879     U8                              Bus;                /* 11h */
1880     U16                             Flags;              /* 12h */
1881 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1882   PersistentData_t, MPI_POINTER pPersistentData_t;
1883
1884 #define MPI_PERSISTENT_FLAGS_SHIFT                      (16)
1885 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID                (0x0001)
1886 #define MPI_PERSISTENT_FLAGS_SCAN_ID                    (0x0002)
1887 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS                  (0x0004)
1888 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE                (0x0008)
1889 #define MPI_PERSISTENT_FLAGS_BY_DID                     (0x0080)
1890
1891 /*
1892  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1893  * one and check Header.PageLength at runtime.
1894  */
1895 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1896 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX        (1)
1897 #endif
1898
1899 typedef struct _CONFIG_PAGE_FC_PORT_3
1900 {
1901     CONFIG_PAGE_HEADER      Header;                                 /* 00h */
1902     FC_PORT_PERSISTENT      Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX];    /* 04h */
1903 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1904   FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1905
1906 #define MPI_FCPORTPAGE3_PAGEVERSION                     (0x01)
1907
1908
1909 typedef struct _CONFIG_PAGE_FC_PORT_4
1910 {
1911     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1912     U32                     PortFlags;                  /* 04h */
1913     U32                     PortSettings;               /* 08h */
1914 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1915   FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1916
1917 #define MPI_FCPORTPAGE4_PAGEVERSION                     (0x00)
1918
1919 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS        (0x00000008)
1920
1921 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA              (0x00000030)
1922 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA           (0x00000000)
1923 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA              (0x00000010)
1924 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA                (0x00000020)
1925 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA           (0x00000030)
1926 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA            (0x000000C0)
1927 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK          (0x00000F00)
1928
1929
1930 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1931 {
1932     U8      Flags;                                      /* 00h */
1933     U8      AliasAlpa;                                  /* 01h */
1934     U16     Reserved;                                   /* 02h */
1935     U64     AliasWWNN;                                  /* 04h */
1936     U64     AliasWWPN;                                  /* 0Ch */
1937 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1938   MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1939   FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1940
1941 typedef struct _CONFIG_PAGE_FC_PORT_5
1942 {
1943     CONFIG_PAGE_HEADER                  Header;         /* 00h */
1944     CONFIG_PAGE_FC_PORT_5_ALIAS_INFO    AliasInfo;      /* 04h */
1945 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1946   FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1947
1948 #define MPI_FCPORTPAGE5_PAGEVERSION                     (0x02)
1949
1950 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED             (0x01)
1951 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA                 (0x02)
1952 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN                 (0x04)
1953 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN                 (0x08)
1954 #define MPI_FCPORTPAGE5_FLAGS_DISABLE                   (0x10)
1955
1956 typedef struct _CONFIG_PAGE_FC_PORT_6
1957 {
1958     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1959     U32                     Reserved;                   /* 04h */
1960     U64                     TimeSinceReset;             /* 08h */
1961     U64                     TxFrames;                   /* 10h */
1962     U64                     RxFrames;                   /* 18h */
1963     U64                     TxWords;                    /* 20h */
1964     U64                     RxWords;                    /* 28h */
1965     U64                     LipCount;                   /* 30h */
1966     U64                     NosCount;                   /* 38h */
1967     U64                     ErrorFrames;                /* 40h */
1968     U64                     DumpedFrames;               /* 48h */
1969     U64                     LinkFailureCount;           /* 50h */
1970     U64                     LossOfSyncCount;            /* 58h */
1971     U64                     LossOfSignalCount;          /* 60h */
1972     U64                     PrimativeSeqErrCount;       /* 68h */
1973     U64                     InvalidTxWordCount;         /* 70h */
1974     U64                     InvalidCrcCount;            /* 78h */
1975     U64                     FcpInitiatorIoCount;        /* 80h */
1976 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1977   FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1978
1979 #define MPI_FCPORTPAGE6_PAGEVERSION                     (0x00)
1980
1981
1982 typedef struct _CONFIG_PAGE_FC_PORT_7
1983 {
1984     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1985     U32                     Reserved;                   /* 04h */
1986     U8                      PortSymbolicName[256];      /* 08h */
1987 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1988   FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1989
1990 #define MPI_FCPORTPAGE7_PAGEVERSION                     (0x00)
1991
1992
1993 typedef struct _CONFIG_PAGE_FC_PORT_8
1994 {
1995     CONFIG_PAGE_HEADER      Header;                     /* 00h */
1996     U32                     BitVector[8];               /* 04h */
1997 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1998   FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1999
2000 #define MPI_FCPORTPAGE8_PAGEVERSION                     (0x00)
2001
2002
2003 typedef struct _CONFIG_PAGE_FC_PORT_9
2004 {
2005     CONFIG_PAGE_HEADER      Header;                     /* 00h */
2006     U32                     Reserved;                   /* 04h */
2007     U64                     GlobalWWPN;                 /* 08h */
2008     U64                     GlobalWWNN;                 /* 10h */
2009     U32                     UnitType;                   /* 18h */
2010     U32                     PhysicalPortNumber;         /* 1Ch */
2011     U32                     NumAttachedNodes;           /* 20h */
2012     U16                     IPVersion;                  /* 24h */
2013     U16                     UDPPortNumber;              /* 26h */
2014     U8                      IPAddress[16];              /* 28h */
2015     U16                     Reserved1;                  /* 38h */
2016     U16                     TopologyDiscoveryFlags;     /* 3Ah */
2017 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
2018   FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
2019
2020 #define MPI_FCPORTPAGE9_PAGEVERSION                     (0x00)
2021
2022
2023 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
2024 {
2025     U8                      Id;                         /* 10h */
2026     U8                      ExtId;                      /* 11h */
2027     U8                      Connector;                  /* 12h */
2028     U8                      Transceiver[8];             /* 13h */
2029     U8                      Encoding;                   /* 1Bh */
2030     U8                      BitRate_100mbs;             /* 1Ch */
2031     U8                      Reserved1;                  /* 1Dh */
2032     U8                      Length9u_km;                /* 1Eh */
2033     U8                      Length9u_100m;              /* 1Fh */
2034     U8                      Length50u_10m;              /* 20h */
2035     U8                      Length62p5u_10m;            /* 21h */
2036     U8                      LengthCopper_m;             /* 22h */
2037     U8                      Reseverved2;                /* 22h */
2038     U8                      VendorName[16];             /* 24h */
2039     U8                      Reserved3;                  /* 34h */
2040     U8                      VendorOUI[3];               /* 35h */
2041     U8                      VendorPN[16];               /* 38h */
2042     U8                      VendorRev[4];               /* 48h */
2043     U16                     Wavelength;                 /* 4Ch */
2044     U8                      Reserved4;                  /* 4Eh */
2045     U8                      CC_BASE;                    /* 4Fh */
2046 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2047   MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2048   FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
2049
2050 #define MPI_FCPORT10_BASE_ID_UNKNOWN        (0x00)
2051 #define MPI_FCPORT10_BASE_ID_GBIC           (0x01)
2052 #define MPI_FCPORT10_BASE_ID_FIXED          (0x02)
2053 #define MPI_FCPORT10_BASE_ID_SFP            (0x03)
2054 #define MPI_FCPORT10_BASE_ID_SFP_MIN        (0x04)
2055 #define MPI_FCPORT10_BASE_ID_SFP_MAX        (0x7F)
2056 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
2057
2058 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN     (0x00)
2059 #define MPI_FCPORT10_BASE_EXTID_MODDEF1     (0x01)
2060 #define MPI_FCPORT10_BASE_EXTID_MODDEF2     (0x02)
2061 #define MPI_FCPORT10_BASE_EXTID_MODDEF3     (0x03)
2062 #define MPI_FCPORT10_BASE_EXTID_SEEPROM     (0x04)
2063 #define MPI_FCPORT10_BASE_EXTID_MODDEF5     (0x05)
2064 #define MPI_FCPORT10_BASE_EXTID_MODDEF6     (0x06)
2065 #define MPI_FCPORT10_BASE_EXTID_MODDEF7     (0x07)
2066 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
2067
2068 #define MPI_FCPORT10_BASE_CONN_UNKNOWN      (0x00)
2069 #define MPI_FCPORT10_BASE_CONN_SC           (0x01)
2070 #define MPI_FCPORT10_BASE_CONN_COPPER1      (0x02)
2071 #define MPI_FCPORT10_BASE_CONN_COPPER2      (0x03)
2072 #define MPI_FCPORT10_BASE_CONN_BNC_TNC      (0x04)
2073 #define MPI_FCPORT10_BASE_CONN_COAXIAL      (0x05)
2074 #define MPI_FCPORT10_BASE_CONN_FIBERJACK    (0x06)
2075 #define MPI_FCPORT10_BASE_CONN_LC           (0x07)
2076 #define MPI_FCPORT10_BASE_CONN_MT_RJ        (0x08)
2077 #define MPI_FCPORT10_BASE_CONN_MU           (0x09)
2078 #define MPI_FCPORT10_BASE_CONN_SG           (0x0A)
2079 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT     (0x0B)
2080 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN     (0x0C)
2081 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX     (0x1F)
2082 #define MPI_FCPORT10_BASE_CONN_HSSDC_II     (0x20)
2083 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT     (0x21)
2084 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN     (0x22)
2085 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX     (0x7F)
2086 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK  (0x80)
2087
2088 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC     (0x00)
2089 #define MPI_FCPORT10_BASE_ENCODE_8B10B      (0x01)
2090 #define MPI_FCPORT10_BASE_ENCODE_4B5B       (0x02)
2091 #define MPI_FCPORT10_BASE_ENCODE_NRZ        (0x03)
2092 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
2093
2094
2095 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
2096 {
2097     U8                      Options[2];                 /* 50h */
2098     U8                      BitRateMax;                 /* 52h */
2099     U8                      BitRateMin;                 /* 53h */
2100     U8                      VendorSN[16];               /* 54h */
2101     U8                      DateCode[8];                /* 64h */
2102     U8                      DiagMonitoringType;         /* 6Ch */
2103     U8                      EnhancedOptions;            /* 6Dh */
2104     U8                      SFF8472Compliance;          /* 6Eh */
2105     U8                      CC_EXT;                     /* 6Fh */
2106 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2107   MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2108   FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
2109
2110 #define MPI_FCPORT10_EXT_OPTION1_RATESEL    (0x20)
2111 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
2112 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT   (0x08)
2113 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
2114 #define MPI_FCPORT10_EXT_OPTION1_LOS        (0x02)
2115
2116
2117 typedef struct _CONFIG_PAGE_FC_PORT_10
2118 {
2119     CONFIG_PAGE_HEADER                          Header;             /* 00h */
2120     U8                                          Flags;              /* 04h */
2121     U8                                          Reserved1;          /* 05h */
2122     U16                                         Reserved2;          /* 06h */
2123     U32                                         HwConfig1;          /* 08h */
2124     U32                                         HwConfig2;          /* 0Ch */
2125     CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA        Base;               /* 10h */
2126     CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA    Extended;           /* 50h */
2127     U8                                          VendorSpecific[32]; /* 70h */
2128 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
2129   FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
2130
2131 #define MPI_FCPORTPAGE10_PAGEVERSION                    (0x01)
2132
2133 /* standard MODDEF pin definitions (from GBIC spec.) */
2134 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK              (0x00000007)
2135 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2                  (0x00000001)
2136 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1                  (0x00000002)
2137 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0                  (0x00000004)
2138 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC            (0x00000007)
2139 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX       (0x00000006)
2140 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER            (0x00000005)
2141 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW        (0x00000004)
2142 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM           (0x00000003)
2143 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL        (0x00000002)
2144 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW    (0x00000001)
2145 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW    (0x00000000)
2146
2147 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK               (0x00000010)
2148 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK                (0x00000020)
2149
2150
2151 /****************************************************************************
2152 *   FC Device Config Pages
2153 ****************************************************************************/
2154
2155 typedef struct _CONFIG_PAGE_FC_DEVICE_0
2156 {
2157     CONFIG_PAGE_HEADER      Header;                     /* 00h */
2158     U64                     WWNN;                       /* 04h */
2159     U64                     WWPN;                       /* 0Ch */
2160     U32                     PortIdentifier;             /* 14h */
2161     U8                      Protocol;                   /* 18h */
2162     U8                      Flags;                      /* 19h */
2163     U16                     BBCredit;                   /* 1Ah */
2164     U16                     MaxRxFrameSize;             /* 1Ch */
2165     U8                      ADISCHardALPA;              /* 1Eh */
2166     U8                      PortNumber;                 /* 1Fh */
2167     U8                      FcPhLowestVersion;          /* 20h */
2168     U8                      FcPhHighestVersion;         /* 21h */
2169     U8                      CurrentTargetID;            /* 22h */
2170     U8                      CurrentBus;                 /* 23h */
2171 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
2172   FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
2173
2174 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION                 (0x03)
2175
2176 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID    (0x01)
2177 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID         (0x02)
2178 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID          (0x04)
2179
2180 #define MPI_FC_DEVICE_PAGE0_PROT_IP                     (0x01)
2181 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET             (0x02)
2182 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR          (0x04)
2183 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY              (0x08)
2184
2185 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK      (MPI_FC_DEVICE_PGAD_PORT_MASK)
2186 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK      (MPI_FC_DEVICE_PGAD_FORM_MASK)
2187 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID  (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
2188 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID   (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
2189 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK       (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
2190 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK       (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
2191 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT      (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
2192 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK       (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2193
2194 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN   (0xFF)
2195
2196 /****************************************************************************
2197 *   RAID Volume Config Pages
2198 ****************************************************************************/
2199
2200 typedef struct _RAID_VOL0_PHYS_DISK
2201 {
2202     U16                         Reserved;               /* 00h */
2203     U8                          PhysDiskMap;            /* 02h */
2204     U8                          PhysDiskNum;            /* 03h */
2205 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2206   RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2207
2208 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY                   (0x01)
2209 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY                 (0x02)
2210
2211 typedef struct _RAID_VOL0_STATUS
2212 {
2213     U8                          Flags;                  /* 00h */
2214     U8                          State;                  /* 01h */
2215     U16                         Reserved;               /* 02h */
2216 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2217   RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2218
2219 /* RAID Volume Page 0 VolumeStatus defines */
2220 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED                (0x01)
2221 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED               (0x02)
2222 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS     (0x04)
2223 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE        (0x08)
2224 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL   (0x10)
2225
2226 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL               (0x00)
2227 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED              (0x01)
2228 #define MPI_RAIDVOL0_STATUS_STATE_FAILED                (0x02)
2229 #define MPI_RAIDVOL0_STATUS_STATE_MISSING               (0x03)
2230
2231 typedef struct _RAID_VOL0_SETTINGS
2232 {
2233     U16                         Settings;       /* 00h */
2234     U8                          HotSparePool;   /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2235     U8                          Reserved;       /* 02h */
2236 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2237   RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2238
2239 /* RAID Volume Page 0 VolumeSettings defines */
2240 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE       (0x0001)
2241 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART           (0x0002)
2242 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE             (0x0004)
2243 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC            (0x0008)
2244 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102   (0x0020) /* obsolete */
2245
2246 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE         (0x00C0)
2247 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE         (0x0000)
2248 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE        (0x0040)
2249
2250 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX      (0x0010)
2251 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS               (0x8000)
2252
2253 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2254 #define MPI_RAID_HOT_SPARE_POOL_0                       (0x01)
2255 #define MPI_RAID_HOT_SPARE_POOL_1                       (0x02)
2256 #define MPI_RAID_HOT_SPARE_POOL_2                       (0x04)
2257 #define MPI_RAID_HOT_SPARE_POOL_3                       (0x08)
2258 #define MPI_RAID_HOT_SPARE_POOL_4                       (0x10)
2259 #define MPI_RAID_HOT_SPARE_POOL_5                       (0x20)
2260 #define MPI_RAID_HOT_SPARE_POOL_6                       (0x40)
2261 #define MPI_RAID_HOT_SPARE_POOL_7                       (0x80)
2262
2263 /*
2264  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2265  * one and check Header.PageLength at runtime.
2266  */
2267 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2268 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX        (1)
2269 #endif
2270
2271 typedef struct _CONFIG_PAGE_RAID_VOL_0
2272 {
2273     CONFIG_PAGE_HEADER      Header;         /* 00h */
2274     U8                      VolumeID;       /* 04h */
2275     U8                      VolumeBus;      /* 05h */
2276     U8                      VolumeIOC;      /* 06h */
2277     U8                      VolumeType;     /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2278     RAID_VOL0_STATUS        VolumeStatus;   /* 08h */
2279     RAID_VOL0_SETTINGS      VolumeSettings; /* 0Ch */
2280     U32                     MaxLBA;         /* 10h */
2281     U32                     MaxLBAHigh;     /* 14h */
2282     U32                     StripeSize;     /* 18h */
2283     U32                     Reserved2;      /* 1Ch */
2284     U32                     Reserved3;      /* 20h */
2285     U8                      NumPhysDisks;   /* 24h */
2286     U8                      DataScrubRate;  /* 25h */
2287     U8                      ResyncRate;     /* 26h */
2288     U8                      InactiveStatus; /* 27h */
2289     RAID_VOL0_PHYS_DISK     PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2290 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2291   RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2292
2293 #define MPI_RAIDVOLPAGE0_PAGEVERSION                    (0x07)
2294
2295 /* values for RAID Volume Page 0 InactiveStatus field */
2296 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE               (0x00)
2297 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE        (0x01)
2298 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE        (0x02)
2299 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2300 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE          (0x04)
2301 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2302 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED             (0x06)
2303
2304
2305 typedef struct _CONFIG_PAGE_RAID_VOL_1
2306 {
2307     CONFIG_PAGE_HEADER      Header;         /* 00h */
2308     U8                      VolumeID;       /* 04h */
2309     U8                      VolumeBus;      /* 05h */
2310     U8                      VolumeIOC;      /* 06h */
2311     U8                      Reserved0;      /* 07h */
2312     U8                      GUID[24];       /* 08h */
2313     U8                      Name[32];       /* 20h */
2314     U64                     WWID;           /* 40h */
2315     U32                     Reserved1;      /* 48h */
2316     U32                     Reserved2;      /* 4Ch */
2317 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2318   RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2319
2320 #define MPI_RAIDVOLPAGE1_PAGEVERSION                    (0x01)
2321
2322
2323 /****************************************************************************
2324 *   RAID Physical Disk Config Pages
2325 ****************************************************************************/
2326
2327 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2328 {
2329     U8                      ErrorCdbByte;               /* 00h */
2330     U8                      ErrorSenseKey;              /* 01h */
2331     U16                     Reserved;                   /* 02h */
2332     U16                     ErrorCount;                 /* 04h */
2333     U8                      ErrorASC;                   /* 06h */
2334     U8                      ErrorASCQ;                  /* 07h */
2335     U16                     SmartCount;                 /* 08h */
2336     U8                      SmartASC;                   /* 0Ah */
2337     U8                      SmartASCQ;                  /* 0Bh */
2338 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2339   RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2340
2341 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2342 {
2343     U8                          VendorID[8];            /* 00h */
2344     U8                          ProductID[16];          /* 08h */
2345     U8                          ProductRevLevel[4];     /* 18h */
2346     U8                          Info[32];               /* 1Ch */
2347 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2348   RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2349
2350 typedef struct _RAID_PHYS_DISK0_SETTINGS
2351 {
2352     U8              SepID;              /* 00h */
2353     U8              SepBus;             /* 01h */
2354     U8              HotSparePool;       /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2355     U8              PhysDiskSettings;   /* 03h */
2356 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2357   RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2358
2359 typedef struct _RAID_PHYS_DISK0_STATUS
2360 {
2361     U8                              Flags;              /* 00h */
2362     U8                              State;              /* 01h */
2363     U16                             Reserved;           /* 02h */
2364 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2365   RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2366
2367 /* RAID Physical Disk PhysDiskStatus flags */
2368
2369 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC           (0x01)
2370 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED              (0x02)
2371 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME       (0x04)
2372 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS      (0x00)
2373 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS  (0x08)
2374
2375 #define MPI_PHYSDISK0_STATUS_ONLINE                     (0x00)
2376 #define MPI_PHYSDISK0_STATUS_MISSING                    (0x01)
2377 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE             (0x02)
2378 #define MPI_PHYSDISK0_STATUS_FAILED                     (0x03)
2379 #define MPI_PHYSDISK0_STATUS_INITIALIZING               (0x04)
2380 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED          (0x05)
2381 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED           (0x06)
2382 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE              (0xFF)
2383
2384 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2385 {
2386     CONFIG_PAGE_HEADER              Header;             /* 00h */
2387     U8                              PhysDiskID;         /* 04h */
2388     U8                              PhysDiskBus;        /* 05h */
2389     U8                              PhysDiskIOC;        /* 06h */
2390     U8                              PhysDiskNum;        /* 07h */
2391     RAID_PHYS_DISK0_SETTINGS        PhysDiskSettings;   /* 08h */
2392     U32                             Reserved1;          /* 0Ch */
2393     U8                              ExtDiskIdentifier[8]; /* 10h */
2394     U8                              DiskIdentifier[16]; /* 18h */
2395     RAID_PHYS_DISK0_INQUIRY_DATA    InquiryData;        /* 28h */
2396     RAID_PHYS_DISK0_STATUS          PhysDiskStatus;     /* 64h */
2397     U32                             MaxLBA;             /* 68h */
2398     RAID_PHYS_DISK0_ERROR_DATA      ErrorData;          /* 6Ch */
2399 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2400   RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2401
2402 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION           (0x02)
2403
2404
2405 typedef struct _RAID_PHYS_DISK1_PATH
2406 {
2407     U8                              PhysDiskID;         /* 00h */
2408     U8                              PhysDiskBus;        /* 01h */
2409     U16                             Reserved1;          /* 02h */
2410     U64                             WWID;               /* 04h */
2411     U64                             OwnerWWID;          /* 0Ch */
2412     U8                              OwnerIdentifier;    /* 14h */
2413     U8                              Reserved2;          /* 15h */
2414     U16                             Flags;              /* 16h */
2415 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2416   RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2417
2418 /* RAID Physical Disk Page 1 Flags field defines */
2419 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN          (0x0002)
2420 #define MPI_RAID_PHYSDISK1_FLAG_INVALID         (0x0001)
2421
2422 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2423 {
2424     CONFIG_PAGE_HEADER              Header;             /* 00h */
2425     U8                              NumPhysDiskPaths;   /* 04h */
2426     U8                              PhysDiskNum;        /* 05h */
2427     U16                             Reserved2;          /* 06h */
2428     U32                             Reserved1;          /* 08h */
2429     RAID_PHYS_DISK1_PATH            Path[1];            /* 0Ch */
2430 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2431   RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2432
2433 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION       (0x00)
2434
2435
2436 /****************************************************************************
2437 *   LAN Config Pages
2438 ****************************************************************************/
2439
2440 typedef struct _CONFIG_PAGE_LAN_0
2441 {
2442     ConfigPageHeader_t      Header;                     /* 00h */
2443     U16                     TxRxModes;                  /* 04h */
2444     U16                     Reserved;                   /* 06h */
2445     U32                     PacketPrePad;               /* 08h */
2446 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2447   LANPage0_t, MPI_POINTER pLANPage0_t;
2448
2449 #define MPI_LAN_PAGE0_PAGEVERSION                       (0x01)
2450
2451 #define MPI_LAN_PAGE0_RETURN_LOOPBACK                   (0x0000)
2452 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK                 (0x0001)
2453 #define MPI_LAN_PAGE0_LOOPBACK_MASK                     (0x0001)
2454
2455 typedef struct _CONFIG_PAGE_LAN_1
2456 {
2457     ConfigPageHeader_t      Header;                     /* 00h */
2458     U16                     Reserved;                   /* 04h */
2459     U8                      CurrentDeviceState;         /* 06h */
2460     U8                      Reserved1;                  /* 07h */
2461     U32                     MinPacketSize;              /* 08h */
2462     U32                     MaxPacketSize;              /* 0Ch */
2463     U32                     HardwareAddressLow;         /* 10h */
2464     U32                     HardwareAddressHigh;        /* 14h */
2465     U32                     MaxWireSpeedLow;            /* 18h */
2466     U32                     MaxWireSpeedHigh;           /* 1Ch */
2467     U32                     BucketsRemaining;           /* 20h */
2468     U32                     MaxReplySize;               /* 24h */
2469     U32                     NegWireSpeedLow;            /* 28h */
2470     U32                     NegWireSpeedHigh;           /* 2Ch */
2471 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2472   LANPage1_t, MPI_POINTER pLANPage1_t;
2473
2474 #define MPI_LAN_PAGE1_PAGEVERSION                       (0x03)
2475
2476 #define MPI_LAN_PAGE1_DEV_STATE_RESET                   (0x00)
2477 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL             (0x01)
2478
2479
2480 /****************************************************************************
2481 *   Inband Config Pages
2482 ****************************************************************************/
2483
2484 typedef struct _CONFIG_PAGE_INBAND_0
2485 {
2486     CONFIG_PAGE_HEADER      Header;                     /* 00h */
2487     MPI_VERSION_FORMAT      InbandVersion;              /* 04h */
2488     U16                     MaximumBuffers;             /* 08h */
2489     U16                     Reserved1;                  /* 0Ah */
2490 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2491   InbandPage0_t, MPI_POINTER pInbandPage0_t;
2492
2493 #define MPI_INBAND_PAGEVERSION          (0x00)
2494
2495
2496
2497 /****************************************************************************
2498 *   SAS IO Unit Config Pages
2499 ****************************************************************************/
2500
2501 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2502 {
2503     U8          Port;                   /* 00h */
2504     U8          PortFlags;              /* 01h */
2505     U8          PhyFlags;               /* 02h */
2506     U8          NegotiatedLinkRate;     /* 03h */
2507     U32         ControllerPhyDeviceInfo;/* 04h */
2508     U16         AttachedDeviceHandle;   /* 08h */
2509     U16         ControllerDevHandle;    /* 0Ah */
2510     U32         DiscoveryStatus;        /* 0Ch */
2511 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2512   SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2513
2514 /*
2515  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2516  * one and check Header.PageLength at runtime.
2517  */
2518 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2519 #define MPI_SAS_IOUNIT0_PHY_MAX         (1)
2520 #endif
2521
2522 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2523 {
2524     CONFIG_EXTENDED_PAGE_HEADER     Header;                             /* 00h */
2525     U16                             NvdataVersionDefault;               /* 08h */
2526     U16                             NvdataVersionPersistent;            /* 0Ah */
2527     U8                              NumPhys;                            /* 0Ch */
2528     U8                              Reserved2;                          /* 0Dh */
2529     U16                             Reserved3;                          /* 0Eh */
2530     MPI_SAS_IO_UNIT0_PHY_DATA       PhyData[MPI_SAS_IOUNIT0_PHY_MAX];   /* 10h */
2531 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2532   SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2533
2534 #define MPI_SASIOUNITPAGE0_PAGEVERSION      (0x04)
2535
2536 /* values for SAS IO Unit Page 0 PortFlags */
2537 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS    (0x08)
2538 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM         (0x00)
2539 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM         (0x04)
2540 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG         (0x01)
2541
2542 /* values for SAS IO Unit Page 0 PhyFlags */
2543 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED              (0x04)
2544 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT                 (0x02)
2545 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT                 (0x01)
2546
2547 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2548 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN                        (0x00)
2549 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED                   (0x01)
2550 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION       (0x02)
2551 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE              (0x03)
2552 #define MPI_SAS_IOUNIT0_RATE_1_5                            (0x08)
2553 #define MPI_SAS_IOUNIT0_RATE_3_0                            (0x09)
2554
2555 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2556
2557 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2558 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2559 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2560 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2561 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR                     (0x00000008)
2562 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2563 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2564 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2565 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2566 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2567 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2568 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK                       (0x00000400)
2569 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2570 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS                 (0x00001000)
2571 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2572
2573
2574 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2575 {
2576     U8          Port;                       /* 00h */
2577     U8          PortFlags;                  /* 01h */
2578     U8          PhyFlags;                   /* 02h */
2579     U8          MaxMinLinkRate;             /* 03h */
2580     U32         ControllerPhyDeviceInfo;    /* 04h */
2581     U16         MaxTargetPortConnectTime;   /* 08h */
2582     U16         Reserved1;                  /* 0Ah */
2583 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2584   SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2585
2586 /*
2587  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2588  * one and check Header.PageLength at runtime.
2589  */
2590 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2591 #define MPI_SAS_IOUNIT1_PHY_MAX         (1)
2592 #endif
2593
2594 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2595 {
2596     CONFIG_EXTENDED_PAGE_HEADER Header;                             /* 00h */
2597     U16                         ControlFlags;                       /* 08h */
2598     U16                         MaxNumSATATargets;                  /* 0Ah */
2599     U16                         AdditionalControlFlags;             /* 0Ch */
2600     U16                         Reserved1;                          /* 0Eh */
2601     U8                          NumPhys;                            /* 10h */
2602     U8                          SATAMaxQDepth;                      /* 11h */
2603     U8                          ReportDeviceMissingDelay;           /* 12h */
2604     U8                          IODeviceMissingDelay;               /* 13h */
2605     MPI_SAS_IO_UNIT1_PHY_DATA   PhyData[MPI_SAS_IOUNIT1_PHY_MAX];   /* 14h */
2606 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2607   SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2608
2609 #define MPI_SASIOUNITPAGE1_PAGEVERSION      (0x07)
2610
2611 /* values for SAS IO Unit Page 1 ControlFlags */
2612 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST            (0x8000)
2613 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX                (0x4000)
2614 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX                (0x2000)
2615 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE            (0x1000)
2616 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH            (0x0800)
2617
2618 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT            (0x0600)
2619 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT           (9)
2620 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH            (0x00)
2621 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT             (0x01)
2622 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT            (0x02)
2623
2624 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT          (0x0100)
2625 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED     (0x0080)
2626 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED         (0x0040)
2627 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED           (0x0020)
2628 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED           (0x0010)
2629 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH       (0x0008)
2630 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL         (0x0004)
2631 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY         (0x0002)
2632 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION           (0x0001)
2633
2634 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2635 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2636 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2637 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT    (0x0020)
2638 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2639 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2640 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2641 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2642 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2643
2644 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2645 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK         (0x7F)
2646 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16              (0x80)
2647
2648 /* values for SAS IO Unit Page 1 PortFlags */
2649 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM         (0x00)
2650 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM         (0x04)
2651 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG         (0x01)
2652
2653 /* values for SAS IO Unit Page 0 PhyFlags */
2654 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE               (0x04)
2655 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT                 (0x02)
2656 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT                 (0x01)
2657
2658 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2659 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK                       (0xF0)
2660 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5                        (0x80)
2661 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0                        (0x90)
2662 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK                       (0x0F)
2663 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5                        (0x08)
2664 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0                        (0x09)
2665
2666 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2667
2668
2669 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2670 {
2671     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2672     U8                                  NumDevsPerEnclosure;    /* 08h */
2673     U8                                  Reserved1;              /* 09h */
2674     U16                                 Reserved2;              /* 0Ah */
2675     U16                                 MaxPersistentIDs;       /* 0Ch */
2676     U16                                 NumPersistentIDsUsed;   /* 0Eh */
2677     U8                                  Status;                 /* 10h */
2678     U8                                  Flags;                  /* 11h */
2679     U16                                 MaxNumPhysicalMappedIDs;/* 12h */
2680 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2681   SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2682
2683 #define MPI_SASIOUNITPAGE2_PAGEVERSION      (0x06)
2684
2685 /* values for SAS IO Unit Page 2 Status field */
2686 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED        (0x08)
2687 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED   (0x04)
2688 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2689 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS     (0x01)
2690
2691 /* values for SAS IO Unit Page 2 Flags field */
2692 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS   (0x01)
2693 /* Physical Mapping Modes */
2694 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE            (0x0E)
2695 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE           (1)
2696 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP                   (0x00)
2697 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP        (0x01)
2698 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP       (0x02)
2699 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP        (0x07)
2700
2701 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT         (0x10)
2702 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT              (0x20)
2703
2704
2705 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2706 {
2707     CONFIG_EXTENDED_PAGE_HEADER Header;                         /* 00h */
2708     U32                         Reserved1;                      /* 08h */
2709     U32                         MaxInvalidDwordCount;           /* 0Ch */
2710     U32                         InvalidDwordCountTime;          /* 10h */
2711     U32                         MaxRunningDisparityErrorCount;  /* 14h */
2712     U32                         RunningDisparityErrorTime;      /* 18h */
2713     U32                         MaxLossDwordSynchCount;         /* 1Ch */
2714     U32                         LossDwordSynchCountTime;        /* 20h */
2715     U32                         MaxPhyResetProblemCount;        /* 24h */
2716     U32                         PhyResetProblemTime;            /* 28h */
2717 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2718   SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2719
2720 #define MPI_SASIOUNITPAGE3_PAGEVERSION      (0x00)
2721
2722
2723 /****************************************************************************
2724 *   SAS Expander Config Pages
2725 ****************************************************************************/
2726
2727 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2728 {
2729     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2730     U8                                  PhysicalPort;           /* 08h */
2731     U8                                  Reserved1;              /* 09h */
2732     U16                                 EnclosureHandle;        /* 0Ah */
2733     U64                                 SASAddress;             /* 0Ch */
2734     U32                                 DiscoveryStatus;        /* 14h */
2735     U16                                 DevHandle;              /* 18h */
2736     U16                                 ParentDevHandle;        /* 1Ah */
2737     U16                                 ExpanderChangeCount;    /* 1Ch */
2738     U16                                 ExpanderRouteIndexes;   /* 1Eh */
2739     U8                                  NumPhys;                /* 20h */
2740     U8                                  SASLevel;               /* 21h */
2741     U8                                  Flags;                  /* 22h */
2742     U8                                  Reserved3;              /* 23h */
2743 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2744   SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2745
2746 #define MPI_SASEXPANDER0_PAGEVERSION        (0x03)
2747
2748 /* values for SAS Expander Page 0 DiscoveryStatus field */
2749 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED              (0x00000001)
2750 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE       (0x00000002)
2751 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS             (0x00000004)
2752 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR               (0x00000008)
2753 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT                (0x00000010)
2754 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES          (0x00000020)
2755 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST            (0x00000040)
2756 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED        (0x00000080)
2757 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR              (0x00000100)
2758 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK           (0x00000200)
2759 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK                 (0x00000400)
2760 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE         (0x00000800)
2761
2762 /* values for SAS Expander Page 0 Flags field */
2763 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE    (0x04)
2764 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG      (0x02)
2765 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS      (0x01)
2766
2767
2768 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2769 {
2770     CONFIG_EXTENDED_PAGE_HEADER Header;                 /* 00h */
2771     U8                          PhysicalPort;           /* 08h */
2772     U8                          Reserved1;              /* 09h */
2773     U16                         Reserved2;              /* 0Ah */
2774     U8                          NumPhys;                /* 0Ch */
2775     U8                          Phy;                    /* 0Dh */
2776     U16                         NumTableEntriesProgrammed; /* 0Eh */
2777     U8                          ProgrammedLinkRate;     /* 10h */
2778     U8                          HwLinkRate;             /* 11h */
2779     U16                         AttachedDevHandle;      /* 12h */
2780     U32                         PhyInfo;                /* 14h */
2781     U32                         AttachedDeviceInfo;     /* 18h */
2782     U16                         OwnerDevHandle;         /* 1Ch */
2783     U8                          ChangeCount;            /* 1Eh */
2784     U8                          NegotiatedLinkRate;     /* 1Fh */
2785     U8                          PhyIdentifier;          /* 20h */
2786     U8                          AttachedPhyIdentifier;  /* 21h */
2787     U8                          Reserved3;              /* 22h */
2788     U8                          DiscoveryInfo;          /* 23h */
2789     U32                         Reserved4;              /* 24h */
2790 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2791   SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2792
2793 #define MPI_SASEXPANDER1_PAGEVERSION        (0x01)
2794
2795 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2796
2797 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2798
2799 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2800
2801 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2802
2803 /* values for SAS Expander Page 1 DiscoveryInfo field */
2804 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED     (0x04)
2805 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
2806 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
2807
2808 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2809 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN              (0x00)
2810 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED         (0x01)
2811 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION   (0x02)
2812 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE    (0x03)
2813 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5                  (0x08)
2814 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0                  (0x09)
2815
2816
2817 /****************************************************************************
2818 *   SAS Device Config Pages
2819 ****************************************************************************/
2820
2821 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2822 {
2823     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2824     U16                                 Slot;                   /* 08h */
2825     U16                                 EnclosureHandle;        /* 0Ah */
2826     U64                                 SASAddress;             /* 0Ch */
2827     U16                                 ParentDevHandle;        /* 14h */
2828     U8                                  PhyNum;                 /* 16h */
2829     U8                                  AccessStatus;           /* 17h */
2830     U16                                 DevHandle;              /* 18h */
2831     U8                                  TargetID;               /* 1Ah */
2832     U8                                  Bus;                    /* 1Bh */
2833     U32                                 DeviceInfo;             /* 1Ch */
2834     U16                                 Flags;                  /* 20h */
2835     U8                                  PhysicalPort;           /* 22h */
2836     U8                                  Reserved2;              /* 23h */
2837 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2838   SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2839
2840 #define MPI_SASDEVICE0_PAGEVERSION          (0x05)
2841
2842 /* values for SAS Device Page 0 AccessStatus field */
2843 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS                   (0x00)
2844 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED            (0x01)
2845 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED      (0x02)
2846 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT   (0x03)
2847 /* specific values for SATA Init failures */
2848 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                 (0x10)
2849 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT    (0x11)
2850 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG                    (0x12)
2851 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION          (0x13)
2852 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER             (0x14)
2853 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                  (0x15)
2854 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                 (0x16)
2855 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                 (0x17)
2856 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION        (0x18)
2857 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE         (0x19)
2858 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX                     (0x1F)
2859
2860 /* values for SAS Device Page 0 Flags field */
2861 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY      (0x0400)
2862 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE              (0x0200)
2863 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE            (0x0100)
2864 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED      (0x0080)
2865 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED          (0x0040)
2866 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED            (0x0020)
2867 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED            (0x0010)
2868 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH          (0x0008)
2869 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT            (0x0004)
2870 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED                 (0x0002)
2871 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT                (0x0001)
2872
2873 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2874
2875
2876 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2877 {
2878     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2879     U32                                 Reserved1;              /* 08h */
2880     U64                                 SASAddress;             /* 0Ch */
2881     U32                                 Reserved2;              /* 14h */
2882     U16                                 DevHandle;              /* 18h */
2883     U8                                  TargetID;               /* 1Ah */
2884     U8                                  Bus;                    /* 1Bh */
2885     U8                                  InitialRegDeviceFIS[20];/* 1Ch */
2886 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2887   SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2888
2889 #define MPI_SASDEVICE1_PAGEVERSION          (0x00)
2890
2891
2892 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2893 {
2894     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2895     U64                                 PhysicalIdentifier;     /* 08h */
2896     U32                                 EnclosureMapping;       /* 10h */
2897 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2898   SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2899
2900 #define MPI_SASDEVICE2_PAGEVERSION          (0x01)
2901
2902 /* defines for SAS Device Page 2 EnclosureMapping field */
2903 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT       (0x0000000F)
2904 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT      (0)
2905 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS           (0x000007F0)
2906 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS          (4)
2907 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX         (0x001FF800)
2908 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX        (11)
2909
2910
2911 /****************************************************************************
2912 *   SAS PHY Config Pages
2913 ****************************************************************************/
2914
2915 typedef struct _CONFIG_PAGE_SAS_PHY_0
2916 {
2917     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2918     U16                                 OwnerDevHandle;         /* 08h */
2919     U16                                 Reserved1;              /* 0Ah */
2920     U64                                 SASAddress;             /* 0Ch */
2921     U16                                 AttachedDevHandle;      /* 14h */
2922     U8                                  AttachedPhyIdentifier;  /* 16h */
2923     U8                                  Reserved2;              /* 17h */
2924     U32                                 AttachedDeviceInfo;     /* 18h */
2925     U8                                  ProgrammedLinkRate;     /* 1Ch */
2926     U8                                  HwLinkRate;             /* 1Dh */
2927     U8                                  ChangeCount;            /* 1Eh */
2928     U8                                  Flags;                  /* 1Fh */
2929     U32                                 PhyInfo;                /* 20h */
2930 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2931   SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2932
2933 #define MPI_SASPHY0_PAGEVERSION             (0x01)
2934
2935 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2936 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK                        (0xF0)
2937 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE            (0x00)
2938 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5                         (0x80)
2939 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0                         (0x90)
2940 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK                        (0x0F)
2941 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE            (0x00)
2942 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5                         (0x08)
2943 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0                         (0x09)
2944
2945 /* values for SAS PHY Page 0 HwLinkRate field */
2946 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK                       (0xF0)
2947 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5                        (0x80)
2948 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0                        (0x90)
2949 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK                       (0x0F)
2950 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5                        (0x08)
2951 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0                        (0x09)
2952
2953 /* values for SAS PHY Page 0 Flags field */
2954 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC              (0x01)
2955
2956 /* values for SAS PHY Page 0 PhyInfo field */
2957 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE                   (0x00004000)
2958 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR                 (0x00002000)
2959 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY                        (0x00001000)
2960
2961 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME          (0x00000F00)
2962 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME         (8)
2963
2964 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE             (0x000000F0)
2965 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING                     (0x00000000)
2966 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING                (0x00000010)
2967 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING                      (0x00000020)
2968
2969 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE                     (0x0000000F)
2970 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE                  (0x00000000)
2971 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED                       (0x00000001)
2972 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED                 (0x00000002)
2973 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE                  (0x00000003)
2974 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5                           (0x00000008)
2975 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0                           (0x00000009)
2976
2977
2978 typedef struct _CONFIG_PAGE_SAS_PHY_1
2979 {
2980     CONFIG_EXTENDED_PAGE_HEADER Header;                     /* 00h */
2981     U32                         Reserved1;                  /* 08h */
2982     U32                         InvalidDwordCount;          /* 0Ch */
2983     U32                         RunningDisparityErrorCount; /* 10h */
2984     U32                         LossDwordSynchCount;        /* 14h */
2985     U32                         PhyResetProblemCount;       /* 18h */
2986 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2987   SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2988
2989 #define MPI_SASPHY1_PAGEVERSION             (0x00)
2990
2991
2992 /****************************************************************************
2993 *   SAS Enclosure Config Pages
2994 ****************************************************************************/
2995
2996 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2997 {
2998     CONFIG_EXTENDED_PAGE_HEADER         Header;                 /* 00h */
2999     U32                                 Reserved1;              /* 08h */
3000     U64                                 EnclosureLogicalID;     /* 0Ch */
3001     U16                                 Flags;                  /* 14h */
3002     U16                                 EnclosureHandle;        /* 16h */
3003     U16                                 NumSlots;               /* 18h */
3004     U16                                 StartSlot;              /* 1Ah */
3005     U8                                  StartTargetID;          /* 1Ch */
3006     U8                                  StartBus;               /* 1Dh */
3007     U8                                  SEPTargetID;            /* 1Eh */
3008     U8                                  SEPBus;                 /* 1Fh */
3009     U32                                 Reserved2;              /* 20h */
3010     U32                                 Reserved3;              /* 24h */
3011 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
3012   SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
3013
3014 #define MPI_SASENCLOSURE0_PAGEVERSION       (0x01)
3015
3016 /* values for SAS Enclosure Page 0 Flags field */
3017 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID       (0x0020)
3018 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID     (0x0010)
3019
3020 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK               (0x000F)
3021 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN            (0x0000)
3022 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES            (0x0001)
3023 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO          (0x0002)
3024 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO          (0x0003)
3025 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE      (0x0004)
3026 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO           (0x0005)
3027
3028
3029 /****************************************************************************
3030 *   Log Config Pages
3031 ****************************************************************************/
3032 /*
3033  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3034  * one and check NumLogEntries at runtime.
3035  */
3036 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
3037 #define MPI_LOG_0_NUM_LOG_ENTRIES        (1)
3038 #endif
3039
3040 #define MPI_LOG_0_LOG_DATA_LENGTH        (0x1C)
3041
3042 typedef struct _MPI_LOG_0_ENTRY
3043 {
3044     U32         TimeStamp;                          /* 00h */
3045     U32         Reserved1;                          /* 04h */
3046     U16         LogSequence;                        /* 08h */
3047     U16         LogEntryQualifier;                  /* 0Ah */
3048     U8          LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
3049 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
3050   MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
3051
3052 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3053 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED           (0x0000)
3054 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET         (0x0001)
3055
3056 typedef struct _CONFIG_PAGE_LOG_0
3057 {
3058     CONFIG_EXTENDED_PAGE_HEADER Header;                     /* 00h */
3059     U32                         Reserved1;                  /* 08h */
3060     U32                         Reserved2;                  /* 0Ch */
3061     U16                         NumLogEntries;              /* 10h */
3062     U16                         Reserved3;                  /* 12h */
3063     MPI_LOG_0_ENTRY             LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
3064 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
3065   LogPage0_t, MPI_POINTER pLogPage0_t;
3066
3067 #define MPI_LOG_0_PAGEVERSION               (0x01)
3068
3069
3070 #endif
3071