Merge branch 'master' of /home/sam/kernel/linux-2.6/
[linux-2.6] / arch / powerpc / platforms / cell / spufs / switch.c
1 /*
2  * spu_switch.c
3  *
4  * (C) Copyright IBM Corp. 2005
5  *
6  * Author: Mark Nutter <mnutter@us.ibm.com>
7  *
8  * Host-side part of SPU context switch sequence outlined in
9  * Synergistic Processor Element, Book IV.
10  *
11  * A fully premptive switch of an SPE is very expensive in terms
12  * of time and system resources.  SPE Book IV indicates that SPE
13  * allocation should follow a "serially reusable device" model,
14  * in which the SPE is assigned a task until it completes.  When
15  * this is not possible, this sequence may be used to premptively
16  * save, and then later (optionally) restore the context of a
17  * program executing on an SPE.
18  *
19  *
20  * This program is free software; you can redistribute it and/or modify
21  * it under the terms of the GNU General Public License as published by
22  * the Free Software Foundation; either version 2, or (at your option)
23  * any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28  * GNU General Public License for more details.
29  *
30  * You should have received a copy of the GNU General Public License
31  * along with this program; if not, write to the Free Software
32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33  */
34
35 #include <linux/module.h>
36 #include <linux/errno.h>
37 #include <linux/sched.h>
38 #include <linux/kernel.h>
39 #include <linux/mm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/smp.h>
42 #include <linux/smp_lock.h>
43 #include <linux/stddef.h>
44 #include <linux/unistd.h>
45
46 #include <asm/io.h>
47 #include <asm/spu.h>
48 #include <asm/spu_priv1.h>
49 #include <asm/spu_csa.h>
50 #include <asm/mmu_context.h>
51
52 #include "spu_save_dump.h"
53 #include "spu_restore_dump.h"
54
55 #if 0
56 #define POLL_WHILE_TRUE(_c) {                           \
57     do {                                                \
58     } while (_c);                                       \
59   }
60 #else
61 #define RELAX_SPIN_COUNT                                1000
62 #define POLL_WHILE_TRUE(_c) {                           \
63     do {                                                \
64         int _i;                                         \
65         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
66             cpu_relax();                                \
67         }                                               \
68         if (unlikely(_c)) yield();                      \
69         else break;                                     \
70     } while (_c);                                       \
71   }
72 #endif                          /* debug */
73
74 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
75
76 static inline void acquire_spu_lock(struct spu *spu)
77 {
78         /* Save, Step 1:
79          * Restore, Step 1:
80          *    Acquire SPU-specific mutual exclusion lock.
81          *    TBD.
82          */
83 }
84
85 static inline void release_spu_lock(struct spu *spu)
86 {
87         /* Restore, Step 76:
88          *    Release SPU-specific mutual exclusion lock.
89          *    TBD.
90          */
91 }
92
93 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
94 {
95         struct spu_problem __iomem *prob = spu->problem;
96         u32 isolate_state;
97
98         /* Save, Step 2:
99          * Save, Step 6:
100          *     If SPU_Status[E,L,IS] any field is '1', this
101          *     SPU is in isolate state and cannot be context
102          *     saved at this time.
103          */
104         isolate_state = SPU_STATUS_ISOLATED_STATE |
105             SPU_STATUS_ISOLATED_LOAD_STAUTUS | SPU_STATUS_ISOLATED_EXIT_STAUTUS;
106         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
107 }
108
109 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
110 {
111         /* Save, Step 3:
112          * Restore, Step 2:
113          *     Save INT_Mask_class0 in CSA.
114          *     Write INT_MASK_class0 with value of 0.
115          *     Save INT_Mask_class1 in CSA.
116          *     Write INT_MASK_class1 with value of 0.
117          *     Save INT_Mask_class2 in CSA.
118          *     Write INT_MASK_class2 with value of 0.
119          */
120         spin_lock_irq(&spu->register_lock);
121         if (csa) {
122                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
123                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
124                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
125         }
126         spu_int_mask_set(spu, 0, 0ul);
127         spu_int_mask_set(spu, 1, 0ul);
128         spu_int_mask_set(spu, 2, 0ul);
129         eieio();
130         spin_unlock_irq(&spu->register_lock);
131 }
132
133 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
134 {
135         /* Save, Step 4:
136          * Restore, Step 25.
137          *    Set a software watchdog timer, which specifies the
138          *    maximum allowable time for a context save sequence.
139          *
140          *    For present, this implementation will not set a global
141          *    watchdog timer, as virtualization & variable system load
142          *    may cause unpredictable execution times.
143          */
144 }
145
146 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
147 {
148         /* Save, Step 5:
149          * Restore, Step 3:
150          *     Inhibit user-space access (if provided) to this
151          *     SPU by unmapping the virtual pages assigned to
152          *     the SPU memory-mapped I/O (MMIO) for problem
153          *     state. TBD.
154          */
155 }
156
157 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
158 {
159         /* Save, Step 7:
160          * Restore, Step 5:
161          *     Set a software context switch pending flag.
162          */
163         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
164         mb();
165 }
166
167 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
168 {
169         struct spu_priv2 __iomem *priv2 = spu->priv2;
170
171         /* Save, Step 8:
172          *     Suspend DMA and save MFC_CNTL.
173          */
174         switch (in_be64(&priv2->mfc_control_RW) &
175                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
176         case MFC_CNTL_SUSPEND_IN_PROGRESS:
177                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
178                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
179                                  MFC_CNTL_SUSPEND_COMPLETE);
180                 /* fall through */
181         case MFC_CNTL_SUSPEND_COMPLETE:
182                 if (csa) {
183                         csa->priv2.mfc_control_RW =
184                                 in_be64(&priv2->mfc_control_RW) |
185                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
186                 }
187                 break;
188         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
189                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
190                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
191                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
192                                  MFC_CNTL_SUSPEND_COMPLETE);
193                 if (csa) {
194                         csa->priv2.mfc_control_RW =
195                                 in_be64(&priv2->mfc_control_RW) &
196                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
197                 }
198                 break;
199         }
200 }
201
202 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
203 {
204         struct spu_problem __iomem *prob = spu->problem;
205
206         /* Save, Step 9:
207          *     Save SPU_Runcntl in the CSA.  This value contains
208          *     the "Application Desired State".
209          */
210         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
211 }
212
213 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
214 {
215         /* Save, Step 10:
216          *     Save MFC_SR1 in the CSA.
217          */
218         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
219 }
220
221 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
222 {
223         struct spu_problem __iomem *prob = spu->problem;
224
225         /* Save, Step 11:
226          *     Read SPU_Status[R], and save to CSA.
227          */
228         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
229                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
230         } else {
231                 u32 stopped;
232
233                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
234                 eieio();
235                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
236                                 SPU_STATUS_RUNNING);
237                 stopped =
238                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
239                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
240                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
241                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
242                 else
243                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
244         }
245 }
246
247 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
248 {
249         struct spu_priv2 __iomem *priv2 = spu->priv2;
250
251         /* Save, Step 12:
252          *     Read MFC_CNTL[Ds].  Update saved copy of
253          *     CSA.MFC_CNTL[Ds].
254          */
255         if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
256                 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
257                 csa->suspend_time = get_cycles();
258                 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
259                 eieio();
260                 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
261                 eieio();
262         } else {
263                 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
264         }
265 }
266
267 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
268 {
269         struct spu_priv2 __iomem *priv2 = spu->priv2;
270
271         /* Save, Step 13:
272          *     Write MFC_CNTL[Dh] set to a '1' to halt
273          *     the decrementer.
274          */
275         out_be64(&priv2->mfc_control_RW, MFC_CNTL_DECREMENTER_HALTED);
276         eieio();
277 }
278
279 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
280 {
281         /* Save, Step 14:
282          *    Read PPE Timebase High and Timebase low registers
283          *    and save in CSA.  TBD.
284          */
285         csa->suspend_time = get_cycles();
286 }
287
288 static inline void remove_other_spu_access(struct spu_state *csa,
289                                            struct spu *spu)
290 {
291         /* Save, Step 15:
292          *     Remove other SPU access to this SPU by unmapping
293          *     this SPU's pages from their address space.  TBD.
294          */
295 }
296
297 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
298 {
299         struct spu_problem __iomem *prob = spu->problem;
300
301         /* Save, Step 16:
302          * Restore, Step 11.
303          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
304          *     for a value of 0.
305          */
306         out_be64(&prob->spc_mssync_RW, 1UL);
307         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
308 }
309
310 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
311 {
312         /* Save, Step 17:
313          * Restore, Step 12.
314          * Restore, Step 48.
315          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
316          *     Then issue a PPE sync instruction.
317          */
318         spu_tlb_invalidate(spu);
319         mb();
320 }
321
322 static inline void handle_pending_interrupts(struct spu_state *csa,
323                                              struct spu *spu)
324 {
325         /* Save, Step 18:
326          *     Handle any pending interrupts from this SPU
327          *     here.  This is OS or hypervisor specific.  One
328          *     option is to re-enable interrupts to handle any
329          *     pending interrupts, with the interrupt handlers
330          *     recognizing the software Context Switch Pending
331          *     flag, to ensure the SPU execution or MFC command
332          *     queue is not restarted.  TBD.
333          */
334 }
335
336 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
337 {
338         struct spu_priv2 __iomem *priv2 = spu->priv2;
339         int i;
340
341         /* Save, Step 19:
342          *     If MFC_Cntl[Se]=0 then save
343          *     MFC command queues.
344          */
345         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
346                 for (i = 0; i < 8; i++) {
347                         csa->priv2.puq[i].mfc_cq_data0_RW =
348                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
349                         csa->priv2.puq[i].mfc_cq_data1_RW =
350                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
351                         csa->priv2.puq[i].mfc_cq_data2_RW =
352                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
353                         csa->priv2.puq[i].mfc_cq_data3_RW =
354                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
355                 }
356                 for (i = 0; i < 16; i++) {
357                         csa->priv2.spuq[i].mfc_cq_data0_RW =
358                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
359                         csa->priv2.spuq[i].mfc_cq_data1_RW =
360                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
361                         csa->priv2.spuq[i].mfc_cq_data2_RW =
362                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
363                         csa->priv2.spuq[i].mfc_cq_data3_RW =
364                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
365                 }
366         }
367 }
368
369 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
370 {
371         struct spu_problem __iomem *prob = spu->problem;
372
373         /* Save, Step 20:
374          *     Save the PPU_QueryMask register
375          *     in the CSA.
376          */
377         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
378 }
379
380 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
381 {
382         struct spu_problem __iomem *prob = spu->problem;
383
384         /* Save, Step 21:
385          *     Save the PPU_QueryType register
386          *     in the CSA.
387          */
388         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
389 }
390
391 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
392 {
393         struct spu_priv2 __iomem *priv2 = spu->priv2;
394
395         /* Save, Step 22:
396          *     Save the MFC_CSR_TSQ register
397          *     in the LSCSA.
398          */
399         csa->priv2.spu_tag_status_query_RW =
400             in_be64(&priv2->spu_tag_status_query_RW);
401 }
402
403 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
404 {
405         struct spu_priv2 __iomem *priv2 = spu->priv2;
406
407         /* Save, Step 23:
408          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
409          *     registers in the CSA.
410          */
411         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
412         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
413 }
414
415 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
416 {
417         struct spu_priv2 __iomem *priv2 = spu->priv2;
418
419         /* Save, Step 24:
420          *     Save the MFC_CSR_ATO register in
421          *     the CSA.
422          */
423         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
424 }
425
426 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
427 {
428         /* Save, Step 25:
429          *     Save the MFC_TCLASS_ID register in
430          *     the CSA.
431          */
432         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
433 }
434
435 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
436 {
437         /* Save, Step 26:
438          * Restore, Step 23.
439          *     Write the MFC_TCLASS_ID register with
440          *     the value 0x10000000.
441          */
442         spu_mfc_tclass_id_set(spu, 0x10000000);
443         eieio();
444 }
445
446 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
447 {
448         struct spu_priv2 __iomem *priv2 = spu->priv2;
449
450         /* Save, Step 27:
451          * Restore, Step 14.
452          *     Write MFC_CNTL[Pc]=1 (purge queue).
453          */
454         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
455         eieio();
456 }
457
458 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
459 {
460         struct spu_priv2 __iomem *priv2 = spu->priv2;
461
462         /* Save, Step 28:
463          *     Poll MFC_CNTL[Ps] until value '11' is read
464          *     (purge complete).
465          */
466         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
467                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
468                          MFC_CNTL_PURGE_DMA_COMPLETE);
469 }
470
471 static inline void save_mfc_slbs(struct spu_state *csa, struct spu *spu)
472 {
473         struct spu_priv2 __iomem *priv2 = spu->priv2;
474         int i;
475
476         /* Save, Step 29:
477          *     If MFC_SR1[R]='1', save SLBs in CSA.
478          */
479         if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK) {
480                 csa->priv2.slb_index_W = in_be64(&priv2->slb_index_W);
481                 for (i = 0; i < 8; i++) {
482                         out_be64(&priv2->slb_index_W, i);
483                         eieio();
484                         csa->slb_esid_RW[i] = in_be64(&priv2->slb_esid_RW);
485                         csa->slb_vsid_RW[i] = in_be64(&priv2->slb_vsid_RW);
486                         eieio();
487                 }
488         }
489 }
490
491 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
492 {
493         /* Save, Step 30:
494          * Restore, Step 18:
495          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
496          *     MFC_SR1[TL,R,Pr,T] set correctly for the
497          *     OS specific environment.
498          *
499          *     Implementation note: The SPU-side code
500          *     for save/restore is privileged, so the
501          *     MFC_SR1[Pr] bit is not set.
502          *
503          */
504         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
505                               MFC_STATE1_RELOCATE_MASK |
506                               MFC_STATE1_BUS_TLBIE_MASK));
507 }
508
509 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
510 {
511         struct spu_problem __iomem *prob = spu->problem;
512
513         /* Save, Step 31:
514          *     Save SPU_NPC in the CSA.
515          */
516         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
517 }
518
519 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
520 {
521         struct spu_priv2 __iomem *priv2 = spu->priv2;
522
523         /* Save, Step 32:
524          *     Save SPU_PrivCntl in the CSA.
525          */
526         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
527 }
528
529 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
530 {
531         struct spu_priv2 __iomem *priv2 = spu->priv2;
532
533         /* Save, Step 33:
534          * Restore, Step 16:
535          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
536          */
537         out_be64(&priv2->spu_privcntl_RW, 0UL);
538         eieio();
539 }
540
541 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
542 {
543         struct spu_priv2 __iomem *priv2 = spu->priv2;
544
545         /* Save, Step 34:
546          *     Save SPU_LSLR in the CSA.
547          */
548         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
549 }
550
551 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
552 {
553         struct spu_priv2 __iomem *priv2 = spu->priv2;
554
555         /* Save, Step 35:
556          * Restore, Step 17.
557          *     Reset SPU_LSLR.
558          */
559         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
560         eieio();
561 }
562
563 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
564 {
565         struct spu_priv2 __iomem *priv2 = spu->priv2;
566
567         /* Save, Step 36:
568          *     Save SPU_Cfg in the CSA.
569          */
570         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
571 }
572
573 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
574 {
575         /* Save, Step 37:
576          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
577          *     Not performed by this implementation.
578          */
579 }
580
581 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
582 {
583         /* Save, Step 38:
584          *     Save RA_GROUP_ID register and the
585          *     RA_ENABLE reigster in the CSA.
586          */
587         csa->priv1.resource_allocation_groupID_RW =
588                 spu_resource_allocation_groupID_get(spu);
589         csa->priv1.resource_allocation_enable_RW =
590                 spu_resource_allocation_enable_get(spu);
591 }
592
593 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
594 {
595         struct spu_problem __iomem *prob = spu->problem;
596
597         /* Save, Step 39:
598          *     Save MB_Stat register in the CSA.
599          */
600         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
601 }
602
603 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
604 {
605         struct spu_problem __iomem *prob = spu->problem;
606
607         /* Save, Step 40:
608          *     Save the PPU_MB register in the CSA.
609          */
610         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
611 }
612
613 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
614 {
615         struct spu_priv2 __iomem *priv2 = spu->priv2;
616
617         /* Save, Step 41:
618          *     Save the PPUINT_MB register in the CSA.
619          */
620         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
621 }
622
623 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
624 {
625         struct spu_priv2 __iomem *priv2 = spu->priv2;
626         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
627         int i;
628
629         /* Save, Step 42:
630          */
631
632         /* Save CH 1, without channel count */
633         out_be64(&priv2->spu_chnlcntptr_RW, 1);
634         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
635
636         /* Save the following CH: [0,3,4,24,25,27] */
637         for (i = 0; i < 7; i++) {
638                 idx = ch_indices[i];
639                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
640                 eieio();
641                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
642                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
643                 out_be64(&priv2->spu_chnldata_RW, 0UL);
644                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
645                 eieio();
646         }
647 }
648
649 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
650 {
651         struct spu_priv2 __iomem *priv2 = spu->priv2;
652         int i;
653
654         /* Save, Step 43:
655          *     Save SPU Read Mailbox Channel.
656          */
657         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
658         eieio();
659         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
660         for (i = 0; i < 4; i++) {
661                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
662         }
663         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
664         eieio();
665 }
666
667 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
668 {
669         struct spu_priv2 __iomem *priv2 = spu->priv2;
670
671         /* Save, Step 44:
672          *     Save MFC_CMD Channel.
673          */
674         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
675         eieio();
676         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
677         eieio();
678 }
679
680 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
681 {
682         struct spu_priv2 __iomem *priv2 = spu->priv2;
683         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
684         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
685         u64 idx;
686         int i;
687
688         /* Save, Step 45:
689          *     Reset the following CH: [21, 23, 28, 30]
690          */
691         for (i = 0; i < 4; i++) {
692                 idx = ch_indices[i];
693                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
694                 eieio();
695                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
696                 eieio();
697         }
698 }
699
700 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
701 {
702         struct spu_priv2 __iomem *priv2 = spu->priv2;
703
704         /* Save, Step 46:
705          * Restore, Step 25.
706          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
707          */
708         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
709 }
710
711 static inline void invalidate_slbs(struct spu_state *csa, struct spu *spu)
712 {
713         struct spu_priv2 __iomem *priv2 = spu->priv2;
714
715         /* Save, Step 45:
716          * Restore, Step 19:
717          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All.
718          */
719         if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK) {
720                 out_be64(&priv2->slb_invalidate_all_W, 0UL);
721                 eieio();
722         }
723 }
724
725 static inline void get_kernel_slb(u64 ea, u64 slb[2])
726 {
727         u64 llp;
728
729         if (REGION_ID(ea) == KERNEL_REGION_ID)
730                 llp = mmu_psize_defs[mmu_linear_psize].sllp;
731         else
732                 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
733         slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
734                 SLB_VSID_KERNEL | llp;
735         slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
736 }
737
738 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
739 {
740         struct spu_priv2 __iomem *priv2 = spu->priv2;
741
742         out_be64(&priv2->slb_index_W, slbe);
743         eieio();
744         out_be64(&priv2->slb_vsid_RW, slb[0]);
745         out_be64(&priv2->slb_esid_RW, slb[1]);
746         eieio();
747 }
748
749 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
750 {
751         u64 code_slb[2];
752         u64 lscsa_slb[2];
753
754         /* Save, Step 47:
755          * Restore, Step 30.
756          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
757          *     register, then initialize SLB_VSID and SLB_ESID
758          *     to provide access to SPU context save code and
759          *     LSCSA.
760          *
761          *     This implementation places both the context
762          *     switch code and LSCSA in kernel address space.
763          *
764          *     Further this implementation assumes that the
765          *     MFC_SR1[R]=1 (in other words, assume that
766          *     translation is desired by OS environment).
767          */
768         invalidate_slbs(csa, spu);
769         get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
770         get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
771         load_mfc_slb(spu, code_slb, 0);
772         if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
773                 load_mfc_slb(spu, lscsa_slb, 1);
774 }
775
776 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
777 {
778         /* Save, Step 48:
779          * Restore, Step 23.
780          *     Change the software context switch pending flag
781          *     to context switch active.
782          */
783         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
784         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
785         mb();
786 }
787
788 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
789 {
790         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
791             CLASS1_ENABLE_STORAGE_FAULT_INTR;
792
793         /* Save, Step 49:
794          * Restore, Step 22:
795          *     Reset and then enable interrupts, as
796          *     needed by OS.
797          *
798          *     This implementation enables only class1
799          *     (translation) interrupts.
800          */
801         spin_lock_irq(&spu->register_lock);
802         spu_int_stat_clear(spu, 0, ~0ul);
803         spu_int_stat_clear(spu, 1, ~0ul);
804         spu_int_stat_clear(spu, 2, ~0ul);
805         spu_int_mask_set(spu, 0, 0ul);
806         spu_int_mask_set(spu, 1, class1_mask);
807         spu_int_mask_set(spu, 2, 0ul);
808         spin_unlock_irq(&spu->register_lock);
809 }
810
811 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
812                                unsigned int ls_offset, unsigned int size,
813                                unsigned int tag, unsigned int rclass,
814                                unsigned int cmd)
815 {
816         struct spu_problem __iomem *prob = spu->problem;
817         union mfc_tag_size_class_cmd command;
818         unsigned int transfer_size;
819         volatile unsigned int status = 0x0;
820
821         while (size > 0) {
822                 transfer_size =
823                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
824                 command.u.mfc_size = transfer_size;
825                 command.u.mfc_tag = tag;
826                 command.u.mfc_rclassid = rclass;
827                 command.u.mfc_cmd = cmd;
828                 do {
829                         out_be32(&prob->mfc_lsa_W, ls_offset);
830                         out_be64(&prob->mfc_ea_W, ea);
831                         out_be64(&prob->mfc_union_W.all64, command.all64);
832                         status =
833                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
834                         if (unlikely(status & 0x2)) {
835                                 cpu_relax();
836                         }
837                 } while (status & 0x3);
838                 size -= transfer_size;
839                 ea += transfer_size;
840                 ls_offset += transfer_size;
841         }
842         return 0;
843 }
844
845 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
846 {
847         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
848         unsigned int ls_offset = 0x0;
849         unsigned int size = 16384;
850         unsigned int tag = 0;
851         unsigned int rclass = 0;
852         unsigned int cmd = MFC_PUT_CMD;
853
854         /* Save, Step 50:
855          *     Issue a DMA command to copy the first 16K bytes
856          *     of local storage to the CSA.
857          */
858         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
859 }
860
861 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
862 {
863         struct spu_problem __iomem *prob = spu->problem;
864
865         /* Save, Step 51:
866          * Restore, Step 31.
867          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
868          *     point address of context save code in local
869          *     storage.
870          *
871          *     This implementation uses SPU-side save/restore
872          *     programs with entry points at LSA of 0.
873          */
874         out_be32(&prob->spu_npc_RW, 0);
875         eieio();
876 }
877
878 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
879 {
880         struct spu_problem __iomem *prob = spu->problem;
881         union {
882                 u64 ull;
883                 u32 ui[2];
884         } addr64;
885
886         /* Save, Step 52:
887          * Restore, Step 32:
888          *    Write SPU_Sig_Notify_1 register with upper 32-bits
889          *    of the CSA.LSCSA effective address.
890          */
891         addr64.ull = (u64) csa->lscsa;
892         out_be32(&prob->signal_notify1, addr64.ui[0]);
893         eieio();
894 }
895
896 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
897 {
898         struct spu_problem __iomem *prob = spu->problem;
899         union {
900                 u64 ull;
901                 u32 ui[2];
902         } addr64;
903
904         /* Save, Step 53:
905          * Restore, Step 33:
906          *    Write SPU_Sig_Notify_2 register with lower 32-bits
907          *    of the CSA.LSCSA effective address.
908          */
909         addr64.ull = (u64) csa->lscsa;
910         out_be32(&prob->signal_notify2, addr64.ui[1]);
911         eieio();
912 }
913
914 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
915 {
916         unsigned long addr = (unsigned long)&spu_save_code[0];
917         unsigned int ls_offset = 0x0;
918         unsigned int size = sizeof(spu_save_code);
919         unsigned int tag = 0;
920         unsigned int rclass = 0;
921         unsigned int cmd = MFC_GETFS_CMD;
922
923         /* Save, Step 54:
924          *     Issue a DMA command to copy context save code
925          *     to local storage and start SPU.
926          */
927         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
928 }
929
930 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
931 {
932         struct spu_problem __iomem *prob = spu->problem;
933
934         /* Save, Step 55:
935          * Restore, Step 38.
936          *     Write PPU_QueryMask=1 (enable Tag Group 0)
937          *     and issue eieio instruction.
938          */
939         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
940         eieio();
941 }
942
943 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
944 {
945         struct spu_problem __iomem *prob = spu->problem;
946         u32 mask = MFC_TAGID_TO_TAGMASK(0);
947         unsigned long flags;
948
949         /* Save, Step 56:
950          * Restore, Step 39.
951          * Restore, Step 39.
952          * Restore, Step 46.
953          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
954          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
955          *     Complete Interrupt.  Write INT_Stat_Class0 or
956          *     INT_Stat_Class2 with value of 'handled'.
957          */
958         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
959
960         local_irq_save(flags);
961         spu_int_stat_clear(spu, 0, ~(0ul));
962         spu_int_stat_clear(spu, 2, ~(0ul));
963         local_irq_restore(flags);
964 }
965
966 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
967 {
968         struct spu_problem __iomem *prob = spu->problem;
969         unsigned long flags;
970
971         /* Save, Step 57:
972          * Restore, Step 40.
973          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
974          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
975          *     or INT_Stat_class2 with value of handled.
976          */
977         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
978
979         local_irq_save(flags);
980         spu_int_stat_clear(spu, 0, ~(0ul));
981         spu_int_stat_clear(spu, 2, ~(0ul));
982         local_irq_restore(flags);
983 }
984
985 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
986 {
987         struct spu_problem __iomem *prob = spu->problem;
988         u32 complete;
989
990         /* Save, Step 54:
991          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
992          *     context save succeeded, otherwise context save
993          *     failed.
994          */
995         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
996                     SPU_STATUS_STOPPED_BY_STOP);
997         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
998 }
999
1000 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
1001 {
1002         /* Restore, Step 4:
1003          *    If required, notify the "using application" that
1004          *    the SPU task has been terminated.  TBD.
1005          */
1006 }
1007
1008 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
1009 {
1010         struct spu_priv2 __iomem *priv2 = spu->priv2;
1011
1012         /* Restore, Step 7:
1013          * Restore, Step 47.
1014          *     Write MFC_Cntl[Dh,Sc]='1','1' to suspend
1015          *     the queue and halt the decrementer.
1016          */
1017         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
1018                  MFC_CNTL_DECREMENTER_HALTED);
1019         eieio();
1020 }
1021
1022 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
1023                                              struct spu *spu)
1024 {
1025         struct spu_priv2 __iomem *priv2 = spu->priv2;
1026
1027         /* Restore, Step 8:
1028          * Restore, Step 47.
1029          *     Poll MFC_CNTL[Ss] until 11 is returned.
1030          */
1031         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1032                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
1033                          MFC_CNTL_SUSPEND_COMPLETE);
1034 }
1035
1036 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1037 {
1038         struct spu_problem __iomem *prob = spu->problem;
1039
1040         /* Restore, Step 9:
1041          *    If SPU_Status[R]=1, stop SPU execution
1042          *    and wait for stop to complete.
1043          *
1044          *    Returns       1 if SPU_Status[R]=1 on entry.
1045          *                  0 otherwise
1046          */
1047         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1048                 if (in_be32(&prob->spu_status_R) &
1049                     SPU_STATUS_ISOLATED_EXIT_STAUTUS) {
1050                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1051                                         SPU_STATUS_RUNNING);
1052                 }
1053                 if ((in_be32(&prob->spu_status_R) &
1054                      SPU_STATUS_ISOLATED_LOAD_STAUTUS)
1055                     || (in_be32(&prob->spu_status_R) &
1056                         SPU_STATUS_ISOLATED_STATE)) {
1057                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1058                         eieio();
1059                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1060                                         SPU_STATUS_RUNNING);
1061                         out_be32(&prob->spu_runcntl_RW, 0x2);
1062                         eieio();
1063                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1064                                         SPU_STATUS_RUNNING);
1065                 }
1066                 if (in_be32(&prob->spu_status_R) &
1067                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1068                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1069                         eieio();
1070                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1071                                         SPU_STATUS_RUNNING);
1072                 }
1073                 return 1;
1074         }
1075         return 0;
1076 }
1077
1078 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1079 {
1080         struct spu_problem __iomem *prob = spu->problem;
1081
1082         /* Restore, Step 10:
1083          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1084          *    release SPU from isolate state.
1085          */
1086         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1087                 if (in_be32(&prob->spu_status_R) &
1088                     SPU_STATUS_ISOLATED_EXIT_STAUTUS) {
1089                         spu_mfc_sr1_set(spu,
1090                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1091                         eieio();
1092                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1093                         eieio();
1094                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1095                                         SPU_STATUS_RUNNING);
1096                 }
1097                 if ((in_be32(&prob->spu_status_R) &
1098                      SPU_STATUS_ISOLATED_LOAD_STAUTUS)
1099                     || (in_be32(&prob->spu_status_R) &
1100                         SPU_STATUS_ISOLATED_STATE)) {
1101                         spu_mfc_sr1_set(spu,
1102                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1103                         eieio();
1104                         out_be32(&prob->spu_runcntl_RW, 0x2);
1105                         eieio();
1106                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1107                                         SPU_STATUS_RUNNING);
1108                 }
1109         }
1110 }
1111
1112 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1113 {
1114         struct spu_priv2 __iomem *priv2 = spu->priv2;
1115         u64 ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1116         u64 idx;
1117         int i;
1118
1119         /* Restore, Step 20:
1120          */
1121
1122         /* Reset CH 1 */
1123         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1124         out_be64(&priv2->spu_chnldata_RW, 0UL);
1125
1126         /* Reset the following CH: [0,3,4,24,25,27] */
1127         for (i = 0; i < 7; i++) {
1128                 idx = ch_indices[i];
1129                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1130                 eieio();
1131                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1132                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1133                 eieio();
1134         }
1135 }
1136
1137 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1138 {
1139         struct spu_priv2 __iomem *priv2 = spu->priv2;
1140         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1141         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1142         u64 idx;
1143         int i;
1144
1145         /* Restore, Step 21:
1146          *     Reset the following CH: [21, 23, 28, 29, 30]
1147          */
1148         for (i = 0; i < 5; i++) {
1149                 idx = ch_indices[i];
1150                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1151                 eieio();
1152                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1153                 eieio();
1154         }
1155 }
1156
1157 static inline void setup_spu_status_part1(struct spu_state *csa,
1158                                           struct spu *spu)
1159 {
1160         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1161         u32 status_I = SPU_STATUS_INVALID_INSTR;
1162         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1163         u32 status_S = SPU_STATUS_SINGLE_STEP;
1164         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1165         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1166         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1167         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1168         u32 status_code;
1169
1170         /* Restore, Step 27:
1171          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1172          *     instruction sequence to the end of the SPU based restore
1173          *     code (after the "context restored" stop and signal) to
1174          *     restore the correct SPU status.
1175          *
1176          *     NOTE: Rather than modifying the SPU executable, we
1177          *     instead add a new 'stopped_status' field to the
1178          *     LSCSA.  The SPU-side restore reads this field and
1179          *     takes the appropriate action when exiting.
1180          */
1181
1182         status_code =
1183             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1184         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1185
1186                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1187                  * by Stop and Signal instruction, followed by 'br -4'.
1188                  *
1189                  */
1190                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1191                 csa->lscsa->stopped_status.slot[1] = status_code;
1192
1193         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1194
1195                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1196                  * by Stop and Signal instruction, followed by
1197                  * 'br -4'.
1198                  */
1199                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1200                 csa->lscsa->stopped_status.slot[1] = status_code;
1201
1202         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1203
1204                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1205                  * followed by 'br -4'.
1206                  */
1207                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1208                 csa->lscsa->stopped_status.slot[1] = status_code;
1209
1210         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1211
1212                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1213                  * by 'br -4'.
1214                  */
1215                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1216                 csa->lscsa->stopped_status.slot[1] = status_code;
1217
1218         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1219
1220                 /* SPU_Status[P]=1 - Stop and Signal instruction
1221                  * followed by 'br -4'.
1222                  */
1223                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1224                 csa->lscsa->stopped_status.slot[1] = status_code;
1225
1226         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1227
1228                 /* SPU_Status[H]=1 - Halt Conditional, followed
1229                  * by 'br -4'.
1230                  */
1231                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1232
1233         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1234
1235                 /* SPU_Status[S]=1 - Two nop instructions.
1236                  */
1237                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1238
1239         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1240
1241                 /* SPU_Status[I]=1 - Illegal instruction followed
1242                  * by 'br -4'.
1243                  */
1244                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1245
1246         }
1247 }
1248
1249 static inline void setup_spu_status_part2(struct spu_state *csa,
1250                                           struct spu *spu)
1251 {
1252         u32 mask;
1253
1254         /* Restore, Step 28:
1255          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1256          *     add a 'br *' instruction to the end of
1257          *     the SPU based restore code.
1258          *
1259          *     NOTE: Rather than modifying the SPU executable, we
1260          *     instead add a new 'stopped_status' field to the
1261          *     LSCSA.  The SPU-side restore reads this field and
1262          *     takes the appropriate action when exiting.
1263          */
1264         mask = SPU_STATUS_INVALID_INSTR |
1265             SPU_STATUS_SINGLE_STEP |
1266             SPU_STATUS_STOPPED_BY_HALT |
1267             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1268         if (!(csa->prob.spu_status_R & mask)) {
1269                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1270         }
1271 }
1272
1273 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1274 {
1275         /* Restore, Step 29:
1276          *     Restore RA_GROUP_ID register and the
1277          *     RA_ENABLE reigster from the CSA.
1278          */
1279         spu_resource_allocation_groupID_set(spu,
1280                         csa->priv1.resource_allocation_groupID_RW);
1281         spu_resource_allocation_enable_set(spu,
1282                         csa->priv1.resource_allocation_enable_RW);
1283 }
1284
1285 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1286 {
1287         unsigned long addr = (unsigned long)&spu_restore_code[0];
1288         unsigned int ls_offset = 0x0;
1289         unsigned int size = sizeof(spu_restore_code);
1290         unsigned int tag = 0;
1291         unsigned int rclass = 0;
1292         unsigned int cmd = MFC_GETFS_CMD;
1293
1294         /* Restore, Step 37:
1295          *     Issue MFC DMA command to copy context
1296          *     restore code to local storage.
1297          */
1298         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1299 }
1300
1301 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1302 {
1303         /* Restore, Step 34:
1304          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1305          *     running) then adjust decrementer, set
1306          *     decrementer running status in LSCSA,
1307          *     and set decrementer "wrapped" status
1308          *     in LSCSA.
1309          */
1310         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1311                 cycles_t resume_time = get_cycles();
1312                 cycles_t delta_time = resume_time - csa->suspend_time;
1313
1314                 csa->lscsa->decr.slot[0] -= delta_time;
1315         }
1316 }
1317
1318 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1319 {
1320         /* Restore, Step 35:
1321          *     Copy the CSA.PU_MB data into the LSCSA.
1322          */
1323         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1324 }
1325
1326 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1327 {
1328         /* Restore, Step 36:
1329          *     Copy the CSA.PUINT_MB data into the LSCSA.
1330          */
1331         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1332 }
1333
1334 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1335 {
1336         struct spu_problem __iomem *prob = spu->problem;
1337         u32 complete;
1338
1339         /* Restore, Step 40:
1340          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1341          *     context restore succeeded, otherwise context restore
1342          *     failed.
1343          */
1344         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1345                     SPU_STATUS_STOPPED_BY_STOP);
1346         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1347 }
1348
1349 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1350 {
1351         struct spu_priv2 __iomem *priv2 = spu->priv2;
1352
1353         /* Restore, Step 41:
1354          *     Restore SPU_PrivCntl from the CSA.
1355          */
1356         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1357         eieio();
1358 }
1359
1360 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1361 {
1362         struct spu_problem __iomem *prob = spu->problem;
1363         u32 mask;
1364
1365         /* Restore, Step 42:
1366          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1367          *     restore the error or single step state.
1368          */
1369         mask = SPU_STATUS_INVALID_INSTR |
1370             SPU_STATUS_SINGLE_STEP |
1371             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1372         if (csa->prob.spu_status_R & mask) {
1373                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1374                 eieio();
1375                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1376                                 SPU_STATUS_RUNNING);
1377         }
1378 }
1379
1380 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1381 {
1382         struct spu_problem __iomem *prob = spu->problem;
1383         u32 mask;
1384
1385         /* Restore, Step 43:
1386          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1387          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1388          *     then write '00' to SPU_RunCntl[R0R1] and wait
1389          *     for SPU_Status[R]=0.
1390          */
1391         mask = SPU_STATUS_INVALID_INSTR |
1392             SPU_STATUS_SINGLE_STEP |
1393             SPU_STATUS_STOPPED_BY_HALT |
1394             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1395         if (!(csa->prob.spu_status_R & mask)) {
1396                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1397                 eieio();
1398                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1399                                  SPU_STATUS_RUNNING);
1400                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1401                 eieio();
1402                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1403                                 SPU_STATUS_RUNNING);
1404         }
1405 }
1406
1407 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1408 {
1409         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1410         unsigned int ls_offset = 0x0;
1411         unsigned int size = 16384;
1412         unsigned int tag = 0;
1413         unsigned int rclass = 0;
1414         unsigned int cmd = MFC_GET_CMD;
1415
1416         /* Restore, Step 44:
1417          *     Issue a DMA command to restore the first
1418          *     16kb of local storage from CSA.
1419          */
1420         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1421 }
1422
1423 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1424 {
1425         /* Restore, Step 49:
1426          *     Write INT_MASK_class0 with value of 0.
1427          *     Write INT_MASK_class1 with value of 0.
1428          *     Write INT_MASK_class2 with value of 0.
1429          *     Write INT_STAT_class0 with value of -1.
1430          *     Write INT_STAT_class1 with value of -1.
1431          *     Write INT_STAT_class2 with value of -1.
1432          */
1433         spin_lock_irq(&spu->register_lock);
1434         spu_int_mask_set(spu, 0, 0ul);
1435         spu_int_mask_set(spu, 1, 0ul);
1436         spu_int_mask_set(spu, 2, 0ul);
1437         spu_int_stat_clear(spu, 0, ~0ul);
1438         spu_int_stat_clear(spu, 1, ~0ul);
1439         spu_int_stat_clear(spu, 2, ~0ul);
1440         spin_unlock_irq(&spu->register_lock);
1441 }
1442
1443 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1444 {
1445         struct spu_priv2 __iomem *priv2 = spu->priv2;
1446         int i;
1447
1448         /* Restore, Step 50:
1449          *     If MFC_Cntl[Se]!=0 then restore
1450          *     MFC command queues.
1451          */
1452         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1453                 for (i = 0; i < 8; i++) {
1454                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1455                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1456                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1457                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1458                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1459                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1460                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1461                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1462                 }
1463                 for (i = 0; i < 16; i++) {
1464                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1465                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1466                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1467                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1468                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1469                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1470                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1471                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1472                 }
1473         }
1474         eieio();
1475 }
1476
1477 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1478 {
1479         struct spu_problem __iomem *prob = spu->problem;
1480
1481         /* Restore, Step 51:
1482          *     Restore the PPU_QueryMask register from CSA.
1483          */
1484         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1485         eieio();
1486 }
1487
1488 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1489 {
1490         struct spu_problem __iomem *prob = spu->problem;
1491
1492         /* Restore, Step 52:
1493          *     Restore the PPU_QueryType register from CSA.
1494          */
1495         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1496         eieio();
1497 }
1498
1499 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1500 {
1501         struct spu_priv2 __iomem *priv2 = spu->priv2;
1502
1503         /* Restore, Step 53:
1504          *     Restore the MFC_CSR_TSQ register from CSA.
1505          */
1506         out_be64(&priv2->spu_tag_status_query_RW,
1507                  csa->priv2.spu_tag_status_query_RW);
1508         eieio();
1509 }
1510
1511 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1512 {
1513         struct spu_priv2 __iomem *priv2 = spu->priv2;
1514
1515         /* Restore, Step 54:
1516          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1517          *     registers from CSA.
1518          */
1519         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1520         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1521         eieio();
1522 }
1523
1524 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1525 {
1526         struct spu_priv2 __iomem *priv2 = spu->priv2;
1527
1528         /* Restore, Step 55:
1529          *     Restore the MFC_CSR_ATO register from CSA.
1530          */
1531         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1532 }
1533
1534 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1535 {
1536         /* Restore, Step 56:
1537          *     Restore the MFC_TCLASS_ID register from CSA.
1538          */
1539         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1540         eieio();
1541 }
1542
1543 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1544 {
1545         u64 ch0_cnt, ch0_data;
1546         u64 ch1_data;
1547
1548         /* Restore, Step 57:
1549          *    Set the Lock Line Reservation Lost Event by:
1550          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1551          *      2. If CSA.SPU_Channel_0_Count=0 and
1552          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1553          *         CSA.SPU_Event_Status[Lr]=0 then set
1554          *         CSA.SPU_Event_Status_Count=1.
1555          */
1556         ch0_cnt = csa->spu_chnlcnt_RW[0];
1557         ch0_data = csa->spu_chnldata_RW[0];
1558         ch1_data = csa->spu_chnldata_RW[1];
1559         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1560         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1561             (ch1_data & MFC_LLR_LOST_EVENT)) {
1562                 csa->spu_chnlcnt_RW[0] = 1;
1563         }
1564 }
1565
1566 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1567 {
1568         /* Restore, Step 58:
1569          *     If the status of the CSA software decrementer
1570          *     "wrapped" flag is set, OR in a '1' to
1571          *     CSA.SPU_Event_Status[Tm].
1572          */
1573         if (csa->lscsa->decr_status.slot[0] == 1) {
1574                 csa->spu_chnldata_RW[0] |= 0x20;
1575         }
1576         if ((csa->lscsa->decr_status.slot[0] == 1) &&
1577             (csa->spu_chnlcnt_RW[0] == 0 &&
1578              ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1579              ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1580                 csa->spu_chnlcnt_RW[0] = 1;
1581         }
1582 }
1583
1584 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1585 {
1586         struct spu_priv2 __iomem *priv2 = spu->priv2;
1587         u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1588         int i;
1589
1590         /* Restore, Step 59:
1591          */
1592
1593         /* Restore CH 1 without count */
1594         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1595         out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1596
1597         /* Restore the following CH: [0,3,4,24,25,27] */
1598         for (i = 0; i < 7; i++) {
1599                 idx = ch_indices[i];
1600                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1601                 eieio();
1602                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1603                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1604                 eieio();
1605         }
1606 }
1607
1608 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1609 {
1610         struct spu_priv2 __iomem *priv2 = spu->priv2;
1611         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1612         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1613         u64 idx;
1614         int i;
1615
1616         /* Restore, Step 60:
1617          *     Restore the following CH: [9,21,23].
1618          */
1619         ch_counts[0] = 1UL;
1620         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1621         ch_counts[2] = 1UL;
1622         for (i = 0; i < 3; i++) {
1623                 idx = ch_indices[i];
1624                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1625                 eieio();
1626                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1627                 eieio();
1628         }
1629 }
1630
1631 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1632 {
1633         struct spu_priv2 __iomem *priv2 = spu->priv2;
1634
1635         /* Restore, Step 61:
1636          *     Restore the SPU_LSLR register from CSA.
1637          */
1638         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1639         eieio();
1640 }
1641
1642 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1643 {
1644         struct spu_priv2 __iomem *priv2 = spu->priv2;
1645
1646         /* Restore, Step 62:
1647          *     Restore the SPU_Cfg register from CSA.
1648          */
1649         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1650         eieio();
1651 }
1652
1653 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1654 {
1655         /* Restore, Step 63:
1656          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1657          *     Not performed by this implementation.
1658          */
1659 }
1660
1661 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1662 {
1663         struct spu_problem __iomem *prob = spu->problem;
1664
1665         /* Restore, Step 64:
1666          *     Restore SPU_NPC from CSA.
1667          */
1668         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1669         eieio();
1670 }
1671
1672 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1673 {
1674         struct spu_priv2 __iomem *priv2 = spu->priv2;
1675         int i;
1676
1677         /* Restore, Step 65:
1678          *     Restore MFC_RdSPU_MB from CSA.
1679          */
1680         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1681         eieio();
1682         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1683         for (i = 0; i < 4; i++) {
1684                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1685         }
1686         eieio();
1687 }
1688
1689 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1690 {
1691         struct spu_problem __iomem *prob = spu->problem;
1692         u32 dummy = 0;
1693
1694         /* Restore, Step 66:
1695          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1696          *     read from the PPU_MB register.
1697          */
1698         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1699                 dummy = in_be32(&prob->pu_mb_R);
1700                 eieio();
1701         }
1702 }
1703
1704 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1705 {
1706         struct spu_priv2 __iomem *priv2 = spu->priv2;
1707         u64 dummy = 0UL;
1708
1709         /* Restore, Step 66:
1710          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1711          *     read from the PPUINT_MB register.
1712          */
1713         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1714                 dummy = in_be64(&priv2->puint_mb_R);
1715                 eieio();
1716                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1717                 eieio();
1718         }
1719 }
1720
1721 static inline void restore_mfc_slbs(struct spu_state *csa, struct spu *spu)
1722 {
1723         struct spu_priv2 __iomem *priv2 = spu->priv2;
1724         int i;
1725
1726         /* Restore, Step 68:
1727          *     If MFC_SR1[R]='1', restore SLBs from CSA.
1728          */
1729         if (csa->priv1.mfc_sr1_RW & MFC_STATE1_RELOCATE_MASK) {
1730                 for (i = 0; i < 8; i++) {
1731                         out_be64(&priv2->slb_index_W, i);
1732                         eieio();
1733                         out_be64(&priv2->slb_esid_RW, csa->slb_esid_RW[i]);
1734                         out_be64(&priv2->slb_vsid_RW, csa->slb_vsid_RW[i]);
1735                         eieio();
1736                 }
1737                 out_be64(&priv2->slb_index_W, csa->priv2.slb_index_W);
1738                 eieio();
1739         }
1740 }
1741
1742 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1743 {
1744         /* Restore, Step 69:
1745          *     Restore the MFC_SR1 register from CSA.
1746          */
1747         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1748         eieio();
1749 }
1750
1751 static inline void restore_other_spu_access(struct spu_state *csa,
1752                                             struct spu *spu)
1753 {
1754         /* Restore, Step 70:
1755          *     Restore other SPU mappings to this SPU. TBD.
1756          */
1757 }
1758
1759 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1760 {
1761         struct spu_problem __iomem *prob = spu->problem;
1762
1763         /* Restore, Step 71:
1764          *     If CSA.SPU_Status[R]=1 then write
1765          *     SPU_RunCntl[R0R1]='01'.
1766          */
1767         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1768                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1769                 eieio();
1770         }
1771 }
1772
1773 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1774 {
1775         struct spu_priv2 __iomem *priv2 = spu->priv2;
1776
1777         /* Restore, Step 72:
1778          *    Restore the MFC_CNTL register for the CSA.
1779          */
1780         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1781         eieio();
1782 }
1783
1784 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1785 {
1786         /* Restore, Step 73:
1787          *     Enable user-space access (if provided) to this
1788          *     SPU by mapping the virtual pages assigned to
1789          *     the SPU memory-mapped I/O (MMIO) for problem
1790          *     state. TBD.
1791          */
1792 }
1793
1794 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1795 {
1796         /* Restore, Step 74:
1797          *     Reset the "context switch active" flag.
1798          */
1799         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1800         mb();
1801 }
1802
1803 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1804 {
1805         /* Restore, Step 75:
1806          *     Re-enable SPU interrupts.
1807          */
1808         spin_lock_irq(&spu->register_lock);
1809         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1810         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1811         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1812         spin_unlock_irq(&spu->register_lock);
1813 }
1814
1815 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1816 {
1817         /*
1818          * Combined steps 2-18 of SPU context save sequence, which
1819          * quiesce the SPU state (disable SPU execution, MFC command
1820          * queues, decrementer, SPU interrupts, etc.).
1821          *
1822          * Returns      0 on success.
1823          *              2 if failed step 2.
1824          *              6 if failed step 6.
1825          */
1826
1827         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1828                 return 2;
1829         }
1830         disable_interrupts(prev, spu);          /* Step 3. */
1831         set_watchdog_timer(prev, spu);          /* Step 4. */
1832         inhibit_user_access(prev, spu);         /* Step 5. */
1833         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1834                 return 6;
1835         }
1836         set_switch_pending(prev, spu);          /* Step 7. */
1837         save_mfc_cntl(prev, spu);               /* Step 8. */
1838         save_spu_runcntl(prev, spu);            /* Step 9. */
1839         save_mfc_sr1(prev, spu);                /* Step 10. */
1840         save_spu_status(prev, spu);             /* Step 11. */
1841         save_mfc_decr(prev, spu);               /* Step 12. */
1842         halt_mfc_decr(prev, spu);               /* Step 13. */
1843         save_timebase(prev, spu);               /* Step 14. */
1844         remove_other_spu_access(prev, spu);     /* Step 15. */
1845         do_mfc_mssync(prev, spu);               /* Step 16. */
1846         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1847         handle_pending_interrupts(prev, spu);   /* Step 18. */
1848
1849         return 0;
1850 }
1851
1852 static void save_csa(struct spu_state *prev, struct spu *spu)
1853 {
1854         /*
1855          * Combine steps 19-44 of SPU context save sequence, which
1856          * save regions of the privileged & problem state areas.
1857          */
1858
1859         save_mfc_queues(prev, spu);     /* Step 19. */
1860         save_ppu_querymask(prev, spu);  /* Step 20. */
1861         save_ppu_querytype(prev, spu);  /* Step 21. */
1862         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1863         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1864         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1865         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1866         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1867         purge_mfc_queue(prev, spu);     /* Step 27. */
1868         wait_purge_complete(prev, spu); /* Step 28. */
1869         save_mfc_slbs(prev, spu);       /* Step 29. */
1870         setup_mfc_sr1(prev, spu);       /* Step 30. */
1871         save_spu_npc(prev, spu);        /* Step 31. */
1872         save_spu_privcntl(prev, spu);   /* Step 32. */
1873         reset_spu_privcntl(prev, spu);  /* Step 33. */
1874         save_spu_lslr(prev, spu);       /* Step 34. */
1875         reset_spu_lslr(prev, spu);      /* Step 35. */
1876         save_spu_cfg(prev, spu);        /* Step 36. */
1877         save_pm_trace(prev, spu);       /* Step 37. */
1878         save_mfc_rag(prev, spu);        /* Step 38. */
1879         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1880         save_ppu_mb(prev, spu);         /* Step 40. */
1881         save_ppuint_mb(prev, spu);      /* Step 41. */
1882         save_ch_part1(prev, spu);       /* Step 42. */
1883         save_spu_mb(prev, spu);         /* Step 43. */
1884         save_mfc_cmd(prev, spu);        /* Step 44. */
1885         reset_ch(prev, spu);            /* Step 45. */
1886 }
1887
1888 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1889 {
1890         /*
1891          * Perform steps 46-57 of SPU context save sequence,
1892          * which save regions of the local store and register
1893          * file.
1894          */
1895
1896         resume_mfc_queue(prev, spu);    /* Step 46. */
1897         setup_mfc_slbs(prev, spu);      /* Step 47. */
1898         set_switch_active(prev, spu);   /* Step 48. */
1899         enable_interrupts(prev, spu);   /* Step 49. */
1900         save_ls_16kb(prev, spu);        /* Step 50. */
1901         set_spu_npc(prev, spu);         /* Step 51. */
1902         set_signot1(prev, spu);         /* Step 52. */
1903         set_signot2(prev, spu);         /* Step 53. */
1904         send_save_code(prev, spu);      /* Step 54. */
1905         set_ppu_querymask(prev, spu);   /* Step 55. */
1906         wait_tag_complete(prev, spu);   /* Step 56. */
1907         wait_spu_stopped(prev, spu);    /* Step 57. */
1908 }
1909
1910 static void harvest(struct spu_state *prev, struct spu *spu)
1911 {
1912         /*
1913          * Perform steps 2-25 of SPU context restore sequence,
1914          * which resets an SPU either after a failed save, or
1915          * when using SPU for first time.
1916          */
1917
1918         disable_interrupts(prev, spu);          /* Step 2.  */
1919         inhibit_user_access(prev, spu);         /* Step 3.  */
1920         terminate_spu_app(prev, spu);           /* Step 4.  */
1921         set_switch_pending(prev, spu);          /* Step 5.  */
1922         remove_other_spu_access(prev, spu);     /* Step 6.  */
1923         suspend_mfc(prev, spu);                 /* Step 7.  */
1924         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1925         if (!suspend_spe(prev, spu))            /* Step 9.  */
1926                 clear_spu_status(prev, spu);    /* Step 10. */
1927         do_mfc_mssync(prev, spu);               /* Step 11. */
1928         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1929         handle_pending_interrupts(prev, spu);   /* Step 13. */
1930         purge_mfc_queue(prev, spu);             /* Step 14. */
1931         wait_purge_complete(prev, spu);         /* Step 15. */
1932         reset_spu_privcntl(prev, spu);          /* Step 16. */
1933         reset_spu_lslr(prev, spu);              /* Step 17. */
1934         setup_mfc_sr1(prev, spu);               /* Step 18. */
1935         invalidate_slbs(prev, spu);             /* Step 19. */
1936         reset_ch_part1(prev, spu);              /* Step 20. */
1937         reset_ch_part2(prev, spu);              /* Step 21. */
1938         enable_interrupts(prev, spu);           /* Step 22. */
1939         set_switch_active(prev, spu);           /* Step 23. */
1940         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1941         resume_mfc_queue(prev, spu);            /* Step 25. */
1942 }
1943
1944 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1945 {
1946         /*
1947          * Perform steps 26-40 of SPU context restore sequence,
1948          * which restores regions of the local store and register
1949          * file.
1950          */
1951
1952         set_watchdog_timer(next, spu);          /* Step 26. */
1953         setup_spu_status_part1(next, spu);      /* Step 27. */
1954         setup_spu_status_part2(next, spu);      /* Step 28. */
1955         restore_mfc_rag(next, spu);             /* Step 29. */
1956         setup_mfc_slbs(next, spu);              /* Step 30. */
1957         set_spu_npc(next, spu);                 /* Step 31. */
1958         set_signot1(next, spu);                 /* Step 32. */
1959         set_signot2(next, spu);                 /* Step 33. */
1960         setup_decr(next, spu);                  /* Step 34. */
1961         setup_ppu_mb(next, spu);                /* Step 35. */
1962         setup_ppuint_mb(next, spu);             /* Step 36. */
1963         send_restore_code(next, spu);           /* Step 37. */
1964         set_ppu_querymask(next, spu);           /* Step 38. */
1965         wait_tag_complete(next, spu);           /* Step 39. */
1966         wait_spu_stopped(next, spu);            /* Step 40. */
1967 }
1968
1969 static void restore_csa(struct spu_state *next, struct spu *spu)
1970 {
1971         /*
1972          * Combine steps 41-76 of SPU context restore sequence, which
1973          * restore regions of the privileged & problem state areas.
1974          */
1975
1976         restore_spu_privcntl(next, spu);        /* Step 41. */
1977         restore_status_part1(next, spu);        /* Step 42. */
1978         restore_status_part2(next, spu);        /* Step 43. */
1979         restore_ls_16kb(next, spu);             /* Step 44. */
1980         wait_tag_complete(next, spu);           /* Step 45. */
1981         suspend_mfc(next, spu);                 /* Step 46. */
1982         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1983         issue_mfc_tlbie(next, spu);             /* Step 48. */
1984         clear_interrupts(next, spu);            /* Step 49. */
1985         restore_mfc_queues(next, spu);          /* Step 50. */
1986         restore_ppu_querymask(next, spu);       /* Step 51. */
1987         restore_ppu_querytype(next, spu);       /* Step 52. */
1988         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1989         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1990         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1991         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1992         set_llr_event(next, spu);               /* Step 57. */
1993         restore_decr_wrapped(next, spu);        /* Step 58. */
1994         restore_ch_part1(next, spu);            /* Step 59. */
1995         restore_ch_part2(next, spu);            /* Step 60. */
1996         restore_spu_lslr(next, spu);            /* Step 61. */
1997         restore_spu_cfg(next, spu);             /* Step 62. */
1998         restore_pm_trace(next, spu);            /* Step 63. */
1999         restore_spu_npc(next, spu);             /* Step 64. */
2000         restore_spu_mb(next, spu);              /* Step 65. */
2001         check_ppu_mb_stat(next, spu);           /* Step 66. */
2002         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2003         restore_mfc_slbs(next, spu);            /* Step 68. */
2004         restore_mfc_sr1(next, spu);             /* Step 69. */
2005         restore_other_spu_access(next, spu);    /* Step 70. */
2006         restore_spu_runcntl(next, spu);         /* Step 71. */
2007         restore_mfc_cntl(next, spu);            /* Step 72. */
2008         enable_user_access(next, spu);          /* Step 73. */
2009         reset_switch_active(next, spu);         /* Step 74. */
2010         reenable_interrupts(next, spu);         /* Step 75. */
2011 }
2012
2013 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2014 {
2015         int rc;
2016
2017         /*
2018          * SPU context save can be broken into three phases:
2019          *
2020          *     (a) quiesce [steps 2-16].
2021          *     (b) save of CSA, performed by PPE [steps 17-42]
2022          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2023          *
2024          * Returns      0 on success.
2025          *              2,6 if failed to quiece SPU
2026          *              53 if SPU-side of save failed.
2027          */
2028
2029         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2030         switch (rc) {
2031         default:
2032         case 2:
2033         case 6:
2034                 harvest(prev, spu);
2035                 return rc;
2036                 break;
2037         case 0:
2038                 break;
2039         }
2040         save_csa(prev, spu);                    /* Steps 17-43. */
2041         save_lscsa(prev, spu);                  /* Steps 44-53. */
2042         return check_save_status(prev, spu);    /* Step 54.     */
2043 }
2044
2045 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2046 {
2047         int rc;
2048
2049         /*
2050          * SPU context restore can be broken into three phases:
2051          *
2052          *    (a) harvest (or reset) SPU [steps 2-24].
2053          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2054          *    (c) restore CSA [steps 41-76], performed by PPE.
2055          *
2056          * The 'harvest' step is not performed here, but rather
2057          * as needed below.
2058          */
2059
2060         restore_lscsa(next, spu);               /* Steps 24-39. */
2061         rc = check_restore_status(next, spu);   /* Step 40.     */
2062         switch (rc) {
2063         default:
2064                 /* Failed. Return now. */
2065                 return rc;
2066                 break;
2067         case 0:
2068                 /* Fall through to next step. */
2069                 break;
2070         }
2071         restore_csa(next, spu);
2072
2073         return 0;
2074 }
2075
2076 /**
2077  * spu_save - SPU context save, with locking.
2078  * @prev: pointer to SPU context save area, to be saved.
2079  * @spu: pointer to SPU iomem structure.
2080  *
2081  * Acquire locks, perform the save operation then return.
2082  */
2083 int spu_save(struct spu_state *prev, struct spu *spu)
2084 {
2085         int rc;
2086
2087         acquire_spu_lock(spu);          /* Step 1.     */
2088         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2089         release_spu_lock(spu);
2090         if (rc) {
2091                 panic("%s failed on SPU[%d], rc=%d.\n",
2092                       __func__, spu->number, rc);
2093         }
2094         return rc;
2095 }
2096 EXPORT_SYMBOL_GPL(spu_save);
2097
2098 /**
2099  * spu_restore - SPU context restore, with harvest and locking.
2100  * @new: pointer to SPU context save area, to be restored.
2101  * @spu: pointer to SPU iomem structure.
2102  *
2103  * Perform harvest + restore, as we may not be coming
2104  * from a previous successful save operation, and the
2105  * hardware state is unknown.
2106  */
2107 int spu_restore(struct spu_state *new, struct spu *spu)
2108 {
2109         int rc;
2110
2111         acquire_spu_lock(spu);
2112         harvest(NULL, spu);
2113         spu->dar = 0;
2114         spu->dsisr = 0;
2115         spu->slb_replace = 0;
2116         spu->class_0_pending = 0;
2117         rc = __do_spu_restore(new, spu);
2118         release_spu_lock(spu);
2119         if (rc) {
2120                 panic("%s failed on SPU[%d] rc=%d.\n",
2121                        __func__, spu->number, rc);
2122         }
2123         return rc;
2124 }
2125 EXPORT_SYMBOL_GPL(spu_restore);
2126
2127 /**
2128  * spu_harvest - SPU harvest (reset) operation
2129  * @spu: pointer to SPU iomem structure.
2130  *
2131  * Perform SPU harvest (reset) operation.
2132  */
2133 void spu_harvest(struct spu *spu)
2134 {
2135         acquire_spu_lock(spu);
2136         harvest(NULL, spu);
2137         release_spu_lock(spu);
2138 }
2139
2140 static void init_prob(struct spu_state *csa)
2141 {
2142         csa->spu_chnlcnt_RW[9] = 1;
2143         csa->spu_chnlcnt_RW[21] = 16;
2144         csa->spu_chnlcnt_RW[23] = 1;
2145         csa->spu_chnlcnt_RW[28] = 1;
2146         csa->spu_chnlcnt_RW[30] = 1;
2147         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2148         csa->prob.mb_stat_R = 0x000400;
2149 }
2150
2151 static void init_priv1(struct spu_state *csa)
2152 {
2153         /* Enable decode, relocate, tlbie response, master runcntl. */
2154         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2155             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2156             MFC_STATE1_PROBLEM_STATE_MASK |
2157             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2158
2159         /* Set storage description.  */
2160         csa->priv1.mfc_sdr_RW = mfspr(SPRN_SDR1);
2161
2162         /* Enable OS-specific set of interrupts. */
2163         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2164             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2165             CLASS0_ENABLE_SPU_ERROR_INTR;
2166         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2167             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2168         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2169             CLASS2_ENABLE_SPU_HALT_INTR |
2170             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2171 }
2172
2173 static void init_priv2(struct spu_state *csa)
2174 {
2175         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2176         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2177             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2178             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2179 }
2180
2181 /**
2182  * spu_alloc_csa - allocate and initialize an SPU context save area.
2183  *
2184  * Allocate and initialize the contents of an SPU context save area.
2185  * This includes enabling address translation, interrupt masks, etc.,
2186  * as appropriate for the given OS environment.
2187  *
2188  * Note that storage for the 'lscsa' is allocated separately,
2189  * as it is by far the largest of the context save regions,
2190  * and may need to be pinned or otherwise specially aligned.
2191  */
2192 void spu_init_csa(struct spu_state *csa)
2193 {
2194         struct spu_lscsa *lscsa;
2195         unsigned char *p;
2196
2197         if (!csa)
2198                 return;
2199         memset(csa, 0, sizeof(struct spu_state));
2200
2201         lscsa = vmalloc(sizeof(struct spu_lscsa));
2202         if (!lscsa)
2203                 return;
2204
2205         memset(lscsa, 0, sizeof(struct spu_lscsa));
2206         csa->lscsa = lscsa;
2207         spin_lock_init(&csa->register_lock);
2208
2209         /* Set LS pages reserved to allow for user-space mapping. */
2210         for (p = lscsa->ls; p < lscsa->ls + LS_SIZE; p += PAGE_SIZE)
2211                 SetPageReserved(vmalloc_to_page(p));
2212
2213         init_prob(csa);
2214         init_priv1(csa);
2215         init_priv2(csa);
2216 }
2217 EXPORT_SYMBOL_GPL(spu_init_csa);
2218
2219 void spu_fini_csa(struct spu_state *csa)
2220 {
2221         /* Clear reserved bit before vfree. */
2222         unsigned char *p;
2223         for (p = csa->lscsa->ls; p < csa->lscsa->ls + LS_SIZE; p += PAGE_SIZE)
2224                 ClearPageReserved(vmalloc_to_page(p));
2225
2226         vfree(csa->lscsa);
2227 }
2228 EXPORT_SYMBOL_GPL(spu_fini_csa);