git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8377_mds.dts

   1 /*
   2  * MPC8377E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,mpc8377emds";
  16         compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8377@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;
  38                         i-cache-line-size = <32>;
  39                         d-cache-size = <32768>;
  40                         i-cache-size = <32768>;
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  50         };
  51
  52         localbus@e0005000 {
  53                 #address-cells = <2>;
  54                 #size-cells = <1>;
  55                 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  56                 reg = <0xe0005000 0x1000>;
  57                 interrupts = <77 0x8>;
  58                 interrupt-parent = <&ipic>;
  59
  60                 // booting from NOR flash
  61                 ranges = <0 0x0 0xfe000000 0x02000000
  62                           1 0x0 0xf8000000 0x00008000
  63                           3 0x0 0xe0600000 0x00008000>;
  64
  65                 flash@0,0 {
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         compatible = "cfi-flash";
  69                         reg = <0 0x0 0x2000000>;
  70                         bank-width = <2>;
  71                         device-width = <1>;
  72
  73                         u-boot@0 {
  74                                 reg = <0x0 0x100000>;
  75                                 read-only;
  76                         };
  77
  78                         fs@100000 {
  79                                 reg = <0x100000 0x800000>;
  80                         };
  81
  82                         kernel@1d00000 {
  83                                 reg = <0x1d00000 0x200000>;
  84                         };
  85
  86                         dtb@1f00000 {
  87                                 reg = <0x1f00000 0x100000>;
  88                         };
  89                 };
  90
  91                 bcsr@1,0 {
  92                         reg = <1 0x0 0x8000>;
  93                         compatible = "fsl,mpc837xmds-bcsr";
  94                 };
  95
  96                 nand@3,0 {
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         compatible = "fsl,mpc8377-fcm-nand",
 100                                      "fsl,elbc-fcm-nand";
 101                         reg = <3 0x0 0x8000>;
 102
 103                         u-boot@0 {
 104                                 reg = <0x0 0x100000>;
 105                                 read-only;
 106                         };
 107
 108                         kernel@100000 {
 109                                 reg = <0x100000 0x300000>;
 110                         };
 111
 112                         fs@400000 {
 113                                 reg = <0x400000 0x1c00000>;
 114                         };
 115                 };
 116         };
 117
 118         soc@e0000000 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 device_type = "soc";
 122                 compatible = "simple-bus";
 123                 ranges = <0x0 0xe0000000 0x00100000>;
 124                 reg = <0xe0000000 0x00000200>;
 125                 bus-frequency = <0>;
 126
 127                 wdt@200 {
 128                         compatible = "mpc83xx_wdt";
 129                         reg = <0x200 0x100>;
 130                 };
 131
 132                 i2c@3000 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         cell-index = <0>;
 136                         compatible = "fsl-i2c";
 137                         reg = <0x3000 0x100>;
 138                         interrupts = <14 0x8>;
 139                         interrupt-parent = <&ipic>;
 140                         dfsrr;
 141
 142                         rtc@68 {
 143                                 compatible = "dallas,ds1374";
 144                                 reg = <0x68>;
 145                                 interrupts = <19 0x8>;
 146                                 interrupt-parent = <&ipic>;
 147                         };
 148                 };
 149
 150                 i2c@3100 {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         cell-index = <1>;
 154                         compatible = "fsl-i2c";
 155                         reg = <0x3100 0x100>;
 156                         interrupts = <15 0x8>;
 157                         interrupt-parent = <&ipic>;
 158                         dfsrr;
 159                 };
 160
 161                 spi@7000 {
 162                         cell-index = <0>;
 163                         compatible = "fsl,spi";
 164                         reg = <0x7000 0x1000>;
 165                         interrupts = <16 0x8>;
 166                         interrupt-parent = <&ipic>;
 167                         mode = "cpu";
 168                 };
 169
 170                 usb@23000 {
 171                         compatible = "fsl-usb2-dr";
 172                         reg = <0x23000 0x1000>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         interrupt-parent = <&ipic>;
 176                         interrupts = <38 0x8>;
 177                         dr_mode = "host";
 178                         phy_type = "ulpi";
 179                 };
 180
 181                 mdio@24520 {
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         compatible = "fsl,gianfar-mdio";
 185                         reg = <0x24520 0x20>;
 186                         phy2: ethernet-phy@2 {
 187                                 interrupt-parent = <&ipic>;
 188                                 interrupts = <17 0x8>;
 189                                 reg = <0x2>;
 190                                 device_type = "ethernet-phy";
 191                         };
 192                         phy3: ethernet-phy@3 {
 193                                 interrupt-parent = <&ipic>;
 194                                 interrupts = <18 0x8>;
 195                                 reg = <0x3>;
 196                                 device_type = "ethernet-phy";
 197                         };
 198                         tbi0: tbi-phy@11 {
 199                                 reg = <0x11>;
 200                                 device_type = "tbi-phy";
 201                         };
 202                 };
 203
 204                 mdio@25520 {
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         compatible = "fsl,gianfar-tbi";
 208                         reg = <0x25520 0x20>;
 209
 210                         tbi1: tbi-phy@11 {
 211                                 reg = <0x11>;
 212                                 device_type = "tbi-phy";
 213                         };
 214                 };
 215
 216
 217                 enet0: ethernet@24000 {
 218                         cell-index = <0>;
 219                         device_type = "network";
 220                         model = "eTSEC";
 221                         compatible = "gianfar";
 222                         reg = <0x24000 0x1000>;
 223                         local-mac-address = [ 00 00 00 00 00 00 ];
 224                         interrupts = <32 0x8 33 0x8 34 0x8>;
 225                         phy-connection-type = "mii";
 226                         interrupt-parent = <&ipic>;
 227                         tbi-handle = <&tbi0>;
 228                         phy-handle = <&phy2>;
 229                 };
 230
 231                 enet1: ethernet@25000 {
 232                         cell-index = <1>;
 233                         device_type = "network";
 234                         model = "eTSEC";
 235                         compatible = "gianfar";
 236                         reg = <0x25000 0x1000>;
 237                         local-mac-address = [ 00 00 00 00 00 00 ];
 238                         interrupts = <35 0x8 36 0x8 37 0x8>;
 239                         phy-connection-type = "mii";
 240                         interrupt-parent = <&ipic>;
 241                         tbi-handle = <&tbi1>;
 242                         phy-handle = <&phy3>;
 243                 };
 244
 245                 serial0: serial@4500 {
 246                         cell-index = <0>;
 247                         device_type = "serial";
 248                         compatible = "ns16550";
 249                         reg = <0x4500 0x100>;
 250                         clock-frequency = <0>;
 251                         interrupts = <9 0x8>;
 252                         interrupt-parent = <&ipic>;
 253                 };
 254
 255                 serial1: serial@4600 {
 256                         cell-index = <1>;
 257                         device_type = "serial";
 258                         compatible = "ns16550";
 259                         reg = <0x4600 0x100>;
 260                         clock-frequency = <0>;
 261                         interrupts = <10 0x8>;
 262                         interrupt-parent = <&ipic>;
 263                 };
 264
 265                 dma@82a8 {
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                         compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
 269                         reg = <0x82a8 4>;
 270                         ranges = <0 0x8100 0x1a8>;
 271                         interrupt-parent = <&ipic>;
 272                         interrupts = <0x47 8>;
 273                         cell-index = <0>;
 274                         dma-channel@0 {
 275                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 276                                 reg = <0 0x80>;
 277                                 cell-index = <0>;
 278                                 interrupt-parent = <&ipic>;
 279                                 interrupts = <0x47 8>;
 280                         };
 281                         dma-channel@80 {
 282                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 283                                 reg = <0x80 0x80>;
 284                                 cell-index = <1>;
 285                                 interrupt-parent = <&ipic>;
 286                                 interrupts = <0x47 8>;
 287                         };
 288                         dma-channel@100 {
 289                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 290                                 reg = <0x100 0x80>;
 291                                 cell-index = <2>;
 292                                 interrupt-parent = <&ipic>;
 293                                 interrupts = <0x47 8>;
 294                         };
 295                         dma-channel@180 {
 296                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 297                                 reg = <0x180 0x28>;
 298                                 cell-index = <3>;
 299                                 interrupt-parent = <&ipic>;
 300                                 interrupts = <0x47 8>;
 301                         };
 302                 };
 303
 304                 crypto@30000 {
 305                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 306                                      "fsl,sec2.1", "fsl,sec2.0";
 307                         reg = <0x30000 0x10000>;
 308                         interrupts = <11 0x8>;
 309                         interrupt-parent = <&ipic>;
 310                         fsl,num-channels = <4>;
 311                         fsl,channel-fifo-len = <24>;
 312                         fsl,exec-units-mask = <0x9fe>;
 313                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 314                 };
 315
 316                 sdhc@2e000 {
 317                         model = "eSDHC";
 318                         compatible = "fsl,esdhc";
 319                         reg = <0x2e000 0x1000>;
 320                         interrupts = <42 0x8>;
 321                         interrupt-parent = <&ipic>;
 322                 };
 323
 324                 sata@18000 {
 325                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 326                         reg = <0x18000 0x1000>;
 327                         interrupts = <44 0x8>;
 328                         interrupt-parent = <&ipic>;
 329                 };
 330
 331                 sata@19000 {
 332                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 333                         reg = <0x19000 0x1000>;
 334                         interrupts = <45 0x8>;
 335                         interrupt-parent = <&ipic>;
 336                 };
 337
 338                 /* IPIC
 339                  * interrupts cell = <intr #, sense>
 340                  * sense values match linux IORESOURCE_IRQ_* defines:
 341                  * sense == 8: Level, low assertion
 342                  * sense == 2: Edge, high-to-low change
 343                  */
 344                 ipic: pic@700 {
 345                         compatible = "fsl,ipic";
 346                         interrupt-controller;
 347                         #address-cells = <0>;
 348                         #interrupt-cells = <2>;
 349                         reg = <0x700 0x100>;
 350                 };
 351         };
 352
 353         pci0: pci@e0008500 {
 354                 cell-index = <0>;
 355                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 356                 interrupt-map = <
 357
 358                                 /* IDSEL 0x11 */
 359                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 360                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 361                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 362                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 363
 364                                 /* IDSEL 0x12 */
 365                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 366                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 367                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 368                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 369
 370                                 /* IDSEL 0x13 */
 371                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 372                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 373                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 374                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 375
 376                                 /* IDSEL 0x15 */
 377                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 378                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 379                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 380                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 381
 382                                 /* IDSEL 0x16 */
 383                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 384                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 385                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 386                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 387
 388                                 /* IDSEL 0x17 */
 389                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 390                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 391                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 392                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 393
 394                                 /* IDSEL 0x18 */
 395                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 396                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 397                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 398                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 399                 interrupt-parent = <&ipic>;
 400                 interrupts = <66 0x8>;
 401                 bus-range = <0x0 0x0>;
 402                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 403                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 404                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 405                 clock-frequency = <0>;
 406                 #interrupt-cells = <1>;
 407                 #size-cells = <2>;
 408                 #address-cells = <3>;
 409                 reg = <0xe0008500 0x100         /* internal registers */
 410                        0xe0008300 0x8>;         /* config space access registers */
 411                 compatible = "fsl,mpc8349-pci";
 412                 device_type = "pci";
 413         };
 414
 415         pci1: pcie@e0009000 {
 416                 #address-cells = <3>;
 417                 #size-cells = <2>;
 418                 #interrupt-cells = <1>;
 419                 device_type = "pci";
 420                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 421                 reg = <0xe0009000 0x00001000>;
 422                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 423                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 424                 bus-range = <0 255>;
 425                 interrupt-map-mask = <0xf800 0 0 7>;
 426                 interrupt-map = <0 0 0 1 &ipic 1 8
 427                                  0 0 0 2 &ipic 1 8
 428                                  0 0 0 3 &ipic 1 8
 429                                  0 0 0 4 &ipic 1 8>;
 430                 clock-frequency = <0>;
 431
 432                 pcie@0 {
 433                         #address-cells = <3>;
 434                         #size-cells = <2>;
 435                         device_type = "pci";
 436                         reg = <0 0 0 0 0>;
 437                         ranges = <0x02000000 0 0xa8000000
 438                                   0x02000000 0 0xa8000000
 439                                   0 0x10000000
 440                                   0x01000000 0 0x00000000
 441                                   0x01000000 0 0x00000000
 442                                   0 0x00800000>;
 443                 };
 444         };
 445
 446         pci2: pcie@e000a000 {
 447                 #address-cells = <3>;
 448                 #size-cells = <2>;
 449                 #interrupt-cells = <1>;
 450                 device_type = "pci";
 451                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 452                 reg = <0xe000a000 0x00001000>;
 453                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 454                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 455                 bus-range = <0 255>;
 456                 interrupt-map-mask = <0xf800 0 0 7>;
 457                 interrupt-map = <0 0 0 1 &ipic 2 8
 458                                  0 0 0 2 &ipic 2 8
 459                                  0 0 0 3 &ipic 2 8
 460                                  0 0 0 4 &ipic 2 8>;
 461                 clock-frequency = <0>;
 462
 463                 pcie@0 {
 464                         #address-cells = <3>;
 465                         #size-cells = <2>;
 466                         device_type = "pci";
 467                         reg = <0 0 0 0 0>;
 468                         ranges = <0x02000000 0 0xc8000000
 469                                   0x02000000 0 0xc8000000
 470                                   0 0x10000000
 471                                   0x01000000 0 0x00000000
 472                                   0x01000000 0 0x00000000
 473                                   0 0x00800000>;
 474                 };
 475         };
 476 };