2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
15 #include <asm/processor.h>
18 #include <asm/sections.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/byteorder.h>
22 #include <asm/uaccess.h>
23 #include <asm/machdep.h>
28 #define DBG(x...) printk(x)
33 unsigned long isa_io_base = 0;
34 unsigned long isa_mem_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
49 static u8* pci_to_OF_bus_map;
52 /* By default, we don't re-assign bus numbers. We do this only on
55 int pci_assign_all_buses;
57 struct pci_controller* hose_head;
58 struct pci_controller** hose_tail = &hose_head;
60 static int pci_bus_count;
63 fixup_broken_pcnet32(struct pci_dev* dev)
65 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
66 dev->vendor = PCI_VENDOR_ID_AMD;
67 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
70 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
73 fixup_cpc710_pci64(struct pci_dev* dev)
75 /* Hide the PCI64 BARs from the kernel as their content doesn't
76 * fit well in the resource management
78 dev->resource[0].start = dev->resource[0].end = 0;
79 dev->resource[0].flags = 0;
80 dev->resource[1].start = dev->resource[1].end = 0;
81 dev->resource[1].flags = 0;
83 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
86 pcibios_fixup_resources(struct pci_dev *dev)
88 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
93 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
96 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
97 struct resource *res = dev->resource + i;
100 if (res->end == 0xffffffff) {
101 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
102 pci_name(dev), i, res->start, res->end);
103 res->end -= res->start;
105 res->flags |= IORESOURCE_UNSET;
109 if (res->flags & IORESOURCE_MEM) {
110 offset = hose->pci_mem_offset;
111 } else if (res->flags & IORESOURCE_IO) {
112 offset = (unsigned long) hose->io_base_virt
116 res->start += offset;
119 printk("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
120 i, res->flags, pci_name(dev),
121 res->start - offset, res->start);
126 /* Call machine specific resource fixup */
127 if (ppc_md.pcibios_fixup_resources)
128 ppc_md.pcibios_fixup_resources(dev);
130 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
132 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
133 struct resource *res)
135 unsigned long offset = 0;
136 struct pci_controller *hose = dev->sysdata;
138 if (hose && res->flags & IORESOURCE_IO)
139 offset = (unsigned long)hose->io_base_virt - isa_io_base;
140 else if (hose && res->flags & IORESOURCE_MEM)
141 offset = hose->pci_mem_offset;
142 region->start = res->start - offset;
143 region->end = res->end - offset;
145 EXPORT_SYMBOL(pcibios_resource_to_bus);
147 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
148 struct pci_bus_region *region)
150 unsigned long offset = 0;
151 struct pci_controller *hose = dev->sysdata;
153 if (hose && res->flags & IORESOURCE_IO)
154 offset = (unsigned long)hose->io_base_virt - isa_io_base;
155 else if (hose && res->flags & IORESOURCE_MEM)
156 offset = hose->pci_mem_offset;
157 res->start = region->start + offset;
158 res->end = region->end + offset;
160 EXPORT_SYMBOL(pcibios_bus_to_resource);
163 * We need to avoid collisions with `mirrored' VGA ports
164 * and other strange ISA hardware, so we always want the
165 * addresses to be allocated in the 0x000-0x0ff region
168 * Why? Because some silly external IO cards only decode
169 * the low 10 bits of the IO address. The 0x00-0xff region
170 * is reserved for motherboard devices that decode all 16
171 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
172 * but we want to try to avoid allocating at 0x2900-0x2bff
173 * which might have be mirrored at 0x0100-0x03ff..
175 void pcibios_align_resource(void *data, struct resource *res,
176 resource_size_t size, resource_size_t align)
178 struct pci_dev *dev = data;
180 if (res->flags & IORESOURCE_IO) {
181 resource_size_t start = res->start;
184 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
185 " (%lld bytes)\n", pci_name(dev),
186 dev->resource - res, (unsigned long long)size);
190 start = (start + 0x3ff) & ~0x3ff;
195 EXPORT_SYMBOL(pcibios_align_resource);
198 * Handle resources of PCI devices. If the world were perfect, we could
199 * just allocate all the resource regions and do nothing more. It isn't.
200 * On the other hand, we cannot just re-allocate all devices, as it would
201 * require us to know lots of host bridge internals. So we attempt to
202 * keep as much of the original configuration as possible, but tweak it
203 * when it's found to be wrong.
205 * Known BIOS problems we have to work around:
206 * - I/O or memory regions not configured
207 * - regions configured, but not enabled in the command register
208 * - bogus I/O addresses above 64K used
209 * - expansion ROMs left enabled (this may sound harmless, but given
210 * the fact the PCI specs explicitly allow address decoders to be
211 * shared between expansion ROMs and other resource regions, it's
212 * at least dangerous)
215 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
216 * This gives us fixed barriers on where we can allocate.
217 * (2) Allocate resources for all enabled devices. If there is
218 * a collision, just mark the resource as unallocated. Also
219 * disable expansion ROMs during this step.
220 * (3) Try to allocate resources for disabled devices. If the
221 * resources were assigned correctly, everything goes well,
222 * if they weren't, they won't disturb allocation of other
224 * (4) Assign new addresses to resources which were either
225 * not configured at all or misconfigured. If explicitly
226 * requested by the user, configure expansion ROM address
231 pcibios_allocate_bus_resources(struct list_head *bus_list)
235 struct resource *res, *pr;
237 /* Depth-First Search on bus tree */
238 list_for_each_entry(bus, bus_list, node) {
239 for (i = 0; i < 4; ++i) {
240 if ((res = bus->resource[i]) == NULL || !res->flags
241 || res->start > res->end)
243 if (bus->parent == NULL)
244 pr = (res->flags & IORESOURCE_IO)?
245 &ioport_resource: &iomem_resource;
247 pr = pci_find_parent_resource(bus->self, res);
249 /* this happens when the generic PCI
250 * code (wrongly) decides that this
251 * bridge is transparent -- paulus
257 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
258 res->start, res->end, res->flags, pr);
260 if (request_resource(pr, res) == 0)
263 * Must be a conflict with an existing entry.
264 * Move that entry (or entries) under the
265 * bridge resource and try again.
267 if (reparent_resources(pr, res) == 0)
270 printk(KERN_ERR "PCI: Cannot allocate resource region "
271 "%d of PCI bridge %d\n", i, bus->number);
272 if (pci_relocate_bridge_resource(bus, i))
273 bus->resource[i] = NULL;
275 pcibios_allocate_bus_resources(&bus->children);
280 * Reparent resource children of pr that conflict with res
281 * under res, and make res replace those children.
284 reparent_resources(struct resource *parent, struct resource *res)
286 struct resource *p, **pp;
287 struct resource **firstpp = NULL;
289 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
290 if (p->end < res->start)
292 if (res->end < p->start)
294 if (p->start < res->start || p->end > res->end)
295 return -1; /* not completely contained */
300 return -1; /* didn't find any conflicting entries? */
301 res->parent = parent;
302 res->child = *firstpp;
306 for (p = res->child; p != NULL; p = p->sibling) {
308 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
309 p->name, p->start, p->end, res->name);
315 * A bridge has been allocated a range which is outside the range
316 * of its parent bridge, so it needs to be moved.
319 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
321 struct resource *res, *pr, *conflict;
322 unsigned long try, size;
324 struct pci_bus *parent = bus->parent;
326 if (parent == NULL) {
327 /* shouldn't ever happen */
328 printk(KERN_ERR "PCI: can't move host bridge resource\n");
331 res = bus->resource[i];
335 for (j = 0; j < 4; j++) {
336 struct resource *r = parent->resource[j];
339 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
341 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
345 if (res->flags & IORESOURCE_PREFETCH)
350 size = res->end - res->start;
351 if (pr->start > pr->end || size > pr->end - pr->start)
355 res->start = try - size;
357 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
359 if (conflict->start <= pr->start + size)
361 try = conflict->start - 1;
363 if (request_resource(pr, res)) {
364 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
365 res->start, res->end);
366 return -1; /* "can't happen" */
368 update_bridge_base(bus, i);
369 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
370 bus->number, i, (unsigned long long)res->start,
371 (unsigned long long)res->end);
376 probe_resource(struct pci_bus *parent, struct resource *pr,
377 struct resource *res, struct resource **conflict)
384 for (r = pr->child; r != NULL; r = r->sibling) {
385 if (r->end >= res->start && res->end >= r->start) {
390 list_for_each_entry(bus, &parent->children, node) {
391 for (i = 0; i < 4; ++i) {
392 if ((r = bus->resource[i]) == NULL)
394 if (!r->flags || r->start > r->end || r == res)
396 if (pci_find_parent_resource(bus->self, r) != pr)
398 if (r->end >= res->start && res->end >= r->start) {
404 list_for_each_entry(dev, &parent->devices, bus_list) {
405 for (i = 0; i < 6; ++i) {
406 r = &dev->resource[i];
407 if (!r->flags || (r->flags & IORESOURCE_UNSET))
409 if (pci_find_parent_resource(dev, r) != pr)
411 if (r->end >= res->start && res->end >= r->start) {
421 update_bridge_base(struct pci_bus *bus, int i)
423 struct resource *res = bus->resource[i];
424 u8 io_base_lo, io_limit_lo;
425 u16 mem_base, mem_limit;
427 unsigned long start, end, off;
428 struct pci_dev *dev = bus->self;
429 struct pci_controller *hose = dev->sysdata;
432 printk("update_bridge_base: no hose?\n");
435 pci_read_config_word(dev, PCI_COMMAND, &cmd);
436 pci_write_config_word(dev, PCI_COMMAND,
437 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
438 if (res->flags & IORESOURCE_IO) {
439 off = (unsigned long) hose->io_base_virt - isa_io_base;
440 start = res->start - off;
441 end = res->end - off;
442 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
443 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
445 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
447 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
449 io_base_lo |= PCI_IO_RANGE_TYPE_32;
451 io_base_lo |= PCI_IO_RANGE_TYPE_16;
452 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
453 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
455 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
457 off = hose->pci_mem_offset;
458 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
459 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
460 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
461 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
463 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
464 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
465 off = hose->pci_mem_offset;
466 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
467 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
468 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
469 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
472 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
473 pci_name(dev), i, res->flags);
475 pci_write_config_word(dev, PCI_COMMAND, cmd);
478 static inline void alloc_resource(struct pci_dev *dev, int idx)
480 struct resource *pr, *r = &dev->resource[idx];
482 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
483 pci_name(dev), idx, r->start, r->end, r->flags);
484 pr = pci_find_parent_resource(dev, r);
485 if (!pr || request_resource(pr, r) < 0) {
486 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
487 " of device %s\n", idx, pci_name(dev));
489 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
490 pr, pr->start, pr->end, pr->flags);
491 /* We'll assign a new address later */
492 r->flags |= IORESOURCE_UNSET;
499 pcibios_allocate_resources(int pass)
501 struct pci_dev *dev = NULL;
506 for_each_pci_dev(dev) {
507 pci_read_config_word(dev, PCI_COMMAND, &command);
508 for (idx = 0; idx < 6; idx++) {
509 r = &dev->resource[idx];
510 if (r->parent) /* Already allocated */
512 if (!r->flags || (r->flags & IORESOURCE_UNSET))
513 continue; /* Not assigned at all */
514 if (r->flags & IORESOURCE_IO)
515 disabled = !(command & PCI_COMMAND_IO);
517 disabled = !(command & PCI_COMMAND_MEMORY);
518 if (pass == disabled)
519 alloc_resource(dev, idx);
523 r = &dev->resource[PCI_ROM_RESOURCE];
524 if (r->flags & IORESOURCE_ROM_ENABLE) {
525 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
527 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
528 r->flags &= ~IORESOURCE_ROM_ENABLE;
529 pci_read_config_dword(dev, dev->rom_base_reg, ®);
530 pci_write_config_dword(dev, dev->rom_base_reg,
531 reg & ~PCI_ROM_ADDRESS_ENABLE);
537 pcibios_assign_resources(void)
539 struct pci_dev *dev = NULL;
543 for_each_pci_dev(dev) {
544 int class = dev->class >> 8;
546 /* Don't touch classless devices and host bridges */
547 if (!class || class == PCI_CLASS_BRIDGE_HOST)
550 for (idx = 0; idx < 6; idx++) {
551 r = &dev->resource[idx];
554 * We shall assign a new address to this resource,
555 * either because the BIOS (sic) forgot to do so
556 * or because we have decided the old address was
557 * unusable for some reason.
559 if ((r->flags & IORESOURCE_UNSET) && r->end &&
560 (!ppc_md.pcibios_enable_device_hook ||
561 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
562 r->flags &= ~IORESOURCE_UNSET;
563 pci_assign_resource(dev, idx);
567 #if 0 /* don't assign ROMs */
568 r = &dev->resource[PCI_ROM_RESOURCE];
572 pci_assign_resource(dev, PCI_ROM_RESOURCE);
579 pcibios_enable_resources(struct pci_dev *dev, int mask)
585 pci_read_config_word(dev, PCI_COMMAND, &cmd);
587 for (idx=0; idx<6; idx++) {
588 /* Only set up the requested stuff */
589 if (!(mask & (1<<idx)))
592 r = &dev->resource[idx];
593 if (r->flags & IORESOURCE_UNSET) {
594 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
597 if (r->flags & IORESOURCE_IO)
598 cmd |= PCI_COMMAND_IO;
599 if (r->flags & IORESOURCE_MEM)
600 cmd |= PCI_COMMAND_MEMORY;
602 if (dev->resource[PCI_ROM_RESOURCE].start)
603 cmd |= PCI_COMMAND_MEMORY;
604 if (cmd != old_cmd) {
605 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
606 pci_write_config_word(dev, PCI_COMMAND, cmd);
611 static int next_controller_index;
613 struct pci_controller * __init
614 pcibios_alloc_controller(void)
616 struct pci_controller *hose;
618 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
619 memset(hose, 0, sizeof(struct pci_controller));
622 hose_tail = &hose->next;
624 hose->index = next_controller_index++;
631 * Functions below are used on OpenFirmware machines.
634 make_one_node_map(struct device_node* node, u8 pci_bus)
639 if (pci_bus >= pci_bus_count)
641 bus_range = (int *) get_property(node, "bus-range", &len);
642 if (bus_range == NULL || len < 2 * sizeof(int)) {
643 printk(KERN_WARNING "Can't get bus-range for %s, "
644 "assuming it starts at 0\n", node->full_name);
645 pci_to_OF_bus_map[pci_bus] = 0;
647 pci_to_OF_bus_map[pci_bus] = bus_range[0];
649 for (node=node->child; node != 0;node = node->sibling) {
651 unsigned int *class_code, *reg;
653 class_code = (unsigned int *) get_property(node, "class-code", NULL);
654 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
655 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
657 reg = (unsigned int *)get_property(node, "reg", NULL);
660 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
661 if (!dev || !dev->subordinate)
663 make_one_node_map(node, dev->subordinate->number);
668 pcibios_make_OF_bus_map(void)
671 struct pci_controller* hose;
674 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
675 if (!pci_to_OF_bus_map) {
676 printk(KERN_ERR "Can't allocate OF bus map !\n");
680 /* We fill the bus map with invalid values, that helps
683 for (i=0; i<pci_bus_count; i++)
684 pci_to_OF_bus_map[i] = 0xff;
686 /* For each hose, we begin searching bridges */
687 for(hose=hose_head; hose; hose=hose->next) {
688 struct device_node* node;
689 node = (struct device_node *)hose->arch_data;
692 make_one_node_map(node, hose->first_busno);
694 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", NULL);
696 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
698 printk("PCI->OF bus map:\n");
699 for (i=0; i<pci_bus_count; i++) {
700 if (pci_to_OF_bus_map[i] == 0xff)
702 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
707 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
709 static struct device_node*
710 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
712 struct device_node* sub_node;
714 for (; node != 0;node = node->sibling) {
715 unsigned int *class_code;
717 if (filter(node, data))
720 /* For PCI<->PCI bridges or CardBus bridges, we go down
721 * Note: some OFs create a parent node "multifunc-device" as
722 * a fake root for all functions of a multi-function device,
723 * we go down them as well.
725 class_code = (unsigned int *) get_property(node, "class-code", NULL);
726 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
727 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
728 strcmp(node->name, "multifunc-device"))
730 sub_node = scan_OF_pci_childs(node->child, filter, data);
738 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
741 u8* fdata = (u8*)data;
743 reg = (unsigned int *) get_property(node, "reg", NULL);
744 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
745 && ((reg[0] >> 16) & 0xff) == fdata[0])
750 static struct device_node*
751 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
753 u8 filter_data[2] = {bus, dev_fn};
755 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
759 * Scans the OF tree for a device node matching a PCI device
762 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
764 struct pci_controller *hose;
765 struct device_node *node;
771 /* Lookup the hose */
773 hose = pci_bus_to_hose(busnr);
777 /* Check it has an OF node associated */
778 node = (struct device_node *) hose->arch_data;
782 /* Fixup bus number according to what OF think it is. */
783 #ifdef CONFIG_PPC_PMAC
784 /* The G5 need a special case here. Basically, we don't remap all
785 * busses on it so we don't create the pci-OF-map. However, we do
786 * remap the AGP bus and so have to deal with it. A future better
787 * fix has to be done by making the remapping per-host and always
788 * filling the pci_to_OF map. --BenH
790 if (machine_is(powermac) && busnr >= 0xf0)
794 if (pci_to_OF_bus_map)
795 busnr = pci_to_OF_bus_map[busnr];
799 /* Now, lookup childs of the hose */
800 return scan_OF_childs_for_device(node->child, busnr, devfn);
802 EXPORT_SYMBOL(pci_busdev_to_OF_node);
805 pci_device_to_OF_node(struct pci_dev *dev)
807 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
809 EXPORT_SYMBOL(pci_device_to_OF_node);
811 /* This routine is meant to be used early during boot, when the
812 * PCI bus numbers have not yet been assigned, and you need to
813 * issue PCI config cycles to an OF device.
814 * It could also be used to "fix" RTAS config cycles if you want
815 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
818 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
823 struct pci_controller* hose;
824 for (hose=hose_head;hose;hose=hose->next)
825 if (hose->arch_data == node)
833 find_OF_pci_device_filter(struct device_node* node, void* data)
835 return ((void *)node == data);
839 * Returns the PCI device matching a given OF node
842 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
845 struct pci_controller* hose;
846 struct pci_dev* dev = NULL;
850 /* Make sure it's really a PCI device */
851 hose = pci_find_hose_for_OF_device(node);
852 if (!hose || !hose->arch_data)
854 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
855 find_OF_pci_device_filter, (void *)node))
857 reg = (unsigned int *) get_property(node, "reg", NULL);
860 *bus = (reg[0] >> 16) & 0xff;
861 *devfn = ((reg[0] >> 8) & 0xff);
863 /* Ok, here we need some tweak. If we have already renumbered
864 * all busses, we can't rely on the OF bus number any more.
865 * the pci_to_OF_bus_map is not enough as several PCI busses
866 * may match the same OF bus number.
868 if (!pci_to_OF_bus_map)
871 for_each_pci_dev(dev)
872 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
873 dev->devfn == *devfn) {
874 *bus = dev->bus->number;
881 EXPORT_SYMBOL(pci_device_from_OF_node);
884 pci_process_bridge_OF_ranges(struct pci_controller *hose,
885 struct device_node *dev, int primary)
887 static unsigned int static_lc_ranges[256] __initdata;
888 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
890 int rlen = 0, orig_rlen;
892 struct resource *res;
893 int np, na = prom_n_addr_cells(dev);
896 /* First we try to merge ranges to fix a problem with some pmacs
897 * that can have more than 3 ranges, fortunately using contiguous
900 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
903 /* Sanity check, though hopefully that never happens */
904 if (rlen > sizeof(static_lc_ranges)) {
905 printk(KERN_WARNING "OF ranges property too large !\n");
906 rlen = sizeof(static_lc_ranges);
908 lc_ranges = static_lc_ranges;
909 memcpy(lc_ranges, dt_ranges, rlen);
912 /* Let's work on a copy of the "ranges" property instead of damaging
913 * the device-tree image in memory
917 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
919 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
920 (prev[2] + prev[na+4]) == ranges[2] &&
921 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
922 prev[na+4] += ranges[na+4];
933 * The ranges property is laid out as an array of elements,
934 * each of which comprises:
935 * cells 0 - 2: a PCI address
936 * cells 3 or 3+4: a CPU physical address
937 * (size depending on dev->n_addr_cells)
938 * cells 4+5 or 5+6: the size of the range
942 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
945 switch ((ranges[0] >> 24) & 0x3) {
946 case 1: /* I/O space */
949 hose->io_base_phys = ranges[na+2];
950 /* limit I/O space to 16MB */
951 if (size > 0x01000000)
953 hose->io_base_virt = ioremap(ranges[na+2], size);
955 isa_io_base = (unsigned long) hose->io_base_virt;
956 res = &hose->io_resource;
957 res->flags = IORESOURCE_IO;
958 res->start = ranges[2];
959 DBG("PCI: IO 0x%llx -> 0x%llx\n",
960 res->start, res->start + size - 1);
962 case 2: /* memory space */
964 if (ranges[1] == 0 && ranges[2] == 0
965 && ranges[na+4] <= (16 << 20)) {
966 /* 1st 16MB, i.e. ISA memory area */
968 isa_mem_base = ranges[na+2];
971 while (memno < 3 && hose->mem_resources[memno].flags)
974 hose->pci_mem_offset = ranges[na+2] - ranges[2];
976 res = &hose->mem_resources[memno];
977 res->flags = IORESOURCE_MEM;
978 if(ranges[0] & 0x40000000)
979 res->flags |= IORESOURCE_PREFETCH;
980 res->start = ranges[na+2];
981 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
982 res->start, res->start + size - 1);
987 res->name = dev->full_name;
988 res->end = res->start + size - 1;
997 /* We create the "pci-OF-bus-map" property now so it appears in the
1001 pci_create_OF_bus_map(void)
1003 struct property* of_prop;
1005 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1006 if (of_prop && find_path_device("/")) {
1007 memset(of_prop, -1, sizeof(struct property) + 256);
1008 of_prop->name = "pci-OF-bus-map";
1009 of_prop->length = 256;
1010 of_prop->value = (unsigned char *)&of_prop[1];
1011 prom_add_property(find_path_device("/"), of_prop);
1015 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1017 struct pci_dev *pdev;
1018 struct device_node *np;
1020 pdev = to_pci_dev (dev);
1021 np = pci_device_to_OF_node(pdev);
1022 if (np == NULL || np->full_name == NULL)
1024 return sprintf(buf, "%s", np->full_name);
1026 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1028 #else /* CONFIG_PPC_OF */
1029 void pcibios_make_OF_bus_map(void)
1032 #endif /* CONFIG_PPC_OF */
1034 /* Add sysfs properties */
1035 void pcibios_add_platform_entries(struct pci_dev *pdev)
1037 #ifdef CONFIG_PPC_OF
1038 device_create_file(&pdev->dev, &dev_attr_devspec);
1039 #endif /* CONFIG_PPC_OF */
1043 #ifdef CONFIG_PPC_PMAC
1045 * This set of routines checks for PCI<->PCI bridges that have closed
1046 * IO resources and have child devices. It tries to re-open an IO
1049 * This is a _temporary_ fix to workaround a problem with Apple's OF
1050 * closing IO windows on P2P bridges when the OF drivers of cards
1051 * below this bridge don't claim any IO range (typically ATI or
1054 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1055 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1056 * ordering when creating the host bus resources, and maybe a few more
1060 /* Initialize bridges with base/limit values we have collected */
1062 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1064 struct pci_dev *bridge = bus->self;
1065 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1068 struct resource res;
1070 if (bus->resource[0] == NULL)
1072 res = *(bus->resource[0]);
1074 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1075 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1076 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1077 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
1079 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1080 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1082 l |= (res.start >> 8) & 0x00f0;
1083 l |= res.end & 0xf000;
1084 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1086 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1087 l = (res.start >> 16) | (res.end & 0xffff0000);
1088 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1091 pci_read_config_word(bridge, PCI_COMMAND, &w);
1092 w |= PCI_COMMAND_IO;
1093 pci_write_config_word(bridge, PCI_COMMAND, w);
1095 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1097 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1098 w |= PCI_BRIDGE_CTL_VGA;
1099 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1104 /* This function is pretty basic and actually quite broken for the
1105 * general case, it's enough for us right now though. It's supposed
1106 * to tell us if we need to open an IO range at all or not and what
1110 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1112 struct pci_dev *dev;
1116 #define push_end(res, mask) do { \
1117 BUG_ON((mask+1) & mask); \
1118 res->end = (res->end + mask) | mask; \
1121 list_for_each_entry(dev, &bus->devices, bus_list) {
1122 u16 class = dev->class >> 8;
1124 if (class == PCI_CLASS_DISPLAY_VGA ||
1125 class == PCI_CLASS_NOT_DEFINED_VGA)
1127 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1128 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1129 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1130 push_end(res, 0xfff);
1132 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1134 unsigned long r_size;
1136 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1137 && i >= PCI_BRIDGE_RESOURCES)
1139 r = &dev->resource[i];
1140 r_size = r->end - r->start;
1143 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1145 push_end(res, r_size);
1153 /* Here we scan all P2P bridges of a given level that have a closed
1154 * IO window. Note that the test for the presence of a VGA card should
1155 * be improved to take into account already configured P2P bridges,
1156 * currently, we don't see them and might end up configuring 2 bridges
1157 * with VGA pass through enabled
1160 do_fixup_p2p_level(struct pci_bus *bus)
1166 for (parent_io=0; parent_io<4; parent_io++)
1167 if (bus->resource[parent_io]
1168 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1173 list_for_each_entry(b, &bus->children, node) {
1174 struct pci_dev *d = b->self;
1175 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1176 struct resource *res = b->resource[0];
1177 struct resource tmp_res;
1181 memset(&tmp_res, 0, sizeof(tmp_res));
1182 tmp_res.start = bus->resource[parent_io]->start;
1184 /* We don't let low addresses go through that closed P2P bridge, well,
1185 * that may not be necessary but I feel safer that way
1187 if (tmp_res.start == 0)
1188 tmp_res.start = 0x1000;
1190 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1191 res != bus->resource[parent_io] &&
1192 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1193 check_for_io_childs(b, &tmp_res, &found_vga)) {
1196 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1200 printk(KERN_WARNING "Skipping VGA, already active"
1201 " on bus segment\n");
1206 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1208 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1209 max = ((unsigned long) hose->io_base_virt
1210 - isa_io_base) + 0xffffffff;
1212 max = ((unsigned long) hose->io_base_virt
1213 - isa_io_base) + 0xffff;
1216 res->flags = IORESOURCE_IO;
1217 res->name = b->name;
1219 /* Find a resource in the parent where we can allocate */
1220 for (i = 0 ; i < 4; i++) {
1221 struct resource *r = bus->resource[i];
1224 if ((r->flags & IORESOURCE_IO) == 0)
1226 DBG("Trying to allocate from %016llx, size %016llx from parent"
1227 " res %d: %016llx -> %016llx\n",
1228 res->start, res->end, i, r->start, r->end);
1230 if (allocate_resource(r, res, res->end + 1, res->start, max,
1231 res->end + 1, NULL, NULL) < 0) {
1235 do_update_p2p_io_resource(b, found_vga);
1239 do_fixup_p2p_level(b);
1244 pcibios_fixup_p2p_bridges(void)
1248 list_for_each_entry(b, &pci_root_buses, node)
1249 do_fixup_p2p_level(b);
1252 #endif /* CONFIG_PPC_PMAC */
1257 struct pci_controller *hose;
1258 struct pci_bus *bus;
1261 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1263 /* Scan all of the recorded PCI controllers. */
1264 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1265 if (pci_assign_all_buses)
1266 hose->first_busno = next_busno;
1267 hose->last_busno = 0xff;
1268 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1269 hose->last_busno = bus->subordinate;
1270 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1271 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1273 pci_bus_count = next_busno;
1275 /* OpenFirmware based machines need a map of OF bus
1276 * numbers vs. kernel bus numbers since we may have to
1279 if (pci_assign_all_buses && have_of)
1280 pcibios_make_OF_bus_map();
1282 /* Do machine dependent PCI interrupt routing */
1283 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1284 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1286 /* Call machine dependent fixup */
1287 if (ppc_md.pcibios_fixup)
1288 ppc_md.pcibios_fixup();
1290 /* Allocate and assign resources */
1291 pcibios_allocate_bus_resources(&pci_root_buses);
1292 pcibios_allocate_resources(0);
1293 pcibios_allocate_resources(1);
1294 #ifdef CONFIG_PPC_PMAC
1295 pcibios_fixup_p2p_bridges();
1296 #endif /* CONFIG_PPC_PMAC */
1297 pcibios_assign_resources();
1299 /* Call machine dependent post-init code */
1300 if (ppc_md.pcibios_after_init)
1301 ppc_md.pcibios_after_init();
1306 subsys_initcall(pcibios_init);
1308 unsigned char __init
1309 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1311 struct pci_controller *hose = dev->sysdata;
1313 if (dev->bus->number != hose->first_busno) {
1316 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1317 /* Move up the chain of bridges. */
1318 dev = dev->bus->self;
1319 } while (dev->bus->self);
1322 /* The slot is the idsel of the last bridge. */
1324 return PCI_SLOT(dev->devfn);
1327 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1328 unsigned long start, unsigned long size)
1333 void __init pcibios_fixup_bus(struct pci_bus *bus)
1335 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1336 unsigned long io_offset;
1337 struct resource *res;
1340 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1341 if (bus->parent == NULL) {
1342 /* This is a host bridge - fill in its resources */
1345 bus->resource[0] = res = &hose->io_resource;
1348 printk(KERN_ERR "I/O resource not set for host"
1349 " bridge %d\n", hose->index);
1351 res->end = IO_SPACE_LIMIT;
1352 res->flags = IORESOURCE_IO;
1354 res->start += io_offset;
1355 res->end += io_offset;
1357 for (i = 0; i < 3; ++i) {
1358 res = &hose->mem_resources[i];
1362 printk(KERN_ERR "Memory resource not set for "
1363 "host bridge %d\n", hose->index);
1364 res->start = hose->pci_mem_offset;
1366 res->flags = IORESOURCE_MEM;
1368 bus->resource[i+1] = res;
1371 /* This is a subordinate bridge */
1372 pci_read_bridge_bases(bus);
1374 for (i = 0; i < 4; ++i) {
1375 if ((res = bus->resource[i]) == NULL)
1379 if (io_offset && (res->flags & IORESOURCE_IO)) {
1380 res->start += io_offset;
1381 res->end += io_offset;
1382 } else if (hose->pci_mem_offset
1383 && (res->flags & IORESOURCE_MEM)) {
1384 res->start += hose->pci_mem_offset;
1385 res->end += hose->pci_mem_offset;
1390 if (ppc_md.pcibios_fixup_bus)
1391 ppc_md.pcibios_fixup_bus(bus);
1394 char __init *pcibios_setup(char *str)
1399 /* the next one is stolen from the alpha port... */
1401 pcibios_update_irq(struct pci_dev *dev, int irq)
1403 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1404 /* XXX FIXME - update OF device tree node interrupt property */
1407 #ifdef CONFIG_PPC_MERGE
1408 /* XXX This is a copy of the ppc64 version. This is temporary until we start
1409 * merging the 2 PCI layers
1412 * Reads the interrupt pin to determine if interrupt is use by card.
1413 * If the interrupt is used, then gets the interrupt line from the
1414 * openfirmware and sets it in the pci_dev and pci_config line.
1416 int pci_read_irq_line(struct pci_dev *pci_dev)
1421 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1423 if (of_irq_map_pci(pci_dev, &oirq)) {
1424 DBG(" -> failed !\n");
1428 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1429 oirq.size, oirq.specifier[0], oirq.controller->full_name);
1431 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, oirq.size);
1432 if(virq == NO_IRQ) {
1433 DBG(" -> failed to map !\n");
1436 pci_dev->irq = virq;
1437 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1441 EXPORT_SYMBOL(pci_read_irq_line);
1442 #endif /* CONFIG_PPC_MERGE */
1444 int pcibios_enable_device(struct pci_dev *dev, int mask)
1450 if (ppc_md.pcibios_enable_device_hook)
1451 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1454 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1456 for (idx=0; idx<6; idx++) {
1457 r = &dev->resource[idx];
1458 if (r->flags & IORESOURCE_UNSET) {
1459 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1462 if (r->flags & IORESOURCE_IO)
1463 cmd |= PCI_COMMAND_IO;
1464 if (r->flags & IORESOURCE_MEM)
1465 cmd |= PCI_COMMAND_MEMORY;
1467 if (cmd != old_cmd) {
1468 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1469 pci_name(dev), old_cmd, cmd);
1470 pci_write_config_word(dev, PCI_COMMAND, cmd);
1475 struct pci_controller*
1476 pci_bus_to_hose(int bus)
1478 struct pci_controller* hose = hose_head;
1480 for (; hose; hose = hose->next)
1481 if (bus >= hose->first_busno && bus <= hose->last_busno)
1487 pci_bus_io_base(unsigned int bus)
1489 struct pci_controller *hose;
1491 hose = pci_bus_to_hose(bus);
1494 return hose->io_base_virt;
1498 pci_bus_io_base_phys(unsigned int bus)
1500 struct pci_controller *hose;
1502 hose = pci_bus_to_hose(bus);
1505 return hose->io_base_phys;
1509 pci_bus_mem_base_phys(unsigned int bus)
1511 struct pci_controller *hose;
1513 hose = pci_bus_to_hose(bus);
1516 return hose->pci_mem_offset;
1520 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1522 /* Hack alert again ! See comments in chrp_pci.c
1524 struct pci_controller* hose =
1525 (struct pci_controller *)pdev->sysdata;
1526 if (hose && res->flags & IORESOURCE_MEM)
1527 return res->start - hose->pci_mem_offset;
1528 /* We may want to do something with IOs here... */
1533 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1534 unsigned long *offset,
1535 enum pci_mmap_state mmap_state)
1537 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1538 unsigned long io_offset = 0;
1542 return NULL; /* should never happen */
1544 /* If memory, add on the PCI bridge address offset */
1545 if (mmap_state == pci_mmap_mem) {
1546 *offset += hose->pci_mem_offset;
1547 res_bit = IORESOURCE_MEM;
1549 io_offset = hose->io_base_virt - ___IO_BASE;
1550 *offset += io_offset;
1551 res_bit = IORESOURCE_IO;
1555 * Check that the offset requested corresponds to one of the
1556 * resources of the device.
1558 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1559 struct resource *rp = &dev->resource[i];
1560 int flags = rp->flags;
1562 /* treat ROM as memory (should be already) */
1563 if (i == PCI_ROM_RESOURCE)
1564 flags |= IORESOURCE_MEM;
1566 /* Active and same type? */
1567 if ((flags & res_bit) == 0)
1570 /* In the range of this resource? */
1571 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1574 /* found it! construct the final physical address */
1575 if (mmap_state == pci_mmap_io)
1576 *offset += hose->io_base_phys - io_offset;
1584 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1587 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1588 pgprot_t protection,
1589 enum pci_mmap_state mmap_state,
1592 unsigned long prot = pgprot_val(protection);
1594 /* Write combine is always 0 on non-memory space mappings. On
1595 * memory space, if the user didn't pass 1, we check for a
1596 * "prefetchable" resource. This is a bit hackish, but we use
1597 * this to workaround the inability of /sysfs to provide a write
1600 if (mmap_state != pci_mmap_mem)
1602 else if (write_combine == 0) {
1603 if (rp->flags & IORESOURCE_PREFETCH)
1607 /* XXX would be nice to have a way to ask for write-through */
1608 prot |= _PAGE_NO_CACHE;
1610 prot &= ~_PAGE_GUARDED;
1612 prot |= _PAGE_GUARDED;
1614 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev),
1615 (unsigned long long)rp->start, prot);
1617 return __pgprot(prot);
1621 * This one is used by /dev/mem and fbdev who have no clue about the
1622 * PCI device, it tries to find the PCI device first and calls the
1625 pgprot_t pci_phys_mem_access_prot(struct file *file,
1628 pgprot_t protection)
1630 struct pci_dev *pdev = NULL;
1631 struct resource *found = NULL;
1632 unsigned long prot = pgprot_val(protection);
1633 unsigned long offset = pfn << PAGE_SHIFT;
1636 if (page_is_ram(pfn))
1639 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1641 for_each_pci_dev(pdev) {
1642 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1643 struct resource *rp = &pdev->resource[i];
1644 int flags = rp->flags;
1646 /* Active and same type? */
1647 if ((flags & IORESOURCE_MEM) == 0)
1649 /* In the range of this resource? */
1650 if (offset < (rp->start & PAGE_MASK) ||
1660 if (found->flags & IORESOURCE_PREFETCH)
1661 prot &= ~_PAGE_GUARDED;
1665 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1667 return __pgprot(prot);
1672 * Perform the actual remap of the pages for a PCI device mapping, as
1673 * appropriate for this architecture. The region in the process to map
1674 * is described by vm_start and vm_end members of VMA, the base physical
1675 * address is found in vm_pgoff.
1676 * The pci device structure is provided so that architectures may make mapping
1677 * decisions on a per-device or per-bus basis.
1679 * Returns a negative error code on failure, zero on success.
1681 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1682 enum pci_mmap_state mmap_state,
1685 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1686 struct resource *rp;
1689 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1693 vma->vm_pgoff = offset >> PAGE_SHIFT;
1694 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1696 mmap_state, write_combine);
1698 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1699 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1704 /* Obsolete functions. Should be removed once the symbios driver
1708 phys_to_bus(unsigned long pa)
1710 struct pci_controller *hose;
1713 for (hose = hose_head; hose; hose = hose->next) {
1714 for (i = 0; i < 3; ++i) {
1715 if (pa >= hose->mem_resources[i].start
1716 && pa <= hose->mem_resources[i].end) {
1718 * XXX the hose->pci_mem_offset really
1719 * only applies to mem_resources[0].
1720 * We need a way to store an offset for
1721 * the others. -- paulus
1724 pa -= hose->pci_mem_offset;
1729 /* hmmm, didn't find it */
1734 pci_phys_to_bus(unsigned long pa, int busnr)
1736 struct pci_controller* hose = pci_bus_to_hose(busnr);
1739 return pa - hose->pci_mem_offset;
1743 pci_bus_to_phys(unsigned int ba, int busnr)
1745 struct pci_controller* hose = pci_bus_to_hose(busnr);
1748 return ba + hose->pci_mem_offset;
1751 /* Provide information on locations of various I/O regions in physical
1752 * memory. Do this on a per-card basis so that we choose the right
1754 * Note that the returned IO or memory base is a physical address
1757 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1759 struct pci_controller* hose;
1760 long result = -EOPNOTSUPP;
1762 /* Argh ! Please forgive me for that hack, but that's the
1763 * simplest way to get existing XFree to not lockup on some
1764 * G5 machines... So when something asks for bus 0 io base
1765 * (bus 0 is HT root), we return the AGP one instead.
1767 #ifdef CONFIG_PPC_PMAC
1768 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1771 #endif /* CONFIG_PPC_PMAC */
1773 hose = pci_bus_to_hose(bus);
1778 case IOBASE_BRIDGE_NUMBER:
1779 return (long)hose->first_busno;
1781 return (long)hose->pci_mem_offset;
1783 return (long)hose->io_base_phys;
1785 return (long)isa_io_base;
1786 case IOBASE_ISA_MEM:
1787 return (long)isa_mem_base;
1793 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1794 const struct resource *rsrc,
1795 resource_size_t *start, resource_size_t *end)
1797 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1798 unsigned long offset = 0;
1803 if (rsrc->flags & IORESOURCE_IO)
1804 offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys;
1806 *start = rsrc->start + offset;
1807 *end = rsrc->end + offset;
1811 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1812 int flags, char *name)
1819 res->sibling = NULL;
1823 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1825 unsigned long start = pci_resource_start(dev, bar);
1826 unsigned long len = pci_resource_len(dev, bar);
1827 unsigned long flags = pci_resource_flags(dev, bar);
1831 if (max && len > max)
1833 if (flags & IORESOURCE_IO)
1834 return ioport_map(start, len);
1835 if (flags & IORESOURCE_MEM)
1836 /* Not checking IORESOURCE_CACHEABLE because PPC does
1837 * not currently distinguish between ioremap and
1840 return ioremap(start, len);
1845 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1849 EXPORT_SYMBOL(pci_iomap);
1850 EXPORT_SYMBOL(pci_iounmap);
1852 unsigned long pci_address_to_pio(phys_addr_t address)
1854 struct pci_controller* hose = hose_head;
1856 for (; hose; hose = hose->next) {
1857 unsigned int size = hose->io_resource.end -
1858 hose->io_resource.start + 1;
1859 if (address >= hose->io_base_phys &&
1860 address < (hose->io_base_phys + size)) {
1861 unsigned long base =
1862 (unsigned long)hose->io_base_virt - _IO_BASE;
1863 return base + (address - hose->io_base_phys);
1866 return (unsigned int)-1;
1868 EXPORT_SYMBOL(pci_address_to_pio);
1871 * Null PCI config access functions, for the case when we can't
1874 #define NULL_PCI_OP(rw, size, type) \
1876 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1878 return PCIBIOS_DEVICE_NOT_FOUND; \
1882 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1885 return PCIBIOS_DEVICE_NOT_FOUND;
1889 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1892 return PCIBIOS_DEVICE_NOT_FOUND;
1895 static struct pci_ops null_pci_ops =
1902 * These functions are used early on before PCI scanning is done
1903 * and all of the pci_dev and pci_bus structures have been created.
1905 static struct pci_bus *
1906 fake_pci_bus(struct pci_controller *hose, int busnr)
1908 static struct pci_bus bus;
1911 hose = pci_bus_to_hose(busnr);
1913 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1917 bus.ops = hose? hose->ops: &null_pci_ops;
1921 #define EARLY_PCI_OP(rw, size, type) \
1922 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1923 int devfn, int offset, type value) \
1925 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1926 devfn, offset, value); \
1929 EARLY_PCI_OP(read, byte, u8 *)
1930 EARLY_PCI_OP(read, word, u16 *)
1931 EARLY_PCI_OP(read, dword, u32 *)
1932 EARLY_PCI_OP(write, byte, u8)
1933 EARLY_PCI_OP(write, word, u16)
1934 EARLY_PCI_OP(write, dword, u32)