4 * Copyright 1993, Drew Eckhardt
6 * (Unix consulting and custom programming)
10 * DISTRIBUTION RELEASE 7
12 * For more information, please consult
15 * SCSI Protocol Controller
17 * NCR Microelectronics
18 * 1635 Aeroplaza Drive
19 * Colorado Springs, CO 80916
31 #include <linux/interrupt.h>
33 #define NCR5380_PUBLIC_RELEASE 7
34 #define NCR53C400_PUBLIC_RELEASE 2
36 #define NDEBUG_ARBITRATION 0x1
37 #define NDEBUG_AUTOSENSE 0x2
38 #define NDEBUG_DMA 0x4
39 #define NDEBUG_HANDSHAKE 0x8
40 #define NDEBUG_INFORMATION 0x10
41 #define NDEBUG_INIT 0x20
42 #define NDEBUG_INTR 0x40
43 #define NDEBUG_LINKED 0x80
44 #define NDEBUG_MAIN 0x100
45 #define NDEBUG_NO_DATAOUT 0x200
46 #define NDEBUG_NO_WRITE 0x400
47 #define NDEBUG_PIO 0x800
48 #define NDEBUG_PSEUDO_DMA 0x1000
49 #define NDEBUG_QUEUES 0x2000
50 #define NDEBUG_RESELECTION 0x4000
51 #define NDEBUG_SELECTION 0x8000
52 #define NDEBUG_USLEEP 0x10000
53 #define NDEBUG_LAST_BYTE_SENT 0x20000
54 #define NDEBUG_RESTART_SELECT 0x40000
55 #define NDEBUG_EXTENDED 0x80000
56 #define NDEBUG_C400_PREAD 0x100000
57 #define NDEBUG_C400_PWRITE 0x200000
58 #define NDEBUG_LISTS 0x400000
60 #define NDEBUG_ANY 0xFFFFFFFFUL
63 * The contents of the OUTPUT DATA register are asserted on the bus when
64 * either arbitration is occurring or the phase-indicating signals (
65 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
66 * bit in the INITIATOR COMMAND register is set.
69 #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
70 #define CURRENT_SCSI_DATA_REG 0 /* ro same */
72 #define INITIATOR_COMMAND_REG 1 /* rw */
73 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
74 #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
75 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
76 #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
77 #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
78 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
79 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
80 #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
81 #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
82 #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
85 #define ICR_BASE ICR_DIFF_ENABLE
92 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
93 * transfer, causing the chip to hog the bus. You probably don't want
96 #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
97 #define MR_TARGET 0x40 /* rw target mode */
98 #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
99 #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
100 #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
101 #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
102 #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
103 #define MR_ARBITRATE 0x01 /* rw start arbitration */
106 #define MR_BASE MR_ENABLE_PAR_CHECK
111 #define TARGET_COMMAND_REG 3
112 #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
113 #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
114 #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
115 #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
116 #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
118 #define STATUS_REG 4 /* ro */
120 * Note : a set bit indicates an active signal, driven by us or another
133 * Setting a bit in this register will cause an interrupt to be generated when
134 * BSY is false and SEL true and this bit is asserted on the bus.
136 #define SELECT_ENABLE_REG 4 /* wo */
138 #define BUS_AND_STATUS_REG 5 /* ro */
139 #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
140 #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
141 #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
142 #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
143 #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
144 #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
145 #define BASR_ATN 0x02 /* ro BUS status */
146 #define BASR_ACK 0x01 /* ro BUS status */
148 /* Write any value to this register to start a DMA send */
149 #define START_DMA_SEND_REG 5 /* wo */
152 * Used in DMA transfer mode, data is latched from the SCSI bus on
153 * the falling edge of REQ (ini) or ACK (tgt)
155 #define INPUT_DATA_REG 6 /* ro */
157 /* Write any value to this register to start a DMA receive */
158 #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
160 /* Read this register to clear interrupt conditions */
161 #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
163 /* Write any value to this register to start an ini mode DMA receive */
164 #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
166 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
168 #define CSR_RESET 0x80 /* wo Resets 53c400 */
169 #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
170 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
171 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
172 #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
173 #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
174 #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
175 #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
176 #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
179 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
181 #define CSR_BASE CSR_53C80_INTR
184 /* Number of 128-byte blocks to be transferred */
185 #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
187 /* Resume transfer after disconnect */
188 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
190 /* Access to host buffer stack */
191 #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
194 /* Note : PHASE_* macros are based on the values of the STATUS register */
195 #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
197 #define PHASE_DATAOUT 0
198 #define PHASE_DATAIN SR_IO
199 #define PHASE_CMDOUT SR_CD
200 #define PHASE_STATIN (SR_CD | SR_IO)
201 #define PHASE_MSGOUT (SR_MSG | SR_CD)
202 #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
203 #define PHASE_UNKNOWN 0xff
206 * Convert status register phase to something we can use to set phase in
207 * the target register so we can get phase mismatch interrupts on DMA
211 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
214 * The internal should_disconnect() function returns these based on the
215 * expected length of a disconnect if a device supports disconnect/
219 #define DISCONNECT_NONE 0
220 #define DISCONNECT_TIME_TO_DATA 1
221 #define DISCONNECT_LONG 2
224 * These are "special" values for the tag parameter passed to NCR5380_select.
227 #define TAG_NEXT -1 /* Use next free tag */
228 #define TAG_NONE -2 /*
229 * Establish I_T_L nexus instead of I_T_L_Q
230 * even on SCSI-II devices.
234 * These are "special" values for the irq and dma_channel fields of the
235 * Scsi_Host structure
238 #define SCSI_IRQ_NONE 255
242 #define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
244 #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
245 #define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
246 #define FLAG_NCR53C400 4 /* NCR53c400 */
247 #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
248 #define FLAG_DTC3181E 16 /* DTC3181E */
251 struct NCR5380_hostdata {
252 NCR5380_implementation_fields; /* implementation specific */
253 struct Scsi_Host *host; /* Host backpointer */
254 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
255 unsigned char targets_present; /* targets we have connected
256 to, so we can call a select
257 failure a retryable condition */
258 volatile unsigned char busy[8]; /* index = target, bit = lun */
259 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
260 volatile int dma_len; /* requested length of DMA */
262 volatile unsigned char last_message; /* last message OUT */
263 volatile Scsi_Cmnd *connected; /* currently connected command */
264 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
265 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
266 volatile int restart_select; /* we have disconnected,
269 volatile unsigned aborted:1; /* flag, says aborted */
271 unsigned long time_expires; /* in jiffies, set prior to sleeping */
272 int select_time; /* timer in select for target response */
273 volatile Scsi_Cmnd *selecting;
274 struct delayed_work coroutine; /* our co-routine */
276 unsigned timebase; /* Base for time calcs */
277 long time_read[8]; /* time to do reads */
278 long time_write[8]; /* time to do writes */
279 unsigned long bytes_read[8]; /* bytes read */
280 unsigned long bytes_write[8]; /* bytes written */
288 #define dprintk(a,b) do {} while(0)
289 #define NCR5380_dprint(a,b) do {} while(0)
290 #define NCR5380_dprint_phase(a,b) do {} while(0)
292 #if defined(AUTOPROBE_IRQ)
293 static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
295 static int NCR5380_init(struct Scsi_Host *instance, int flags);
296 static void NCR5380_exit(struct Scsi_Host *instance);
297 static void NCR5380_information_transfer(struct Scsi_Host *instance);
298 #ifndef DONT_USE_INTR
299 static irqreturn_t NCR5380_intr(int irq, void *dev_id);
301 static void NCR5380_main(struct work_struct *work);
302 static void __maybe_unused NCR5380_print_options(struct Scsi_Host *instance);
304 static void NCR5380_print_phase(struct Scsi_Host *instance);
305 static void NCR5380_print(struct Scsi_Host *instance);
307 static int NCR5380_abort(Scsi_Cmnd * cmd);
308 static int NCR5380_bus_reset(Scsi_Cmnd * cmd);
309 static int NCR5380_queue_command(Scsi_Cmnd * cmd, void (*done) (Scsi_Cmnd *));
310 static int __maybe_unused NCR5380_proc_info(struct Scsi_Host *instance,
311 char *buffer, char **start, off_t offset, int length, int inout);
313 static void NCR5380_reselect(struct Scsi_Host *instance);
314 static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
315 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
316 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
318 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
320 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
322 #if defined(i386) || defined(__alpha__)
325 * NCR5380_pc_dma_setup - setup ISA DMA
326 * @instance: adapter to set up
327 * @ptr: block to transfer (virtual address)
328 * @count: number of bytes to transfer
329 * @mode: DMA controller mode to use
331 * Program the DMA controller ready to perform an ISA DMA transfer
334 * Locks: takes and releases the ISA DMA lock.
337 static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
340 unsigned long bus_addr = virt_to_bus(ptr);
343 if (instance->dma_channel <= 3) {
346 limit = 65536 - (bus_addr & 0xFFFF);
348 if (count > 65536 * 2)
350 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
356 if ((count & 1) || (bus_addr & 1))
357 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
359 flags=claim_dma_lock();
360 disable_dma(instance->dma_channel);
361 clear_dma_ff(instance->dma_channel);
362 set_dma_addr(instance->dma_channel, bus_addr);
363 set_dma_count(instance->dma_channel, count);
364 set_dma_mode(instance->dma_channel, mode);
365 enable_dma(instance->dma_channel);
366 release_dma_lock(flags);
372 * NCR5380_pc_dma_write_setup - setup ISA DMA write
373 * @instance: adapter to set up
374 * @ptr: block to transfer (virtual address)
375 * @count: number of bytes to transfer
377 * Program the DMA controller ready to perform an ISA DMA write to the
380 * Locks: called routines take and release the ISA DMA lock.
383 static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
385 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
389 * NCR5380_pc_dma_read_setup - setup ISA DMA read
390 * @instance: adapter to set up
391 * @ptr: block to transfer (virtual address)
392 * @count: number of bytes to transfer
394 * Program the DMA controller ready to perform an ISA DMA read from the
397 * Locks: called routines take and release the ISA DMA lock.
400 static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
402 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
406 * NCR5380_pc_dma_residual - return bytes left
409 * Reports the number of bytes left over after the DMA was terminated.
411 * Locks: takes and releases the ISA DMA lock.
414 static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
419 flags = claim_dma_lock();
420 clear_dma_ff(instance->dma_channel);
421 tmp = get_dma_residue(instance->dma_channel);
422 release_dma_lock(flags);
426 #endif /* defined(i386) || defined(__alpha__) */
427 #endif /* defined(REAL_DMA) */
428 #endif /* __KERNEL__ */
429 #endif /* ndef ASM */
430 #endif /* NCR5380_H */