Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
[linux-2.6] / drivers / i2c / busses / i2c-mv64xxx.c
1 /*
2  * Driver for the i2c controller on the Marvell line of host bridges
3  * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4  *
5  * Author: Mark A. Greer <mgreer@mvista.com>
6  *
7  * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
8  * the terms of the GNU General Public License version 2.  This program
9  * is licensed "as is" without any warranty of any kind, whether express
10  * or implied.
11  */
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/mv643xx_i2c.h>
18 #include <linux/platform_device.h>
19
20 #include <asm/io.h>
21
22 /* Register defines */
23 #define MV64XXX_I2C_REG_SLAVE_ADDR                      0x00
24 #define MV64XXX_I2C_REG_DATA                            0x04
25 #define MV64XXX_I2C_REG_CONTROL                         0x08
26 #define MV64XXX_I2C_REG_STATUS                          0x0c
27 #define MV64XXX_I2C_REG_BAUD                            0x0c
28 #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR                  0x10
29 #define MV64XXX_I2C_REG_SOFT_RESET                      0x1c
30
31 #define MV64XXX_I2C_REG_CONTROL_ACK                     0x00000004
32 #define MV64XXX_I2C_REG_CONTROL_IFLG                    0x00000008
33 #define MV64XXX_I2C_REG_CONTROL_STOP                    0x00000010
34 #define MV64XXX_I2C_REG_CONTROL_START                   0x00000020
35 #define MV64XXX_I2C_REG_CONTROL_TWSIEN                  0x00000040
36 #define MV64XXX_I2C_REG_CONTROL_INTEN                   0x00000080
37
38 /* Ctlr status values */
39 #define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
40 #define MV64XXX_I2C_STATUS_MAST_START                   0x08
41 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START            0x10
42 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
43 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
44 #define MV64XXX_I2C_STATUS_MAST_WR_ACK                  0x28
45 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK               0x30
46 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB                0x38
47 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
48 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
49 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK             0x50
50 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
51 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
52 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
53 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
54 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
55 #define MV64XXX_I2C_STATUS_NO_STATUS                    0xf8
56
57 /* Driver states */
58 enum {
59         MV64XXX_I2C_STATE_INVALID,
60         MV64XXX_I2C_STATE_IDLE,
61         MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
62         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
63         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
64         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
65         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
66 };
67
68 /* Driver actions */
69 enum {
70         MV64XXX_I2C_ACTION_INVALID,
71         MV64XXX_I2C_ACTION_CONTINUE,
72         MV64XXX_I2C_ACTION_SEND_START,
73         MV64XXX_I2C_ACTION_SEND_ADDR_1,
74         MV64XXX_I2C_ACTION_SEND_ADDR_2,
75         MV64XXX_I2C_ACTION_SEND_DATA,
76         MV64XXX_I2C_ACTION_RCV_DATA,
77         MV64XXX_I2C_ACTION_RCV_DATA_STOP,
78         MV64XXX_I2C_ACTION_SEND_STOP,
79 };
80
81 struct mv64xxx_i2c_data {
82         int                     irq;
83         u32                     state;
84         u32                     action;
85         u32                     aborting;
86         u32                     cntl_bits;
87         void __iomem            *reg_base;
88         u32                     reg_base_p;
89         u32                     reg_size;
90         u32                     addr1;
91         u32                     addr2;
92         u32                     bytes_left;
93         u32                     byte_posn;
94         u32                     block;
95         int                     rc;
96         u32                     freq_m;
97         u32                     freq_n;
98         wait_queue_head_t       waitq;
99         spinlock_t              lock;
100         struct i2c_msg          *msg;
101         struct i2c_adapter      adapter;
102 };
103
104 /*
105  *****************************************************************************
106  *
107  *      Finite State Machine & Interrupt Routines
108  *
109  *****************************************************************************
110  */
111
112 /* Reset hardware and initialize FSM */
113 static void
114 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
115 {
116         writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
117         writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
118                 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
119         writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
120         writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
121         writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
122                 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
123         drv_data->state = MV64XXX_I2C_STATE_IDLE;
124 }
125
126 static void
127 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
128 {
129         /*
130          * If state is idle, then this is likely the remnants of an old
131          * operation that driver has given up on or the user has killed.
132          * If so, issue the stop condition and go to idle.
133          */
134         if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
135                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
136                 return;
137         }
138
139         /* The status from the ctlr [mostly] tells us what to do next */
140         switch (status) {
141         /* Start condition interrupt */
142         case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
143         case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
144                 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
145                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
146                 break;
147
148         /* Performing a write */
149         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
150                 if (drv_data->msg->flags & I2C_M_TEN) {
151                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
152                         drv_data->state =
153                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
154                         break;
155                 }
156                 /* FALLTHRU */
157         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
158         case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
159                 if ((drv_data->bytes_left == 0)
160                                 || (drv_data->aborting
161                                         && (drv_data->byte_posn != 0))) {
162                         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
163                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
164                 } else {
165                         drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
166                         drv_data->state =
167                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
168                         drv_data->bytes_left--;
169                 }
170                 break;
171
172         /* Performing a read */
173         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
174                 if (drv_data->msg->flags & I2C_M_TEN) {
175                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
176                         drv_data->state =
177                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
178                         break;
179                 }
180                 /* FALLTHRU */
181         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
182                 if (drv_data->bytes_left == 0) {
183                         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
184                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
185                         break;
186                 }
187                 /* FALLTHRU */
188         case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
189                 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
190                         drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
191                 else {
192                         drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
193                         drv_data->bytes_left--;
194                 }
195                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
196
197                 if ((drv_data->bytes_left == 1) || drv_data->aborting)
198                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
199                 break;
200
201         case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
202                 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
203                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
204                 break;
205
206         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
207         case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
208         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
209                 /* Doesn't seem to be a device at other end */
210                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
211                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
212                 drv_data->rc = -ENODEV;
213                 break;
214
215         default:
216                 dev_err(&drv_data->adapter.dev,
217                         "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
218                         "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
219                          drv_data->state, status, drv_data->msg->addr,
220                          drv_data->msg->flags);
221                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
222                 mv64xxx_i2c_hw_init(drv_data);
223                 drv_data->rc = -EIO;
224         }
225 }
226
227 static void
228 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
229 {
230         switch(drv_data->action) {
231         case MV64XXX_I2C_ACTION_CONTINUE:
232                 writel(drv_data->cntl_bits,
233                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
234                 break;
235
236         case MV64XXX_I2C_ACTION_SEND_START:
237                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
238                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
239                 break;
240
241         case MV64XXX_I2C_ACTION_SEND_ADDR_1:
242                 writel(drv_data->addr1,
243                         drv_data->reg_base + MV64XXX_I2C_REG_DATA);
244                 writel(drv_data->cntl_bits,
245                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
246                 break;
247
248         case MV64XXX_I2C_ACTION_SEND_ADDR_2:
249                 writel(drv_data->addr2,
250                         drv_data->reg_base + MV64XXX_I2C_REG_DATA);
251                 writel(drv_data->cntl_bits,
252                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
253                 break;
254
255         case MV64XXX_I2C_ACTION_SEND_DATA:
256                 writel(drv_data->msg->buf[drv_data->byte_posn++],
257                         drv_data->reg_base + MV64XXX_I2C_REG_DATA);
258                 writel(drv_data->cntl_bits,
259                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
260                 break;
261
262         case MV64XXX_I2C_ACTION_RCV_DATA:
263                 drv_data->msg->buf[drv_data->byte_posn++] =
264                         readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
265                 writel(drv_data->cntl_bits,
266                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
267                 break;
268
269         case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
270                 drv_data->msg->buf[drv_data->byte_posn++] =
271                         readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
272                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
273                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
274                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
275                 drv_data->block = 0;
276                 wake_up_interruptible(&drv_data->waitq);
277                 break;
278
279         case MV64XXX_I2C_ACTION_INVALID:
280         default:
281                 dev_err(&drv_data->adapter.dev,
282                         "mv64xxx_i2c_do_action: Invalid action: %d\n",
283                         drv_data->action);
284                 drv_data->rc = -EIO;
285                 /* FALLTHRU */
286         case MV64XXX_I2C_ACTION_SEND_STOP:
287                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
288                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
289                         drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
290                 drv_data->block = 0;
291                 wake_up_interruptible(&drv_data->waitq);
292                 break;
293         }
294 }
295
296 static int
297 mv64xxx_i2c_intr(int irq, void *dev_id)
298 {
299         struct mv64xxx_i2c_data *drv_data = dev_id;
300         unsigned long   flags;
301         u32             status;
302         int             rc = IRQ_NONE;
303
304         spin_lock_irqsave(&drv_data->lock, flags);
305         while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
306                                                 MV64XXX_I2C_REG_CONTROL_IFLG) {
307                 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
308                 mv64xxx_i2c_fsm(drv_data, status);
309                 mv64xxx_i2c_do_action(drv_data);
310                 rc = IRQ_HANDLED;
311         }
312         spin_unlock_irqrestore(&drv_data->lock, flags);
313
314         return rc;
315 }
316
317 /*
318  *****************************************************************************
319  *
320  *      I2C Msg Execution Routines
321  *
322  *****************************************************************************
323  */
324 static void
325 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
326         struct i2c_msg *msg)
327 {
328         u32     dir = 0;
329
330         drv_data->msg = msg;
331         drv_data->byte_posn = 0;
332         drv_data->bytes_left = msg->len;
333         drv_data->aborting = 0;
334         drv_data->rc = 0;
335         drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
336                 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
337
338         if (msg->flags & I2C_M_RD)
339                 dir = 1;
340
341         if (msg->flags & I2C_M_REV_DIR_ADDR)
342                 dir ^= 1;
343
344         if (msg->flags & I2C_M_TEN) {
345                 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
346                 drv_data->addr2 = (u32)msg->addr & 0xff;
347         } else {
348                 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
349                 drv_data->addr2 = 0;
350         }
351 }
352
353 static void
354 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
355 {
356         long            time_left;
357         unsigned long   flags;
358         char            abort = 0;
359
360         time_left = wait_event_interruptible_timeout(drv_data->waitq,
361                 !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
362
363         spin_lock_irqsave(&drv_data->lock, flags);
364         if (!time_left) { /* Timed out */
365                 drv_data->rc = -ETIMEDOUT;
366                 abort = 1;
367         } else if (time_left < 0) { /* Interrupted/Error */
368                 drv_data->rc = time_left; /* errno value */
369                 abort = 1;
370         }
371
372         if (abort && drv_data->block) {
373                 drv_data->aborting = 1;
374                 spin_unlock_irqrestore(&drv_data->lock, flags);
375
376                 time_left = wait_event_timeout(drv_data->waitq,
377                         !drv_data->block,
378                         msecs_to_jiffies(drv_data->adapter.timeout));
379
380                 if ((time_left <= 0) && drv_data->block) {
381                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
382                         dev_err(&drv_data->adapter.dev,
383                                 "mv64xxx: I2C bus locked, block: %d, "
384                                 "time_left: %d\n", drv_data->block,
385                                 (int)time_left);
386                         mv64xxx_i2c_hw_init(drv_data);
387                 }
388         } else
389                 spin_unlock_irqrestore(&drv_data->lock, flags);
390 }
391
392 static int
393 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
394 {
395         unsigned long   flags;
396
397         spin_lock_irqsave(&drv_data->lock, flags);
398         mv64xxx_i2c_prepare_for_io(drv_data, msg);
399
400         if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
401                 if (drv_data->msg->flags & I2C_M_RD) {
402                         /* No action to do, wait for slave to send a byte */
403                         drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
404                         drv_data->state =
405                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
406                 } else {
407                         drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
408                         drv_data->state =
409                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
410                         drv_data->bytes_left--;
411                 }
412         } else {
413                 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
414                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
415         }
416
417         drv_data->block = 1;
418         mv64xxx_i2c_do_action(drv_data);
419         spin_unlock_irqrestore(&drv_data->lock, flags);
420
421         mv64xxx_i2c_wait_for_completion(drv_data);
422         return drv_data->rc;
423 }
424
425 /*
426  *****************************************************************************
427  *
428  *      I2C Core Support Routines (Interface to higher level I2C code)
429  *
430  *****************************************************************************
431  */
432 static u32
433 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
434 {
435         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
436 }
437
438 static int
439 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
440 {
441         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
442         int     i, rc;
443
444         for (i=0; i<num; i++)
445                 if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0)
446                         return rc;
447
448         return num;
449 }
450
451 static const struct i2c_algorithm mv64xxx_i2c_algo = {
452         .master_xfer = mv64xxx_i2c_xfer,
453         .functionality = mv64xxx_i2c_functionality,
454 };
455
456 /*
457  *****************************************************************************
458  *
459  *      Driver Interface & Early Init Routines
460  *
461  *****************************************************************************
462  */
463 static int __devinit
464 mv64xxx_i2c_map_regs(struct platform_device *pd,
465         struct mv64xxx_i2c_data *drv_data)
466 {
467         int size;
468         struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0);
469
470         if (!r)
471                 return -ENODEV;
472
473         size = r->end - r->start + 1;
474
475         if (!request_mem_region(r->start, size, drv_data->adapter.name))
476                 return -EBUSY;
477
478         drv_data->reg_base = ioremap(r->start, size);
479         drv_data->reg_base_p = r->start;
480         drv_data->reg_size = size;
481
482         return 0;
483 }
484
485 static void
486 mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
487 {
488         if (drv_data->reg_base) {
489                 iounmap(drv_data->reg_base);
490                 release_mem_region(drv_data->reg_base_p, drv_data->reg_size);
491         }
492
493         drv_data->reg_base = NULL;
494         drv_data->reg_base_p = 0;
495 }
496
497 static int __devinit
498 mv64xxx_i2c_probe(struct platform_device *pd)
499 {
500         struct mv64xxx_i2c_data         *drv_data;
501         struct mv64xxx_i2c_pdata        *pdata = pd->dev.platform_data;
502         int     rc;
503
504         if ((pd->id != 0) || !pdata)
505                 return -ENODEV;
506
507         drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
508         if (!drv_data)
509                 return -ENOMEM;
510
511         if (mv64xxx_i2c_map_regs(pd, drv_data)) {
512                 rc = -ENODEV;
513                 goto exit_kfree;
514         }
515
516         strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
517                 sizeof(drv_data->adapter.name));
518
519         init_waitqueue_head(&drv_data->waitq);
520         spin_lock_init(&drv_data->lock);
521
522         drv_data->freq_m = pdata->freq_m;
523         drv_data->freq_n = pdata->freq_n;
524         drv_data->irq = platform_get_irq(pd, 0);
525         if (drv_data->irq < 0) {
526                 rc = -ENXIO;
527                 goto exit_unmap_regs;
528         }
529         drv_data->adapter.dev.parent = &pd->dev;
530         drv_data->adapter.algo = &mv64xxx_i2c_algo;
531         drv_data->adapter.owner = THIS_MODULE;
532         drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
533         drv_data->adapter.timeout = pdata->timeout;
534         drv_data->adapter.nr = pd->id;
535         platform_set_drvdata(pd, drv_data);
536         i2c_set_adapdata(&drv_data->adapter, drv_data);
537
538         mv64xxx_i2c_hw_init(drv_data);
539
540         if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
541                         MV64XXX_I2C_CTLR_NAME, drv_data)) {
542                 dev_err(&drv_data->adapter.dev,
543                         "mv64xxx: Can't register intr handler irq: %d\n",
544                         drv_data->irq);
545                 rc = -EINVAL;
546                 goto exit_unmap_regs;
547         } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
548                 dev_err(&drv_data->adapter.dev,
549                         "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
550                 goto exit_free_irq;
551         }
552
553         return 0;
554
555         exit_free_irq:
556                 free_irq(drv_data->irq, drv_data);
557         exit_unmap_regs:
558                 mv64xxx_i2c_unmap_regs(drv_data);
559         exit_kfree:
560                 kfree(drv_data);
561         return rc;
562 }
563
564 static int __devexit
565 mv64xxx_i2c_remove(struct platform_device *dev)
566 {
567         struct mv64xxx_i2c_data         *drv_data = platform_get_drvdata(dev);
568         int     rc;
569
570         rc = i2c_del_adapter(&drv_data->adapter);
571         free_irq(drv_data->irq, drv_data);
572         mv64xxx_i2c_unmap_regs(drv_data);
573         kfree(drv_data);
574
575         return rc;
576 }
577
578 static struct platform_driver mv64xxx_i2c_driver = {
579         .probe  = mv64xxx_i2c_probe,
580         .remove = __devexit_p(mv64xxx_i2c_remove),
581         .driver = {
582                 .owner  = THIS_MODULE,
583                 .name   = MV64XXX_I2C_CTLR_NAME,
584         },
585 };
586
587 static int __init
588 mv64xxx_i2c_init(void)
589 {
590         return platform_driver_register(&mv64xxx_i2c_driver);
591 }
592
593 static void __exit
594 mv64xxx_i2c_exit(void)
595 {
596         platform_driver_unregister(&mv64xxx_i2c_driver);
597 }
598
599 module_init(mv64xxx_i2c_init);
600 module_exit(mv64xxx_i2c_exit);
601
602 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
603 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
604 MODULE_LICENSE("GPL");