git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/phy.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "core.h"
  18 #include "hw.h"
  19 #include "reg.h"
  20 #include "phy.h"
  21
  22 void
  23 ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
  24                     int regWrites)
  25 {
  26         struct ath_hal_5416 *ahp = AH5416(ah);
  27
  28         REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
  29 }
  30
  31 bool
  32 ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
  33 {
  34         u32 channelSel = 0;
  35         u32 bModeSynth = 0;
  36         u32 aModeRefSel = 0;
  37         u32 reg32 = 0;
  38         u16 freq;
  39         struct chan_centers centers;
  40
  41         ath9k_hw_get_channel_centers(ah, chan, &centers);
  42         freq = centers.synth_center;
  43
  44         if (freq < 4800) {
  45                 u32 txctl;
  46
  47                 if (((freq - 2192) % 5) == 0) {
  48                         channelSel = ((freq - 672) * 2 - 3040) / 10;
  49                         bModeSynth = 0;
  50                 } else if (((freq - 2224) % 5) == 0) {
  51                         channelSel = ((freq - 704) * 2 - 3040) / 10;
  52                         bModeSynth = 1;
  53                 } else {
  54                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
  55                                 "Invalid channel %u MHz\n", freq);
  56                         return false;
  57                 }
  58
  59                 channelSel = (channelSel << 2) & 0xff;
  60                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  61
  62                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  63                 if (freq == 2484) {
  64
  65                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  66                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  67                 } else {
  68                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  69                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  70                 }
  71
  72         } else if ((freq % 20) == 0 && freq >= 5120) {
  73                 channelSel =
  74                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  75                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  76         } else if ((freq % 10) == 0) {
  77                 channelSel =
  78                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  79                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  80                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  81                 else
  82                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  83         } else if ((freq % 5) == 0) {
  84                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  85                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  86         } else {
  87                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
  88                         "Invalid channel %u MHz\n", freq);
  89                 return false;
  90         }
  91
  92         reg32 =
  93             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  94             (1 << 5) | 0x1;
  95
  96         REG_WRITE(ah, AR_PHY(0x37), reg32);
  97
  98         ah->ah_curchan = chan;
  99
 100         AH5416(ah)->ah_curchanRadIndex = -1;
 101
 102         return true;
 103 }
 104
 105 bool
 106 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 107                             struct ath9k_channel *chan)
 108 {
 109         u16 bMode, fracMode, aModeRefSel = 0;
 110         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 111         struct chan_centers centers;
 112         u32 refDivA = 24;
 113
 114         ath9k_hw_get_channel_centers(ah, chan, &centers);
 115         freq = centers.synth_center;
 116
 117         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 118         reg32 &= 0xc0000000;
 119
 120         if (freq < 4800) {
 121                 u32 txctl;
 122
 123                 bMode = 1;
 124                 fracMode = 1;
 125                 aModeRefSel = 0;
 126                 channelSel = (freq * 0x10000) / 15;
 127
 128                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 129                 if (freq == 2484) {
 130
 131                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 132                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 133                 } else {
 134                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 135                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 136                 }
 137         } else {
 138                 bMode = 0;
 139                 fracMode = 0;
 140
 141                 if ((freq % 20) == 0) {
 142                         aModeRefSel = 3;
 143                 } else if ((freq % 10) == 0) {
 144                         aModeRefSel = 2;
 145                 } else {
 146                         aModeRefSel = 0;
 147
 148                         fracMode = 1;
 149                         refDivA = 1;
 150                         channelSel = (freq * 0x8000) / 15;
 151
 152                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 153                                       AR_AN_SYNTH9_REFDIVA, refDivA);
 154                 }
 155                 if (!fracMode) {
 156                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
 157                         channelSel = ndiv & 0x1ff;
 158                         channelFrac = (ndiv & 0xfffffe00) * 2;
 159                         channelSel = (channelSel << 17) | channelFrac;
 160                 }
 161         }
 162
 163         reg32 = reg32 |
 164             (bMode << 29) |
 165             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
 166
 167         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 168
 169         ah->ah_curchan = chan;
 170
 171         AH5416(ah)->ah_curchanRadIndex = -1;
 172
 173         return true;
 174 }
 175
 176 static void
 177 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
 178                            u32 numBits, u32 firstBit,
 179                            u32 column)
 180 {
 181         u32 tmp32, mask, arrayEntry, lastBit;
 182         int32_t bitPosition, bitsLeft;
 183
 184         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
 185         arrayEntry = (firstBit - 1) / 8;
 186         bitPosition = (firstBit - 1) % 8;
 187         bitsLeft = numBits;
 188         while (bitsLeft > 0) {
 189                 lastBit = (bitPosition + bitsLeft > 8) ?
 190                     8 : bitPosition + bitsLeft;
 191                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
 192                     (column * 8);
 193                 rfBuf[arrayEntry] &= ~mask;
 194                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
 195                                       (column * 8)) & mask;
 196                 bitsLeft -= 8 - bitPosition;
 197                 tmp32 = tmp32 >> (8 - bitPosition);
 198                 bitPosition = 0;
 199                 arrayEntry++;
 200         }
 201 }
 202
 203 bool
 204 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
 205                      u16 modesIndex)
 206 {
 207         struct ath_hal_5416 *ahp = AH5416(ah);
 208
 209         u32 eepMinorRev;
 210         u32 ob5GHz = 0, db5GHz = 0;
 211         u32 ob2GHz = 0, db2GHz = 0;
 212         int regWrites = 0;
 213
 214         if (AR_SREV_9280_10_OR_LATER(ah))
 215                 return true;
 216
 217         eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
 218
 219         RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1);
 220
 221         RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1);
 222
 223         RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1);
 224
 225         RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3,
 226                       modesIndex);
 227         {
 228                 int i;
 229                 for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) {
 230                         ahp->ah_analogBank6Data[i] =
 231                             INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex);
 232                 }
 233         }
 234
 235         if (eepMinorRev >= 2) {
 236                 if (IS_CHAN_2GHZ(chan)) {
 237                         ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
 238                         db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
 239                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 240                                                    ob2GHz, 3, 197, 0);
 241                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 242                                                    db2GHz, 3, 194, 0);
 243                 } else {
 244                         ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
 245                         db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
 246                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 247                                                    ob5GHz, 3, 203, 0);
 248                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 249                                                    db5GHz, 3, 200, 0);
 250                 }
 251         }
 252
 253         RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1);
 254
 255         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data,
 256                            regWrites);
 257         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data,
 258                            regWrites);
 259         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data,
 260                            regWrites);
 261         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data,
 262                            regWrites);
 263         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data,
 264                            regWrites);
 265         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
 266                            regWrites);
 267
 268         return true;
 269 }
 270
 271 void
 272 ath9k_hw_rfdetach(struct ath_hal *ah)
 273 {
 274         struct ath_hal_5416 *ahp = AH5416(ah);
 275
 276         if (ahp->ah_analogBank0Data != NULL) {
 277                 kfree(ahp->ah_analogBank0Data);
 278                 ahp->ah_analogBank0Data = NULL;
 279         }
 280         if (ahp->ah_analogBank1Data != NULL) {
 281                 kfree(ahp->ah_analogBank1Data);
 282                 ahp->ah_analogBank1Data = NULL;
 283         }
 284         if (ahp->ah_analogBank2Data != NULL) {
 285                 kfree(ahp->ah_analogBank2Data);
 286                 ahp->ah_analogBank2Data = NULL;
 287         }
 288         if (ahp->ah_analogBank3Data != NULL) {
 289                 kfree(ahp->ah_analogBank3Data);
 290                 ahp->ah_analogBank3Data = NULL;
 291         }
 292         if (ahp->ah_analogBank6Data != NULL) {
 293                 kfree(ahp->ah_analogBank6Data);
 294                 ahp->ah_analogBank6Data = NULL;
 295         }
 296         if (ahp->ah_analogBank6TPCData != NULL) {
 297                 kfree(ahp->ah_analogBank6TPCData);
 298                 ahp->ah_analogBank6TPCData = NULL;
 299         }
 300         if (ahp->ah_analogBank7Data != NULL) {
 301                 kfree(ahp->ah_analogBank7Data);
 302                 ahp->ah_analogBank7Data = NULL;
 303         }
 304         if (ahp->ah_addac5416_21 != NULL) {
 305                 kfree(ahp->ah_addac5416_21);
 306                 ahp->ah_addac5416_21 = NULL;
 307         }
 308         if (ahp->ah_bank6Temp != NULL) {
 309                 kfree(ahp->ah_bank6Temp);
 310                 ahp->ah_bank6Temp = NULL;
 311         }
 312 }
 313
 314 bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
 315 {
 316         struct ath_hal_5416 *ahp = AH5416(ah);
 317
 318         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 319
 320                 ahp->ah_analogBank0Data =
 321                     kzalloc((sizeof(u32) *
 322                              ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
 323                 ahp->ah_analogBank1Data =
 324                     kzalloc((sizeof(u32) *
 325                              ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
 326                 ahp->ah_analogBank2Data =
 327                     kzalloc((sizeof(u32) *
 328                              ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
 329                 ahp->ah_analogBank3Data =
 330                     kzalloc((sizeof(u32) *
 331                              ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
 332                 ahp->ah_analogBank6Data =
 333                     kzalloc((sizeof(u32) *
 334                              ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 335                 ahp->ah_analogBank6TPCData =
 336                     kzalloc((sizeof(u32) *
 337                              ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
 338                 ahp->ah_analogBank7Data =
 339                     kzalloc((sizeof(u32) *
 340                              ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
 341
 342                 if (ahp->ah_analogBank0Data == NULL
 343                     || ahp->ah_analogBank1Data == NULL
 344                     || ahp->ah_analogBank2Data == NULL
 345                     || ahp->ah_analogBank3Data == NULL
 346                     || ahp->ah_analogBank6Data == NULL
 347                     || ahp->ah_analogBank6TPCData == NULL
 348                     || ahp->ah_analogBank7Data == NULL) {
 349                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 350                                 "Cannot allocate RF banks\n");
 351                         *status = -ENOMEM;
 352                         return false;
 353                 }
 354
 355                 ahp->ah_addac5416_21 =
 356                     kzalloc((sizeof(u32) *
 357                              ahp->ah_iniAddac.ia_rows *
 358                              ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
 359                 if (ahp->ah_addac5416_21 == NULL) {
 360                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 361                                 "Cannot allocate ah_addac5416_21\n");
 362                         *status = -ENOMEM;
 363                         return false;
 364                 }
 365
 366                 ahp->ah_bank6Temp =
 367                     kzalloc((sizeof(u32) *
 368                              ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 369                 if (ahp->ah_bank6Temp == NULL) {
 370                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 371                                 "Cannot allocate ah_bank6Temp\n");
 372                         *status = -ENOMEM;
 373                         return false;
 374                 }
 375         }
 376
 377         return true;
 378 }
 379
 380 void
 381 ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
 382 {
 383         int i, regWrites = 0;
 384         struct ath_hal_5416 *ahp = AH5416(ah);
 385         u32 bank6SelMask;
 386         u32 *bank6Temp = ahp->ah_bank6Temp;
 387
 388         switch (ahp->ah_diversityControl) {
 389         case ATH9K_ANT_FIXED_A:
 390                 bank6SelMask =
 391                     (ahp->
 392                      ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
 393                     REDUCE_CHAIN_1;
 394                 break;
 395         case ATH9K_ANT_FIXED_B:
 396                 bank6SelMask =
 397                     (ahp->
 398                      ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
 399                     REDUCE_CHAIN_0;
 400                 break;
 401         case ATH9K_ANT_VARIABLE:
 402                 return;
 403                 break;
 404         default:
 405                 return;
 406                 break;
 407         }
 408
 409         for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++)
 410                 bank6Temp[i] = ahp->ah_analogBank6Data[i];
 411
 412         REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
 413
 414         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
 415         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
 416         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
 417         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
 418         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
 419         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
 420         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
 421         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
 422         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
 423
 424         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites);
 425
 426         REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
 427 #ifdef ALTER_SWITCH
 428         REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
 429                   (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
 430                   | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
 431 #endif
 432 }