2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
32 #include <linux/config.h>
34 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
35 #define DMA_WAIT_TIMEOUT 100
36 #define NUM_DESCRIPTORS PRD_ENTRIES
37 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
38 #define NUM_DESCRIPTORS 2
41 #ifndef AU1XXX_ATA_RQSIZE
42 #define AU1XXX_ATA_RQSIZE 128
45 /* Disable Burstable-Support for DBDMA */
46 #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
47 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
52 * This will enable the device to be powered up when write() or read()
53 * is called. If this is not defined, the driver will return -EBUSY.
55 #define WAKE_ON_ACCESS 1
59 spinlock_t lock; /* Used to block on state transitions */
60 au1xxx_power_dev_t *dev; /* Power Managers device structure */
61 unsigned stopped; /* USed to signaling device is stopped */
68 u32 tx_dev_id, rx_dev_id, target_dev_id;
70 void *tx_desc_head, *rx_desc_head;
72 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
74 u8 white_list, black_list;
75 struct dbdma_cmd *dma_table_cpu;
76 dma_addr_t dma_table_dma;
77 struct scatterlist *sg_table;
89 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
90 struct drive_list_entry {
91 const char * id_model;
92 const char * id_firmware;
96 static const struct drive_list_entry dma_white_list [] = {
100 { "HITACHI_DK14FA-20" , "ALL" },
101 { "HTS726060M9AT00" , "ALL" },
105 { "Maxtor 6E040L0" , "ALL" },
106 { "Maxtor 6Y080P0" , "ALL" },
107 { "Maxtor 6Y160P0" , "ALL" },
111 { "ST3120026A" , "ALL" },
112 { "ST320014A" , "ALL" },
113 { "ST94011A" , "ALL" },
114 { "ST340016A" , "ALL" },
118 { "WDC WD400UE-00HCT0" , "ALL" },
119 { "WDC WD400JB-00JJC0" , "ALL" },
124 static const struct drive_list_entry dma_black_list [] = {
128 { "WDC WD100EB-00CGH0" , "ALL" },
129 { "WDC WD200BB-00AUA1" , "ALL" },
130 { "WDC AC24300L" , "ALL" },
135 /* function prototyping */
136 u8 auide_inb(unsigned long port);
137 u16 auide_inw(unsigned long port);
138 u32 auide_inl(unsigned long port);
139 void auide_insw(unsigned long port, void *addr, u32 count);
140 void auide_insl(unsigned long port, void *addr, u32 count);
141 void auide_outb(u8 addr, unsigned long port);
142 void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
143 void auide_outw(u16 addr, unsigned long port);
144 void auide_outl(u32 addr, unsigned long port);
145 void auide_outsw(unsigned long port, void *addr, u32 count);
146 void auide_outsl(unsigned long port, void *addr, u32 count);
147 static void auide_tune_drive(ide_drive_t *drive, byte pio);
148 static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
149 static int auide_ddma_init( _auide_hwif *auide );
150 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
151 int __init auide_probe(void);
154 int au1200ide_pm_callback( au1xxx_power_dev_t *dev,
155 au1xxx_request_t request, void *data);
156 static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev );
157 static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev );
158 static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev );
159 static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev );
160 static int au1xxxide_pm_access( au1xxx_power_dev_t *dev );
161 static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev );
162 static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev );
167 * Multi-Word DMA + DbDMA functions
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
171 static int in_drive_list(struct hd_driveid *id,
172 const struct drive_list_entry *drive_table);
173 static int auide_build_sglist(ide_drive_t *drive, struct request *rq);
174 static int auide_build_dmatable(ide_drive_t *drive);
175 static int auide_dma_end(ide_drive_t *drive);
176 static void auide_dma_start(ide_drive_t *drive );
177 ide_startstop_t auide_dma_intr (ide_drive_t *drive);
178 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
179 static int auide_dma_setup(ide_drive_t *drive);
180 static int auide_dma_check(ide_drive_t *drive);
181 static int auide_dma_test_irq(ide_drive_t *drive);
182 static int auide_dma_host_off(ide_drive_t *drive);
183 static int auide_dma_host_on(ide_drive_t *drive);
184 static int auide_dma_lostirq(ide_drive_t *drive);
185 static int auide_dma_on(ide_drive_t *drive);
186 static void auide_ddma_tx_callback(int irq, void *param,
187 struct pt_regs *regs);
188 static void auide_ddma_rx_callback(int irq, void *param,
189 struct pt_regs *regs);
190 static int auide_dma_off_quietly(ide_drive_t *drive);
191 static int auide_dma_timeout(ide_drive_t *drive);
193 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
195 /*******************************************************************************
196 * PIO Mode timing calculation : *
198 * Static Bus Spec ATA Spec *
203 * Tcsoff = t2i | t2 *
208 *******************************************************************************/
210 #define TCSOE_MASK (0x07<<29)
211 #define TOECS_MASK (0x07<<26)
212 #define TWCS_MASK (0x07<<28)
213 #define TCSH_MASK (0x0F<<24)
214 #define TCSOFF_MASK (0x07<<20)
215 #define TWP_MASK (0x3F<<14)
216 #define TCSW_MASK (0x0F<<10)
217 #define TPM_MASK (0x0F<<6)
218 #define TA_MASK (0x3F<<0)
219 #define TS_MASK (1<<8)
221 /* Timing parameters PIO mode 0 */
222 #define SBC_IDE_PIO0_TCSOE (0x04<<29)
223 #define SBC_IDE_PIO0_TOECS (0x01<<26)
224 #define SBC_IDE_PIO0_TWCS (0x02<<28)
225 #define SBC_IDE_PIO0_TCSH (0x08<<24)
226 #define SBC_IDE_PIO0_TCSOFF (0x07<<20)
227 #define SBC_IDE_PIO0_TWP (0x10<<14)
228 #define SBC_IDE_PIO0_TCSW (0x04<<10)
229 #define SBC_IDE_PIO0_TPM (0x0<<6)
230 #define SBC_IDE_PIO0_TA (0x15<<0)
231 /* Timing parameters PIO mode 1 */
232 #define SBC_IDE_PIO1_TCSOE (0x03<<29)
233 #define SBC_IDE_PIO1_TOECS (0x01<<26)
234 #define SBC_IDE_PIO1_TWCS (0x01<<28)
235 #define SBC_IDE_PIO1_TCSH (0x06<<24)
236 #define SBC_IDE_PIO1_TCSOFF (0x06<<20)
237 #define SBC_IDE_PIO1_TWP (0x08<<14)
238 #define SBC_IDE_PIO1_TCSW (0x03<<10)
239 #define SBC_IDE_PIO1_TPM (0x00<<6)
240 #define SBC_IDE_PIO1_TA (0x0B<<0)
241 /* Timing parameters PIO mode 2 */
242 #define SBC_IDE_PIO2_TCSOE (0x05<<29)
243 #define SBC_IDE_PIO2_TOECS (0x01<<26)
244 #define SBC_IDE_PIO2_TWCS (0x01<<28)
245 #define SBC_IDE_PIO2_TCSH (0x07<<24)
246 #define SBC_IDE_PIO2_TCSOFF (0x07<<20)
247 #define SBC_IDE_PIO2_TWP (0x1F<<14)
248 #define SBC_IDE_PIO2_TCSW (0x05<<10)
249 #define SBC_IDE_PIO2_TPM (0x00<<6)
250 #define SBC_IDE_PIO2_TA (0x22<<0)
251 /* Timing parameters PIO mode 3 */
252 #define SBC_IDE_PIO3_TCSOE (0x05<<29)
253 #define SBC_IDE_PIO3_TOECS (0x01<<26)
254 #define SBC_IDE_PIO3_TWCS (0x01<<28)
255 #define SBC_IDE_PIO3_TCSH (0x0D<<24)
256 #define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
257 #define SBC_IDE_PIO3_TWP (0x15<<14)
258 #define SBC_IDE_PIO3_TCSW (0x05<<10)
259 #define SBC_IDE_PIO3_TPM (0x00<<6)
260 #define SBC_IDE_PIO3_TA (0x1A<<0)
261 /* Timing parameters PIO mode 4 */
262 #define SBC_IDE_PIO4_TCSOE (0x04<<29)
263 #define SBC_IDE_PIO4_TOECS (0x01<<26)
264 #define SBC_IDE_PIO4_TWCS (0x01<<28)
265 #define SBC_IDE_PIO4_TCSH (0x04<<24)
266 #define SBC_IDE_PIO4_TCSOFF (0x04<<20)
267 #define SBC_IDE_PIO4_TWP (0x0D<<14)
268 #define SBC_IDE_PIO4_TCSW (0x03<<10)
269 #define SBC_IDE_PIO4_TPM (0x00<<6)
270 #define SBC_IDE_PIO4_TA (0x12<<0)
271 /* Timing parameters MDMA mode 0 */
272 #define SBC_IDE_MDMA0_TCSOE (0x03<<29)
273 #define SBC_IDE_MDMA0_TOECS (0x01<<26)
274 #define SBC_IDE_MDMA0_TWCS (0x01<<28)
275 #define SBC_IDE_MDMA0_TCSH (0x07<<24)
276 #define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
277 #define SBC_IDE_MDMA0_TWP (0x0C<<14)
278 #define SBC_IDE_MDMA0_TCSW (0x03<<10)
279 #define SBC_IDE_MDMA0_TPM (0x00<<6)
280 #define SBC_IDE_MDMA0_TA (0x0F<<0)
281 /* Timing parameters MDMA mode 1 */
282 #define SBC_IDE_MDMA1_TCSOE (0x05<<29)
283 #define SBC_IDE_MDMA1_TOECS (0x01<<26)
284 #define SBC_IDE_MDMA1_TWCS (0x01<<28)
285 #define SBC_IDE_MDMA1_TCSH (0x05<<24)
286 #define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
287 #define SBC_IDE_MDMA1_TWP (0x0F<<14)
288 #define SBC_IDE_MDMA1_TCSW (0x05<<10)
289 #define SBC_IDE_MDMA1_TPM (0x00<<6)
290 #define SBC_IDE_MDMA1_TA (0x15<<0)
291 /* Timing parameters MDMA mode 2 */
292 #define SBC_IDE_MDMA2_TCSOE (0x04<<29)
293 #define SBC_IDE_MDMA2_TOECS (0x01<<26)
294 #define SBC_IDE_MDMA2_TWCS (0x01<<28)
295 #define SBC_IDE_MDMA2_TCSH (0x04<<24)
296 #define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
297 #define SBC_IDE_MDMA2_TWP (0x0D<<14)
298 #define SBC_IDE_MDMA2_TCSW (0x04<<10)
299 #define SBC_IDE_MDMA2_TPM (0x00<<6)
300 #define SBC_IDE_MDMA2_TA (0x12<<0)