1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <asm/ip32/ip32_ints.h>
6 * O2 has up to 5 PCI devices connected into the MACE bridge. The device
16 #define SCSI0 MACEPCI_SCSI0_IRQ
17 #define SCSI1 MACEPCI_SCSI1_IRQ
18 #define INTA0 MACEPCI_SLOT0_IRQ
19 #define INTA1 MACEPCI_SLOT1_IRQ
20 #define INTA2 MACEPCI_SLOT2_IRQ
21 #define INTB MACEPCI_SHARED0_IRQ
22 #define INTC MACEPCI_SHARED1_IRQ
23 #define INTD MACEPCI_SHARED2_IRQ
24 static char irq_tab_mace[][5] __initdata = {
25 /* Dummy INT#A INT#B INT#C INT#D */
26 {0, 0, 0, 0, 0}, /* This is placeholder row - never used */
27 {0, SCSI0, SCSI0, SCSI0, SCSI0},
28 {0, SCSI1, SCSI1, SCSI1, SCSI1},
29 {0, INTA0, INTB, INTC, INTD},
30 {0, INTA1, INTC, INTD, INTB},
31 {0, INTA2, INTD, INTB, INTC},
36 * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
37 * the device (1-4 => A-D), tell what irq to use. Note that we don't
38 * in theory have slots 4 and 5, and we never normally use the shared
39 * irqs. I suppose a device without a pin A will thank us for doing it
40 * right if there exists such a broken piece of crap.
42 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
44 return irq_tab_mace[slot][pin];
47 /* Do platform specific device initialization at pci_enable_device() time */
48 int pcibios_plat_dev_init(struct pci_dev *dev)