Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fix
[linux-2.6] / arch / mips / kernel / unaligned.c
1 /*
2  * Handle unaligned accesses by emulation.
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9  * Copyright (C) 1999 Silicon Graphics, Inc.
10  *
11  * This file contains exception handler for address error exception with the
12  * special capability to execute faulting instructions in software.  The
13  * handler does not try to handle the case when the program counter points
14  * to an address not aligned to a word boundary.
15  *
16  * Putting data to unaligned addresses is a bad practice even on Intel where
17  * only the performance is affected.  Much worse is that such code is non-
18  * portable.  Due to several programs that die on MIPS due to alignment
19  * problems I decided to implement this handler anyway though I originally
20  * didn't intend to do this at all for user code.
21  *
22  * For now I enable fixing of address errors by default to make life easier.
23  * I however intend to disable this somewhen in the future when the alignment
24  * problems with user programs have been fixed.  For programmers this is the
25  * right way to go.
26  *
27  * Fixing address errors is a per process option.  The option is inherited
28  * across fork(2) and execve(2) calls.  If you really want to use the
29  * option in your user programs - I discourage the use of the software
30  * emulation strongly - use the following code in your userland stuff:
31  *
32  * #include <sys/sysmips.h>
33  *
34  * ...
35  * sysmips(MIPS_FIXADE, x);
36  * ...
37  *
38  * The argument x is 0 for disabling software emulation, enabled otherwise.
39  *
40  * Below a little program to play around with this feature.
41  *
42  * #include <stdio.h>
43  * #include <sys/sysmips.h>
44  *
45  * struct foo {
46  *         unsigned char bar[8];
47  * };
48  *
49  * main(int argc, char *argv[])
50  * {
51  *         struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
52  *         unsigned int *p = (unsigned int *) (x.bar + 3);
53  *         int i;
54  *
55  *         if (argc > 1)
56  *                 sysmips(MIPS_FIXADE, atoi(argv[1]));
57  *
58  *         printf("*p = %08lx\n", *p);
59  *
60  *         *p = 0xdeadface;
61  *
62  *         for(i = 0; i <= 7; i++)
63  *         printf("%02x ", x.bar[i]);
64  *         printf("\n");
65  * }
66  *
67  * Coprocessor loads are not supported; I think this case is unimportant
68  * in the practice.
69  *
70  * TODO: Handle ndc (attempted store to doubleword in uncached memory)
71  *       exception for the R6000.
72  *       A store crossing a page boundary might be executed only partially.
73  *       Undo the partial store in this case.
74  */
75 #include <linux/mm.h>
76 #include <linux/module.h>
77 #include <linux/signal.h>
78 #include <linux/smp.h>
79 #include <linux/sched.h>
80 #include <asm/asm.h>
81 #include <asm/branch.h>
82 #include <asm/byteorder.h>
83 #include <asm/inst.h>
84 #include <asm/uaccess.h>
85 #include <asm/system.h>
86
87 #define STR(x)  __STR(x)
88 #define __STR(x)  #x
89
90 #ifdef CONFIG_PROC_FS
91 unsigned long unaligned_instructions;
92 #endif
93
94 static inline int emulate_load_store_insn(struct pt_regs *regs,
95         void __user *addr, unsigned int __user *pc,
96         unsigned long **regptr, unsigned long *newvalue)
97 {
98         union mips_instruction insn;
99         unsigned long value;
100         unsigned int res;
101
102         regs->regs[0] = 0;
103         *regptr=NULL;
104
105         /*
106          * This load never faults.
107          */
108         __get_user(insn.word, pc);
109
110         switch (insn.i_format.opcode) {
111         /*
112          * These are instructions that a compiler doesn't generate.  We
113          * can assume therefore that the code is MIPS-aware and
114          * really buggy.  Emulating these instructions would break the
115          * semantics anyway.
116          */
117         case ll_op:
118         case lld_op:
119         case sc_op:
120         case scd_op:
121
122         /*
123          * For these instructions the only way to create an address
124          * error is an attempted access to kernel/supervisor address
125          * space.
126          */
127         case ldl_op:
128         case ldr_op:
129         case lwl_op:
130         case lwr_op:
131         case sdl_op:
132         case sdr_op:
133         case swl_op:
134         case swr_op:
135         case lb_op:
136         case lbu_op:
137         case sb_op:
138                 goto sigbus;
139
140         /*
141          * The remaining opcodes are the ones that are really of interest.
142          */
143         case lh_op:
144                 if (!access_ok(VERIFY_READ, addr, 2))
145                         goto sigbus;
146
147                 __asm__ __volatile__ (".set\tnoat\n"
148 #ifdef __BIG_ENDIAN
149                         "1:\tlb\t%0, 0(%2)\n"
150                         "2:\tlbu\t$1, 1(%2)\n\t"
151 #endif
152 #ifdef __LITTLE_ENDIAN
153                         "1:\tlb\t%0, 1(%2)\n"
154                         "2:\tlbu\t$1, 0(%2)\n\t"
155 #endif
156                         "sll\t%0, 0x8\n\t"
157                         "or\t%0, $1\n\t"
158                         "li\t%1, 0\n"
159                         "3:\t.set\tat\n\t"
160                         ".section\t.fixup,\"ax\"\n\t"
161                         "4:\tli\t%1, %3\n\t"
162                         "j\t3b\n\t"
163                         ".previous\n\t"
164                         ".section\t__ex_table,\"a\"\n\t"
165                         STR(PTR)"\t1b, 4b\n\t"
166                         STR(PTR)"\t2b, 4b\n\t"
167                         ".previous"
168                         : "=&r" (value), "=r" (res)
169                         : "r" (addr), "i" (-EFAULT));
170                 if (res)
171                         goto fault;
172                 *newvalue = value;
173                 *regptr = &regs->regs[insn.i_format.rt];
174                 break;
175
176         case lw_op:
177                 if (!access_ok(VERIFY_READ, addr, 4))
178                         goto sigbus;
179
180                 __asm__ __volatile__ (
181 #ifdef __BIG_ENDIAN
182                         "1:\tlwl\t%0, (%2)\n"
183                         "2:\tlwr\t%0, 3(%2)\n\t"
184 #endif
185 #ifdef __LITTLE_ENDIAN
186                         "1:\tlwl\t%0, 3(%2)\n"
187                         "2:\tlwr\t%0, (%2)\n\t"
188 #endif
189                         "li\t%1, 0\n"
190                         "3:\t.section\t.fixup,\"ax\"\n\t"
191                         "4:\tli\t%1, %3\n\t"
192                         "j\t3b\n\t"
193                         ".previous\n\t"
194                         ".section\t__ex_table,\"a\"\n\t"
195                         STR(PTR)"\t1b, 4b\n\t"
196                         STR(PTR)"\t2b, 4b\n\t"
197                         ".previous"
198                         : "=&r" (value), "=r" (res)
199                         : "r" (addr), "i" (-EFAULT));
200                 if (res)
201                         goto fault;
202                 *newvalue = value;
203                 *regptr = &regs->regs[insn.i_format.rt];
204                 break;
205
206         case lhu_op:
207                 if (!access_ok(VERIFY_READ, addr, 2))
208                         goto sigbus;
209
210                 __asm__ __volatile__ (
211                         ".set\tnoat\n"
212 #ifdef __BIG_ENDIAN
213                         "1:\tlbu\t%0, 0(%2)\n"
214                         "2:\tlbu\t$1, 1(%2)\n\t"
215 #endif
216 #ifdef __LITTLE_ENDIAN
217                         "1:\tlbu\t%0, 1(%2)\n"
218                         "2:\tlbu\t$1, 0(%2)\n\t"
219 #endif
220                         "sll\t%0, 0x8\n\t"
221                         "or\t%0, $1\n\t"
222                         "li\t%1, 0\n"
223                         "3:\t.set\tat\n\t"
224                         ".section\t.fixup,\"ax\"\n\t"
225                         "4:\tli\t%1, %3\n\t"
226                         "j\t3b\n\t"
227                         ".previous\n\t"
228                         ".section\t__ex_table,\"a\"\n\t"
229                         STR(PTR)"\t1b, 4b\n\t"
230                         STR(PTR)"\t2b, 4b\n\t"
231                         ".previous"
232                         : "=&r" (value), "=r" (res)
233                         : "r" (addr), "i" (-EFAULT));
234                 if (res)
235                         goto fault;
236                 *newvalue = value;
237                 *regptr = &regs->regs[insn.i_format.rt];
238                 break;
239
240         case lwu_op:
241 #ifdef CONFIG_64BIT
242                 /*
243                  * A 32-bit kernel might be running on a 64-bit processor.  But
244                  * if we're on a 32-bit processor and an i-cache incoherency
245                  * or race makes us see a 64-bit instruction here the sdl/sdr
246                  * would blow up, so for now we don't handle unaligned 64-bit
247                  * instructions on 32-bit kernels.
248                  */
249                 if (!access_ok(VERIFY_READ, addr, 4))
250                         goto sigbus;
251
252                 __asm__ __volatile__ (
253 #ifdef __BIG_ENDIAN
254                         "1:\tlwl\t%0, (%2)\n"
255                         "2:\tlwr\t%0, 3(%2)\n\t"
256 #endif
257 #ifdef __LITTLE_ENDIAN
258                         "1:\tlwl\t%0, 3(%2)\n"
259                         "2:\tlwr\t%0, (%2)\n\t"
260 #endif
261                         "dsll\t%0, %0, 32\n\t"
262                         "dsrl\t%0, %0, 32\n\t"
263                         "li\t%1, 0\n"
264                         "3:\t.section\t.fixup,\"ax\"\n\t"
265                         "4:\tli\t%1, %3\n\t"
266                         "j\t3b\n\t"
267                         ".previous\n\t"
268                         ".section\t__ex_table,\"a\"\n\t"
269                         STR(PTR)"\t1b, 4b\n\t"
270                         STR(PTR)"\t2b, 4b\n\t"
271                         ".previous"
272                         : "=&r" (value), "=r" (res)
273                         : "r" (addr), "i" (-EFAULT));
274                 if (res)
275                         goto fault;
276                 *newvalue = value;
277                 *regptr = &regs->regs[insn.i_format.rt];
278                 break;
279 #endif /* CONFIG_64BIT */
280
281                 /* Cannot handle 64-bit instructions in 32-bit kernel */
282                 goto sigill;
283
284         case ld_op:
285 #ifdef CONFIG_64BIT
286                 /*
287                  * A 32-bit kernel might be running on a 64-bit processor.  But
288                  * if we're on a 32-bit processor and an i-cache incoherency
289                  * or race makes us see a 64-bit instruction here the sdl/sdr
290                  * would blow up, so for now we don't handle unaligned 64-bit
291                  * instructions on 32-bit kernels.
292                  */
293                 if (!access_ok(VERIFY_READ, addr, 8))
294                         goto sigbus;
295
296                 __asm__ __volatile__ (
297 #ifdef __BIG_ENDIAN
298                         "1:\tldl\t%0, (%2)\n"
299                         "2:\tldr\t%0, 7(%2)\n\t"
300 #endif
301 #ifdef __LITTLE_ENDIAN
302                         "1:\tldl\t%0, 7(%2)\n"
303                         "2:\tldr\t%0, (%2)\n\t"
304 #endif
305                         "li\t%1, 0\n"
306                         "3:\t.section\t.fixup,\"ax\"\n\t"
307                         "4:\tli\t%1, %3\n\t"
308                         "j\t3b\n\t"
309                         ".previous\n\t"
310                         ".section\t__ex_table,\"a\"\n\t"
311                         STR(PTR)"\t1b, 4b\n\t"
312                         STR(PTR)"\t2b, 4b\n\t"
313                         ".previous"
314                         : "=&r" (value), "=r" (res)
315                         : "r" (addr), "i" (-EFAULT));
316                 if (res)
317                         goto fault;
318                 *newvalue = value;
319                 *regptr = &regs->regs[insn.i_format.rt];
320                 break;
321 #endif /* CONFIG_64BIT */
322
323                 /* Cannot handle 64-bit instructions in 32-bit kernel */
324                 goto sigill;
325
326         case sh_op:
327                 if (!access_ok(VERIFY_WRITE, addr, 2))
328                         goto sigbus;
329
330                 value = regs->regs[insn.i_format.rt];
331                 __asm__ __volatile__ (
332 #ifdef __BIG_ENDIAN
333                         ".set\tnoat\n"
334                         "1:\tsb\t%1, 1(%2)\n\t"
335                         "srl\t$1, %1, 0x8\n"
336                         "2:\tsb\t$1, 0(%2)\n\t"
337                         ".set\tat\n\t"
338 #endif
339 #ifdef __LITTLE_ENDIAN
340                         ".set\tnoat\n"
341                         "1:\tsb\t%1, 0(%2)\n\t"
342                         "srl\t$1,%1, 0x8\n"
343                         "2:\tsb\t$1, 1(%2)\n\t"
344                         ".set\tat\n\t"
345 #endif
346                         "li\t%0, 0\n"
347                         "3:\n\t"
348                         ".section\t.fixup,\"ax\"\n\t"
349                         "4:\tli\t%0, %3\n\t"
350                         "j\t3b\n\t"
351                         ".previous\n\t"
352                         ".section\t__ex_table,\"a\"\n\t"
353                         STR(PTR)"\t1b, 4b\n\t"
354                         STR(PTR)"\t2b, 4b\n\t"
355                         ".previous"
356                         : "=r" (res)
357                         : "r" (value), "r" (addr), "i" (-EFAULT));
358                 if (res)
359                         goto fault;
360                 break;
361
362         case sw_op:
363                 if (!access_ok(VERIFY_WRITE, addr, 4))
364                         goto sigbus;
365
366                 value = regs->regs[insn.i_format.rt];
367                 __asm__ __volatile__ (
368 #ifdef __BIG_ENDIAN
369                         "1:\tswl\t%1,(%2)\n"
370                         "2:\tswr\t%1, 3(%2)\n\t"
371 #endif
372 #ifdef __LITTLE_ENDIAN
373                         "1:\tswl\t%1, 3(%2)\n"
374                         "2:\tswr\t%1, (%2)\n\t"
375 #endif
376                         "li\t%0, 0\n"
377                         "3:\n\t"
378                         ".section\t.fixup,\"ax\"\n\t"
379                         "4:\tli\t%0, %3\n\t"
380                         "j\t3b\n\t"
381                         ".previous\n\t"
382                         ".section\t__ex_table,\"a\"\n\t"
383                         STR(PTR)"\t1b, 4b\n\t"
384                         STR(PTR)"\t2b, 4b\n\t"
385                         ".previous"
386                 : "=r" (res)
387                 : "r" (value), "r" (addr), "i" (-EFAULT));
388                 if (res)
389                         goto fault;
390                 break;
391
392         case sd_op:
393 #ifdef CONFIG_64BIT
394                 /*
395                  * A 32-bit kernel might be running on a 64-bit processor.  But
396                  * if we're on a 32-bit processor and an i-cache incoherency
397                  * or race makes us see a 64-bit instruction here the sdl/sdr
398                  * would blow up, so for now we don't handle unaligned 64-bit
399                  * instructions on 32-bit kernels.
400                  */
401                 if (!access_ok(VERIFY_WRITE, addr, 8))
402                         goto sigbus;
403
404                 value = regs->regs[insn.i_format.rt];
405                 __asm__ __volatile__ (
406 #ifdef __BIG_ENDIAN
407                         "1:\tsdl\t%1,(%2)\n"
408                         "2:\tsdr\t%1, 7(%2)\n\t"
409 #endif
410 #ifdef __LITTLE_ENDIAN
411                         "1:\tsdl\t%1, 7(%2)\n"
412                         "2:\tsdr\t%1, (%2)\n\t"
413 #endif
414                         "li\t%0, 0\n"
415                         "3:\n\t"
416                         ".section\t.fixup,\"ax\"\n\t"
417                         "4:\tli\t%0, %3\n\t"
418                         "j\t3b\n\t"
419                         ".previous\n\t"
420                         ".section\t__ex_table,\"a\"\n\t"
421                         STR(PTR)"\t1b, 4b\n\t"
422                         STR(PTR)"\t2b, 4b\n\t"
423                         ".previous"
424                 : "=r" (res)
425                 : "r" (value), "r" (addr), "i" (-EFAULT));
426                 if (res)
427                         goto fault;
428                 break;
429 #endif /* CONFIG_64BIT */
430
431                 /* Cannot handle 64-bit instructions in 32-bit kernel */
432                 goto sigill;
433
434         case lwc1_op:
435         case ldc1_op:
436         case swc1_op:
437         case sdc1_op:
438                 /*
439                  * I herewith declare: this does not happen.  So send SIGBUS.
440                  */
441                 goto sigbus;
442
443         case lwc2_op:
444         case ldc2_op:
445         case swc2_op:
446         case sdc2_op:
447                 /*
448                  * These are the coprocessor 2 load/stores.  The current
449                  * implementations don't use cp2 and cp2 should always be
450                  * disabled in c0_status.  So send SIGILL.
451                  * (No longer true: The Sony Praystation uses cp2 for
452                  * 3D matrix operations.  Dunno if that thingy has a MMU ...)
453                  */
454         default:
455                 /*
456                  * Pheeee...  We encountered an yet unknown instruction or
457                  * cache coherence problem.  Die sucker, die ...
458                  */
459                 goto sigill;
460         }
461
462 #ifdef CONFIG_PROC_FS
463         unaligned_instructions++;
464 #endif
465
466         return 0;
467
468 fault:
469         /* Did we have an exception handler installed? */
470         if (fixup_exception(regs))
471                 return 1;
472
473         die_if_kernel ("Unhandled kernel unaligned access", regs);
474         send_sig(SIGSEGV, current, 1);
475
476         return 0;
477
478 sigbus:
479         die_if_kernel("Unhandled kernel unaligned access", regs);
480         send_sig(SIGBUS, current, 1);
481
482         return 0;
483
484 sigill:
485         die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
486         send_sig(SIGILL, current, 1);
487
488         return 0;
489 }
490
491 asmlinkage void do_ade(struct pt_regs *regs)
492 {
493         unsigned long *regptr, newval;
494         extern int do_dsemulret(struct pt_regs *);
495         unsigned int __user *pc;
496         mm_segment_t seg;
497
498         /*
499          * Address errors may be deliberately induced by the FPU emulator to
500          * retake control of the CPU after executing the instruction in the
501          * delay slot of an emulated branch.
502          */
503         /* Terminate if exception was recognized as a delay slot return */
504         if (do_dsemulret(regs))
505                 return;
506
507         /* Otherwise handle as normal */
508
509         /*
510          * Did we catch a fault trying to load an instruction?
511          * Or are we running in MIPS16 mode?
512          */
513         if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
514                 goto sigbus;
515
516         pc = (unsigned int __user *) exception_epc(regs);
517         if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0)
518                 goto sigbus;
519
520         /*
521          * Do branch emulation only if we didn't forward the exception.
522          * This is all so but ugly ...
523          */
524         seg = get_fs();
525         if (!user_mode(regs))
526                 set_fs(KERNEL_DS);
527         if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
528                                      &regptr, &newval)) {
529                 compute_return_epc(regs);
530                 /*
531                  * Now that branch is evaluated, update the dest
532                  * register if necessary
533                  */
534                 if (regptr)
535                         *regptr = newval;
536         }
537         set_fs(seg);
538
539         return;
540
541 sigbus:
542         die_if_kernel("Kernel unaligned instruction access", regs);
543         force_sig(SIGBUS, current);
544
545         /*
546          * XXX On return from the signal handler we should advance the epc
547          */
548 }