sh: sh7785 pinmux support
[linux-2.6] / arch / sh / kernel / traps_32.c
1 /*
2  * 'traps.c' handles hardware traps and faults after we have saved some
3  * state in 'entry.S'.
4  *
5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
6  *                  Copyright (C) 2000 Philipp Rumpf
7  *                  Copyright (C) 2000 David Howells
8  *                  Copyright (C) 2002 - 2007 Paul Mundt
9  *
10  * This file is subject to the terms and conditions of the GNU General Public
11  * License.  See the file "COPYING" in the main directory of this archive
12  * for more details.
13  */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
20 #include <linux/io.h>
21 #include <linux/bug.h>
22 #include <linux/debug_locks.h>
23 #include <linux/kdebug.h>
24 #include <linux/kexec.h>
25 #include <linux/limits.h>
26 #include <asm/system.h>
27 #include <asm/uaccess.h>
28 #include <asm/fpu.h>
29 #include <asm/kprobes.h>
30
31 #ifdef CONFIG_SH_KGDB
32 #include <asm/kgdb.h>
33 #define CHK_REMOTE_DEBUG(regs)                  \
34 {                                               \
35         if (kgdb_debug_hook && !user_mode(regs))\
36                 (*kgdb_debug_hook)(regs);       \
37 }
38 #else
39 #define CHK_REMOTE_DEBUG(regs)
40 #endif
41
42 #ifdef CONFIG_CPU_SH2
43 # define TRAP_RESERVED_INST     4
44 # define TRAP_ILLEGAL_SLOT_INST 6
45 # define TRAP_ADDRESS_ERROR     9
46 # ifdef CONFIG_CPU_SH2A
47 #  define TRAP_FPU_ERROR        13
48 #  define TRAP_DIVZERO_ERROR    17
49 #  define TRAP_DIVOVF_ERROR     18
50 # endif
51 #else
52 #define TRAP_RESERVED_INST      12
53 #define TRAP_ILLEGAL_SLOT_INST  13
54 #endif
55
56 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
57 {
58         unsigned long p;
59         int i;
60
61         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
62
63         for (p = bottom & ~31; p < top; ) {
64                 printk("%04lx: ", p & 0xffff);
65
66                 for (i = 0; i < 8; i++, p += 4) {
67                         unsigned int val;
68
69                         if (p < bottom || p >= top)
70                                 printk("         ");
71                         else {
72                                 if (__get_user(val, (unsigned int __user *)p)) {
73                                         printk("\n");
74                                         return;
75                                 }
76                                 printk("%08x ", val);
77                         }
78                 }
79                 printk("\n");
80         }
81 }
82
83 static DEFINE_SPINLOCK(die_lock);
84
85 void die(const char * str, struct pt_regs * regs, long err)
86 {
87         static int die_counter;
88
89         oops_enter();
90
91         console_verbose();
92         spin_lock_irq(&die_lock);
93         bust_spinlocks(1);
94
95         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
96
97         CHK_REMOTE_DEBUG(regs);
98         print_modules();
99         show_regs(regs);
100
101         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
102                         task_pid_nr(current), task_stack_page(current) + 1);
103
104         if (!user_mode(regs) || in_interrupt())
105                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
106                          (unsigned long)task_stack_page(current));
107
108         notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
109
110         bust_spinlocks(0);
111         add_taint(TAINT_DIE);
112         spin_unlock_irq(&die_lock);
113
114         if (kexec_should_crash(current))
115                 crash_kexec(regs);
116
117         if (in_interrupt())
118                 panic("Fatal exception in interrupt");
119
120         if (panic_on_oops)
121                 panic("Fatal exception");
122
123         oops_exit();
124         do_exit(SIGSEGV);
125 }
126
127 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
128                                  long err)
129 {
130         if (!user_mode(regs))
131                 die(str, regs, err);
132 }
133
134 /*
135  * try and fix up kernelspace address errors
136  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
137  * - kernel/userspace interfaces cause a jump to an appropriate handler
138  * - other kernel errors are bad
139  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
140  */
141 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
142 {
143         if (!user_mode(regs)) {
144                 const struct exception_table_entry *fixup;
145                 fixup = search_exception_tables(regs->pc);
146                 if (fixup) {
147                         regs->pc = fixup->fixup;
148                         return 0;
149                 }
150                 die(str, regs, err);
151         }
152         return -EFAULT;
153 }
154
155 static inline void sign_extend(unsigned int count, unsigned char *dst)
156 {
157 #ifdef __LITTLE_ENDIAN__
158         if ((count == 1) && dst[0] & 0x80) {
159                 dst[1] = 0xff;
160                 dst[2] = 0xff;
161                 dst[3] = 0xff;
162         }
163         if ((count == 2) && dst[1] & 0x80) {
164                 dst[2] = 0xff;
165                 dst[3] = 0xff;
166         }
167 #else
168         if ((count == 1) && dst[3] & 0x80) {
169                 dst[2] = 0xff;
170                 dst[1] = 0xff;
171                 dst[0] = 0xff;
172         }
173         if ((count == 2) && dst[2] & 0x80) {
174                 dst[1] = 0xff;
175                 dst[0] = 0xff;
176         }
177 #endif
178 }
179
180 static struct mem_access user_mem_access = {
181         copy_from_user,
182         copy_to_user,
183 };
184
185 /*
186  * handle an instruction that does an unaligned memory access by emulating the
187  * desired behaviour
188  * - note that PC _may not_ point to the faulting instruction
189  *   (if that instruction is in a branch delay slot)
190  * - return 0 if emulation okay, -EFAULT on existential error
191  */
192 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
193                                 struct mem_access *ma)
194 {
195         int ret, index, count;
196         unsigned long *rm, *rn;
197         unsigned char *src, *dst;
198         unsigned char __user *srcu, *dstu;
199
200         index = (instruction>>8)&15;    /* 0x0F00 */
201         rn = &regs->regs[index];
202
203         index = (instruction>>4)&15;    /* 0x00F0 */
204         rm = &regs->regs[index];
205
206         count = 1<<(instruction&3);
207
208         ret = -EFAULT;
209         switch (instruction>>12) {
210         case 0: /* mov.[bwl] to/from memory via r0+rn */
211                 if (instruction & 8) {
212                         /* from memory */
213                         srcu = (unsigned char __user *)*rm;
214                         srcu += regs->regs[0];
215                         dst = (unsigned char *)rn;
216                         *(unsigned long *)dst = 0;
217
218 #if !defined(__LITTLE_ENDIAN__)
219                         dst += 4-count;
220 #endif
221                         if (ma->from(dst, srcu, count))
222                                 goto fetch_fault;
223
224                         sign_extend(count, dst);
225                 } else {
226                         /* to memory */
227                         src = (unsigned char *)rm;
228 #if !defined(__LITTLE_ENDIAN__)
229                         src += 4-count;
230 #endif
231                         dstu = (unsigned char __user *)*rn;
232                         dstu += regs->regs[0];
233
234                         if (ma->to(dstu, src, count))
235                                 goto fetch_fault;
236                 }
237                 ret = 0;
238                 break;
239
240         case 1: /* mov.l Rm,@(disp,Rn) */
241                 src = (unsigned char*) rm;
242                 dstu = (unsigned char __user *)*rn;
243                 dstu += (instruction&0x000F)<<2;
244
245                 if (ma->to(dstu, src, 4))
246                         goto fetch_fault;
247                 ret = 0;
248                 break;
249
250         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
251                 if (instruction & 4)
252                         *rn -= count;
253                 src = (unsigned char*) rm;
254                 dstu = (unsigned char __user *)*rn;
255 #if !defined(__LITTLE_ENDIAN__)
256                 src += 4-count;
257 #endif
258                 if (ma->to(dstu, src, count))
259                         goto fetch_fault;
260                 ret = 0;
261                 break;
262
263         case 5: /* mov.l @(disp,Rm),Rn */
264                 srcu = (unsigned char __user *)*rm;
265                 srcu += (instruction & 0x000F) << 2;
266                 dst = (unsigned char *)rn;
267                 *(unsigned long *)dst = 0;
268
269                 if (ma->from(dst, srcu, 4))
270                         goto fetch_fault;
271                 ret = 0;
272                 break;
273
274         case 6: /* mov.[bwl] from memory, possibly with post-increment */
275                 srcu = (unsigned char __user *)*rm;
276                 if (instruction & 4)
277                         *rm += count;
278                 dst = (unsigned char*) rn;
279                 *(unsigned long*)dst = 0;
280
281 #if !defined(__LITTLE_ENDIAN__)
282                 dst += 4-count;
283 #endif
284                 if (ma->from(dst, srcu, count))
285                         goto fetch_fault;
286                 sign_extend(count, dst);
287                 ret = 0;
288                 break;
289
290         case 8:
291                 switch ((instruction&0xFF00)>>8) {
292                 case 0x81: /* mov.w R0,@(disp,Rn) */
293                         src = (unsigned char *) &regs->regs[0];
294 #if !defined(__LITTLE_ENDIAN__)
295                         src += 2;
296 #endif
297                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
298                         dstu += (instruction & 0x000F) << 1;
299
300                         if (ma->to(dstu, src, 2))
301                                 goto fetch_fault;
302                         ret = 0;
303                         break;
304
305                 case 0x85: /* mov.w @(disp,Rm),R0 */
306                         srcu = (unsigned char __user *)*rm;
307                         srcu += (instruction & 0x000F) << 1;
308                         dst = (unsigned char *) &regs->regs[0];
309                         *(unsigned long *)dst = 0;
310
311 #if !defined(__LITTLE_ENDIAN__)
312                         dst += 2;
313 #endif
314                         if (ma->from(dst, srcu, 2))
315                                 goto fetch_fault;
316                         sign_extend(2, dst);
317                         ret = 0;
318                         break;
319                 }
320                 break;
321         }
322         return ret;
323
324  fetch_fault:
325         /* Argh. Address not only misaligned but also non-existent.
326          * Raise an EFAULT and see if it's trapped
327          */
328         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
329 }
330
331 /*
332  * emulate the instruction in the delay slot
333  * - fetches the instruction from PC+2
334  */
335 static inline int handle_delayslot(struct pt_regs *regs,
336                                    opcode_t old_instruction,
337                                    struct mem_access *ma)
338 {
339         opcode_t instruction;
340         void __user *addr = (void __user *)(regs->pc +
341                 instruction_size(old_instruction));
342
343         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
344                 /* the instruction-fetch faulted */
345                 if (user_mode(regs))
346                         return -EFAULT;
347
348                 /* kernel */
349                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
350                     regs, 0);
351         }
352
353         return handle_unaligned_ins(instruction, regs, ma);
354 }
355
356 /*
357  * handle an instruction that does an unaligned memory access
358  * - have to be careful of branch delay-slot instructions that fault
359  *  SH3:
360  *   - if the branch would be taken PC points to the branch
361  *   - if the branch would not be taken, PC points to delay-slot
362  *  SH4:
363  *   - PC always points to delayed branch
364  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
365  */
366
367 /* Macros to determine offset from current PC for branch instructions */
368 /* Explicit type coercion is used to force sign extension where needed */
369 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
370 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
371
372 /*
373  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
374  * opcodes..
375  */
376
377 static int handle_unaligned_notify_count = 10;
378
379 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
380                             struct mem_access *ma)
381 {
382         u_int rm;
383         int ret, index;
384
385         index = (instruction>>8)&15;    /* 0x0F00 */
386         rm = regs->regs[index];
387
388         /* shout about the first ten userspace fixups */
389         if (user_mode(regs) && handle_unaligned_notify_count>0) {
390                 handle_unaligned_notify_count--;
391
392                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
393                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
394                        current->comm, task_pid_nr(current),
395                        (void *)regs->pc, instruction);
396         }
397
398         ret = -EFAULT;
399         switch (instruction&0xF000) {
400         case 0x0000:
401                 if (instruction==0x000B) {
402                         /* rts */
403                         ret = handle_delayslot(regs, instruction, ma);
404                         if (ret==0)
405                                 regs->pc = regs->pr;
406                 }
407                 else if ((instruction&0x00FF)==0x0023) {
408                         /* braf @Rm */
409                         ret = handle_delayslot(regs, instruction, ma);
410                         if (ret==0)
411                                 regs->pc += rm + 4;
412                 }
413                 else if ((instruction&0x00FF)==0x0003) {
414                         /* bsrf @Rm */
415                         ret = handle_delayslot(regs, instruction, ma);
416                         if (ret==0) {
417                                 regs->pr = regs->pc + 4;
418                                 regs->pc += rm + 4;
419                         }
420                 }
421                 else {
422                         /* mov.[bwl] to/from memory via r0+rn */
423                         goto simple;
424                 }
425                 break;
426
427         case 0x1000: /* mov.l Rm,@(disp,Rn) */
428                 goto simple;
429
430         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
431                 goto simple;
432
433         case 0x4000:
434                 if ((instruction&0x00FF)==0x002B) {
435                         /* jmp @Rm */
436                         ret = handle_delayslot(regs, instruction, ma);
437                         if (ret==0)
438                                 regs->pc = rm;
439                 }
440                 else if ((instruction&0x00FF)==0x000B) {
441                         /* jsr @Rm */
442                         ret = handle_delayslot(regs, instruction, ma);
443                         if (ret==0) {
444                                 regs->pr = regs->pc + 4;
445                                 regs->pc = rm;
446                         }
447                 }
448                 else {
449                         /* mov.[bwl] to/from memory via r0+rn */
450                         goto simple;
451                 }
452                 break;
453
454         case 0x5000: /* mov.l @(disp,Rm),Rn */
455                 goto simple;
456
457         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
458                 goto simple;
459
460         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
461                 switch (instruction&0x0F00) {
462                 case 0x0100: /* mov.w R0,@(disp,Rm) */
463                         goto simple;
464                 case 0x0500: /* mov.w @(disp,Rm),R0 */
465                         goto simple;
466                 case 0x0B00: /* bf   lab - no delayslot*/
467                         break;
468                 case 0x0F00: /* bf/s lab */
469                         ret = handle_delayslot(regs, instruction, ma);
470                         if (ret==0) {
471 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
472                                 if ((regs->sr & 0x00000001) != 0)
473                                         regs->pc += 4; /* next after slot */
474                                 else
475 #endif
476                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
477                         }
478                         break;
479                 case 0x0900: /* bt   lab - no delayslot */
480                         break;
481                 case 0x0D00: /* bt/s lab */
482                         ret = handle_delayslot(regs, instruction, ma);
483                         if (ret==0) {
484 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
485                                 if ((regs->sr & 0x00000001) == 0)
486                                         regs->pc += 4; /* next after slot */
487                                 else
488 #endif
489                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
490                         }
491                         break;
492                 }
493                 break;
494
495         case 0xA000: /* bra label */
496                 ret = handle_delayslot(regs, instruction, ma);
497                 if (ret==0)
498                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
499                 break;
500
501         case 0xB000: /* bsr label */
502                 ret = handle_delayslot(regs, instruction, ma);
503                 if (ret==0) {
504                         regs->pr = regs->pc + 4;
505                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
506                 }
507                 break;
508         }
509         return ret;
510
511         /* handle non-delay-slot instruction */
512  simple:
513         ret = handle_unaligned_ins(instruction, regs, ma);
514         if (ret==0)
515                 regs->pc += instruction_size(instruction);
516         return ret;
517 }
518
519 /*
520  * Handle various address error exceptions:
521  *  - instruction address error:
522  *       misaligned PC
523  *       PC >= 0x80000000 in user mode
524  *  - data address error (read and write)
525  *       misaligned data access
526  *       access to >= 0x80000000 is user mode
527  * Unfortuntaly we can't distinguish between instruction address error
528  * and data address errors caused by read accesses.
529  */
530 asmlinkage void do_address_error(struct pt_regs *regs,
531                                  unsigned long writeaccess,
532                                  unsigned long address)
533 {
534         unsigned long error_code = 0;
535         mm_segment_t oldfs;
536         siginfo_t info;
537         opcode_t instruction;
538         int tmp;
539
540         /* Intentional ifdef */
541 #ifdef CONFIG_CPU_HAS_SR_RB
542         error_code = lookup_exception_vector();
543 #endif
544
545         oldfs = get_fs();
546
547         if (user_mode(regs)) {
548                 int si_code = BUS_ADRERR;
549
550                 local_irq_enable();
551
552                 /* bad PC is not something we can fix */
553                 if (regs->pc & 1) {
554                         si_code = BUS_ADRALN;
555                         goto uspace_segv;
556                 }
557
558                 set_fs(USER_DS);
559                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
560                                    sizeof(instruction))) {
561                         /* Argh. Fault on the instruction itself.
562                            This should never happen non-SMP
563                         */
564                         set_fs(oldfs);
565                         goto uspace_segv;
566                 }
567
568                 tmp = handle_unaligned_access(instruction, regs,
569                                               &user_mem_access);
570                 set_fs(oldfs);
571
572                 if (tmp==0)
573                         return; /* sorted */
574 uspace_segv:
575                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
576                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
577                        regs->pr);
578
579                 info.si_signo = SIGBUS;
580                 info.si_errno = 0;
581                 info.si_code = si_code;
582                 info.si_addr = (void __user *)address;
583                 force_sig_info(SIGBUS, &info, current);
584         } else {
585                 if (regs->pc & 1)
586                         die("unaligned program counter", regs, error_code);
587
588                 set_fs(KERNEL_DS);
589                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
590                                    sizeof(instruction))) {
591                         /* Argh. Fault on the instruction itself.
592                            This should never happen non-SMP
593                         */
594                         set_fs(oldfs);
595                         die("insn faulting in do_address_error", regs, 0);
596                 }
597
598                 handle_unaligned_access(instruction, regs, &user_mem_access);
599                 set_fs(oldfs);
600         }
601 }
602
603 #ifdef CONFIG_SH_DSP
604 /*
605  *      SH-DSP support gerg@snapgear.com.
606  */
607 int is_dsp_inst(struct pt_regs *regs)
608 {
609         unsigned short inst = 0;
610
611         /*
612          * Safe guard if DSP mode is already enabled or we're lacking
613          * the DSP altogether.
614          */
615         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
616                 return 0;
617
618         get_user(inst, ((unsigned short *) regs->pc));
619
620         inst &= 0xf000;
621
622         /* Check for any type of DSP or support instruction */
623         if ((inst == 0xf000) || (inst == 0x4000))
624                 return 1;
625
626         return 0;
627 }
628 #else
629 #define is_dsp_inst(regs)       (0)
630 #endif /* CONFIG_SH_DSP */
631
632 #ifdef CONFIG_CPU_SH2A
633 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
634                                 unsigned long r6, unsigned long r7,
635                                 struct pt_regs __regs)
636 {
637         siginfo_t info;
638
639         switch (r4) {
640         case TRAP_DIVZERO_ERROR:
641                 info.si_code = FPE_INTDIV;
642                 break;
643         case TRAP_DIVOVF_ERROR:
644                 info.si_code = FPE_INTOVF;
645                 break;
646         }
647
648         force_sig_info(SIGFPE, &info, current);
649 }
650 #endif
651
652 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
653                                 unsigned long r6, unsigned long r7,
654                                 struct pt_regs __regs)
655 {
656         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
657         unsigned long error_code;
658         struct task_struct *tsk = current;
659
660 #ifdef CONFIG_SH_FPU_EMU
661         unsigned short inst = 0;
662         int err;
663
664         get_user(inst, (unsigned short*)regs->pc);
665
666         err = do_fpu_inst(inst, regs);
667         if (!err) {
668                 regs->pc += instruction_size(inst);
669                 return;
670         }
671         /* not a FPU inst. */
672 #endif
673
674 #ifdef CONFIG_SH_DSP
675         /* Check if it's a DSP instruction */
676         if (is_dsp_inst(regs)) {
677                 /* Enable DSP mode, and restart instruction. */
678                 regs->sr |= SR_DSP;
679                 return;
680         }
681 #endif
682
683         error_code = lookup_exception_vector();
684
685         local_irq_enable();
686         CHK_REMOTE_DEBUG(regs);
687         force_sig(SIGILL, tsk);
688         die_if_no_fixup("reserved instruction", regs, error_code);
689 }
690
691 #ifdef CONFIG_SH_FPU_EMU
692 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
693 {
694         /*
695          * bfs: 8fxx: PC+=d*2+4;
696          * bts: 8dxx: PC+=d*2+4;
697          * bra: axxx: PC+=D*2+4;
698          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
699          * braf:0x23: PC+=Rn*2+4;
700          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
701          * jmp: 4x2b: PC=Rn;
702          * jsr: 4x0b: PC=Rn      after PR=PC+4;
703          * rts: 000b: PC=PR;
704          */
705         if ((inst & 0xfd00) == 0x8d00) {
706                 regs->pc += SH_PC_8BIT_OFFSET(inst);
707                 return 0;
708         }
709
710         if ((inst & 0xe000) == 0xa000) {
711                 regs->pc += SH_PC_12BIT_OFFSET(inst);
712                 return 0;
713         }
714
715         if ((inst & 0xf0df) == 0x0003) {
716                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
717                 return 0;
718         }
719
720         if ((inst & 0xf0df) == 0x400b) {
721                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
722                 return 0;
723         }
724
725         if ((inst & 0xffff) == 0x000b) {
726                 regs->pc = regs->pr;
727                 return 0;
728         }
729
730         return 1;
731 }
732 #endif
733
734 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
735                                 unsigned long r6, unsigned long r7,
736                                 struct pt_regs __regs)
737 {
738         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
739         unsigned long inst;
740         struct task_struct *tsk = current;
741
742         if (kprobe_handle_illslot(regs->pc) == 0)
743                 return;
744
745 #ifdef CONFIG_SH_FPU_EMU
746         get_user(inst, (unsigned short *)regs->pc + 1);
747         if (!do_fpu_inst(inst, regs)) {
748                 get_user(inst, (unsigned short *)regs->pc);
749                 if (!emulate_branch(inst, regs))
750                         return;
751                 /* fault in branch.*/
752         }
753         /* not a FPU inst. */
754 #endif
755
756         inst = lookup_exception_vector();
757
758         local_irq_enable();
759         CHK_REMOTE_DEBUG(regs);
760         force_sig(SIGILL, tsk);
761         die_if_no_fixup("illegal slot instruction", regs, inst);
762 }
763
764 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
765                                    unsigned long r6, unsigned long r7,
766                                    struct pt_regs __regs)
767 {
768         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
769         long ex;
770
771         ex = lookup_exception_vector();
772         die_if_kernel("exception", regs, ex);
773 }
774
775 #if defined(CONFIG_SH_STANDARD_BIOS)
776 void *gdb_vbr_vector;
777
778 static inline void __init gdb_vbr_init(void)
779 {
780         register unsigned long vbr;
781
782         /*
783          * Read the old value of the VBR register to initialise
784          * the vector through which debug and BIOS traps are
785          * delegated by the Linux trap handler.
786          */
787         asm volatile("stc vbr, %0" : "=r" (vbr));
788
789         gdb_vbr_vector = (void *)(vbr + 0x100);
790         printk("Setting GDB trap vector to 0x%08lx\n",
791                (unsigned long)gdb_vbr_vector);
792 }
793 #endif
794
795 void __cpuinit per_cpu_trap_init(void)
796 {
797         extern void *vbr_base;
798
799 #ifdef CONFIG_SH_STANDARD_BIOS
800         if (raw_smp_processor_id() == 0)
801                 gdb_vbr_init();
802 #endif
803
804         /* NOTE: The VBR value should be at P1
805            (or P2, virtural "fixed" address space).
806            It's definitely should not in physical address.  */
807
808         asm volatile("ldc       %0, vbr"
809                      : /* no output */
810                      : "r" (&vbr_base)
811                      : "memory");
812 }
813
814 void *set_exception_table_vec(unsigned int vec, void *handler)
815 {
816         extern void *exception_handling_table[];
817         void *old_handler;
818
819         old_handler = exception_handling_table[vec];
820         exception_handling_table[vec] = handler;
821         return old_handler;
822 }
823
824 void __init trap_init(void)
825 {
826         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
827         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
828
829 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
830     defined(CONFIG_SH_FPU_EMU)
831         /*
832          * For SH-4 lacking an FPU, treat floating point instructions as
833          * reserved. They'll be handled in the math-emu case, or faulted on
834          * otherwise.
835          */
836         set_exception_table_evt(0x800, do_reserved_inst);
837         set_exception_table_evt(0x820, do_illegal_slot_inst);
838 #elif defined(CONFIG_SH_FPU)
839 #ifdef CONFIG_CPU_SUBTYPE_SHX3
840         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
841         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
842 #else
843         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
844         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
845 #endif
846 #endif
847
848 #ifdef CONFIG_CPU_SH2
849         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
850 #endif
851 #ifdef CONFIG_CPU_SH2A
852         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
853         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
854 #ifdef CONFIG_SH_FPU
855         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
856 #endif
857 #endif
858
859         /* Setup VBR for boot cpu */
860         per_cpu_trap_init();
861 }
862
863 void show_trace(struct task_struct *tsk, unsigned long *sp,
864                 struct pt_regs *regs)
865 {
866         unsigned long addr;
867
868         if (regs && user_mode(regs))
869                 return;
870
871         printk("\nCall trace: ");
872 #ifdef CONFIG_KALLSYMS
873         printk("\n");
874 #endif
875
876         while (!kstack_end(sp)) {
877                 addr = *sp++;
878                 if (kernel_text_address(addr))
879                         print_ip_sym(addr);
880         }
881
882         printk("\n");
883
884         if (!tsk)
885                 tsk = current;
886
887         debug_show_held_locks(tsk);
888 }
889
890 void show_stack(struct task_struct *tsk, unsigned long *sp)
891 {
892         unsigned long stack;
893
894         if (!tsk)
895                 tsk = current;
896         if (tsk == current)
897                 sp = (unsigned long *)current_stack_pointer;
898         else
899                 sp = (unsigned long *)tsk->thread.sp;
900
901         stack = (unsigned long)sp;
902         dump_mem("Stack: ", stack, THREAD_SIZE +
903                  (unsigned long)task_stack_page(tsk));
904         show_trace(tsk, sp, NULL);
905 }
906
907 void dump_stack(void)
908 {
909         show_stack(NULL, NULL);
910 }
911 EXPORT_SYMBOL(dump_stack);