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   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/clk.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/dma.h>
  21
  22 #include <mach/regs-sdi.h>
  23 #include <mach/regs-gpio.h>
  24
  25 #include <asm/plat-s3c24xx/mci.h>
  26
  27 #include "s3cmci.h"
  28
  29 #define DRIVER_NAME "s3c-mci"
  30
  31 enum dbg_channels {
  32         dbg_err   = (1 << 0),
  33         dbg_debug = (1 << 1),
  34         dbg_info  = (1 << 2),
  35         dbg_irq   = (1 << 3),
  36         dbg_sg    = (1 << 4),
  37         dbg_dma   = (1 << 5),
  38         dbg_pio   = (1 << 6),
  39         dbg_fail  = (1 << 7),
  40         dbg_conf  = (1 << 8),
  41 };
  42
  43 static const int dbgmap_err   = dbg_fail;
  44 static const int dbgmap_info  = dbg_info | dbg_conf;
  45 static const int dbgmap_debug = dbg_err | dbg_debug;
  46
  47 #define dbg(host, channels, args...)              \
  48         do {                                      \
  49         if (dbgmap_err & channels)                \
  50                 dev_err(&host->pdev->dev, args);  \
  51         else if (dbgmap_info & channels)          \
  52                 dev_info(&host->pdev->dev, args); \
  53         else if (dbgmap_debug & channels)         \
  54                 dev_dbg(&host->pdev->dev, args);  \
  55         } while (0)
  56
  57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  58
  59 static struct s3c2410_dma_client s3cmci_dma_client = {
  60         .name           = "s3c-mci",
  61 };
  62
  63 static void finalize_request(struct s3cmci_host *host);
  64 static void s3cmci_send_request(struct mmc_host *mmc);
  65 static void s3cmci_reset(struct s3cmci_host *host);
  66
  67 #ifdef CONFIG_MMC_DEBUG
  68
  69 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  70 {
  71         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
  72         u32 datcon, datcnt, datsta, fsta, imask;
  73
  74         con     = readl(host->base + S3C2410_SDICON);
  75         pre     = readl(host->base + S3C2410_SDIPRE);
  76         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
  77         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
  78         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
  79         r0      = readl(host->base + S3C2410_SDIRSP0);
  80         r1      = readl(host->base + S3C2410_SDIRSP1);
  81         r2      = readl(host->base + S3C2410_SDIRSP2);
  82         r3      = readl(host->base + S3C2410_SDIRSP3);
  83         timer   = readl(host->base + S3C2410_SDITIMER);
  84         bsize   = readl(host->base + S3C2410_SDIBSIZE);
  85         datcon  = readl(host->base + S3C2410_SDIDCON);
  86         datcnt  = readl(host->base + S3C2410_SDIDCNT);
  87         datsta  = readl(host->base + S3C2410_SDIDSTA);
  88         fsta    = readl(host->base + S3C2410_SDIFSTA);
  89         imask   = readl(host->base + host->sdiimsk);
  90
  91         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
  92                                 prefix, con, pre, timer);
  93
  94         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  95                                 prefix, cmdcon, cmdarg, cmdsta);
  96
  97         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
  98                                " DSTA:[%08x] DCNT:[%08x]\n",
  99                                 prefix, datcon, fsta, datsta, datcnt);
 100
 101         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 102                                "   R2:[%08x]   R3:[%08x]\n",
 103                                 prefix, r0, r1, r2, r3);
 104 }
 105
 106 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 107                            int stop)
 108 {
 109         snprintf(host->dbgmsg_cmd, 300,
 110                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 111                  host->ccnt, (stop ? " (STOP)" : ""),
 112                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 113
 114         if (cmd->data) {
 115                 snprintf(host->dbgmsg_dat, 300,
 116                          "#%u bsize:%u blocks:%u bytes:%u",
 117                          host->dcnt, cmd->data->blksz,
 118                          cmd->data->blocks,
 119                          cmd->data->blocks * cmd->data->blksz);
 120         } else {
 121                 host->dbgmsg_dat[0] = '\0';
 122         }
 123 }
 124
 125 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 126                         int fail)
 127 {
 128         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 129
 130         if (!cmd)
 131                 return;
 132
 133         if (cmd->error == 0) {
 134                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 135                         host->dbgmsg_cmd, cmd->resp[0]);
 136         } else {
 137                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 138                         cmd->error, host->dbgmsg_cmd, host->status);
 139         }
 140
 141         if (!cmd->data)
 142                 return;
 143
 144         if (cmd->data->error == 0) {
 145                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 146         } else {
 147                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 148                         cmd->data->error, host->dbgmsg_dat,
 149                         readl(host->base + S3C2410_SDIDCNT));
 150         }
 151 }
 152 #else
 153 static void dbg_dumpcmd(struct s3cmci_host *host,
 154                         struct mmc_command *cmd, int fail) { }
 155
 156 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 157                            int stop) { }
 158
 159 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 160
 161 #endif /* CONFIG_MMC_DEBUG */
 162
 163 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 164 {
 165         u32 newmask;
 166
 167         newmask = readl(host->base + host->sdiimsk);
 168         newmask |= imask;
 169
 170         writel(newmask, host->base + host->sdiimsk);
 171
 172         return newmask;
 173 }
 174
 175 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 176 {
 177         u32 newmask;
 178
 179         newmask = readl(host->base + host->sdiimsk);
 180         newmask &= ~imask;
 181
 182         writel(newmask, host->base + host->sdiimsk);
 183
 184         return newmask;
 185 }
 186
 187 static inline void clear_imask(struct s3cmci_host *host)
 188 {
 189         writel(0, host->base + host->sdiimsk);
 190 }
 191
 192 static inline int get_data_buffer(struct s3cmci_host *host,
 193                                   u32 *bytes, u32 **pointer)
 194 {
 195         struct scatterlist *sg;
 196
 197         if (host->pio_active == XFER_NONE)
 198                 return -EINVAL;
 199
 200         if ((!host->mrq) || (!host->mrq->data))
 201                 return -EINVAL;
 202
 203         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 204                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 205                       host->pio_sgptr, host->mrq->data->sg_len);
 206                 return -EBUSY;
 207         }
 208         sg = &host->mrq->data->sg[host->pio_sgptr];
 209
 210         *bytes = sg->length;
 211         *pointer = sg_virt(sg);
 212
 213         host->pio_sgptr++;
 214
 215         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 216             host->pio_sgptr, host->mrq->data->sg_len);
 217
 218         return 0;
 219 }
 220
 221 static inline u32 fifo_count(struct s3cmci_host *host)
 222 {
 223         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 224
 225         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 226         return fifostat;
 227 }
 228
 229 static inline u32 fifo_free(struct s3cmci_host *host)
 230 {
 231         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 232
 233         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 234         return 63 - fifostat;
 235 }
 236
 237 static void do_pio_read(struct s3cmci_host *host)
 238 {
 239         int res;
 240         u32 fifo;
 241         u32 fifo_words;
 242         void __iomem *from_ptr;
 243
 244         /* write real prescaler to host, it might be set slow to fix */
 245         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 246
 247         from_ptr = host->base + host->sdidata;
 248
 249         while ((fifo = fifo_count(host))) {
 250                 if (!host->pio_bytes) {
 251                         res = get_data_buffer(host, &host->pio_bytes,
 252                                               &host->pio_ptr);
 253                         if (res) {
 254                                 host->pio_active = XFER_NONE;
 255                                 host->complete_what = COMPLETION_FINALIZE;
 256
 257                                 dbg(host, dbg_pio, "pio_read(): "
 258                                     "complete (no more data).\n");
 259                                 return;
 260                         }
 261
 262                         dbg(host, dbg_pio,
 263                             "pio_read(): new target: [%i]@[%p]\n",
 264                             host->pio_bytes, host->pio_ptr);
 265                 }
 266
 267                 dbg(host, dbg_pio,
 268                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 269                     fifo, host->pio_bytes,
 270                     readl(host->base + S3C2410_SDIDCNT));
 271
 272                 /* If we have reached the end of the block, we can
 273                  * read a word and get 1 to 3 bytes.  If we in the
 274                  * middle of the block, we have to read full words,
 275                  * otherwise we will write garbage, so round down to
 276                  * an even multiple of 4. */
 277                 if (fifo >= host->pio_bytes)
 278                         fifo = host->pio_bytes;
 279                 else
 280                         fifo -= fifo & 3;
 281
 282                 host->pio_bytes -= fifo;
 283                 host->pio_count += fifo;
 284
 285                 fifo_words = fifo >> 2;
 286                 while (fifo_words--)
 287                         *(host->pio_ptr++) = readl(from_ptr);
 288
 289                 if (fifo & 3) {
 290                         u32 n = fifo & 3;
 291                         u32 data = readl(from_ptr);
 292                         u8 *p = (u8 *)host->pio_ptr;
 293
 294                         while (n--) {
 295                                 *p++ = data;
 296                                 data >>= 8;
 297                         }
 298                 }
 299         }
 300
 301         if (!host->pio_bytes) {
 302                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 303                 if (res) {
 304                         dbg(host, dbg_pio,
 305                             "pio_read(): complete (no more buffers).\n");
 306                         host->pio_active = XFER_NONE;
 307                         host->complete_what = COMPLETION_FINALIZE;
 308
 309                         return;
 310                 }
 311         }
 312
 313         enable_imask(host,
 314                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 315 }
 316
 317 static void do_pio_write(struct s3cmci_host *host)
 318 {
 319         void __iomem *to_ptr;
 320         int res;
 321         u32 fifo;
 322
 323         to_ptr = host->base + host->sdidata;
 324
 325         while ((fifo = fifo_free(host))) {
 326                 if (!host->pio_bytes) {
 327                         res = get_data_buffer(host, &host->pio_bytes,
 328                                                         &host->pio_ptr);
 329                         if (res) {
 330                                 dbg(host, dbg_pio,
 331                                     "pio_write(): complete (no more data).\n");
 332                                 host->pio_active = XFER_NONE;
 333
 334                                 return;
 335                         }
 336
 337                         dbg(host, dbg_pio,
 338                             "pio_write(): new source: [%i]@[%p]\n",
 339                             host->pio_bytes, host->pio_ptr);
 340
 341                 }
 342
 343                 /* If we have reached the end of the block, we have to
 344                  * write exactly the remaining number of bytes.  If we
 345                  * in the middle of the block, we have to write full
 346                  * words, so round down to an even multiple of 4. */
 347                 if (fifo >= host->pio_bytes)
 348                         fifo = host->pio_bytes;
 349                 else
 350                         fifo -= fifo & 3;
 351
 352                 host->pio_bytes -= fifo;
 353                 host->pio_count += fifo;
 354
 355                 fifo = (fifo + 3) >> 2;
 356                 while (fifo--)
 357                         writel(*(host->pio_ptr++), to_ptr);
 358         }
 359
 360         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 361 }
 362
 363 static void pio_tasklet(unsigned long data)
 364 {
 365         struct s3cmci_host *host = (struct s3cmci_host *) data;
 366
 367
 368         disable_irq(host->irq);
 369
 370         if (host->pio_active == XFER_WRITE)
 371                 do_pio_write(host);
 372
 373         if (host->pio_active == XFER_READ)
 374                 do_pio_read(host);
 375
 376         if (host->complete_what == COMPLETION_FINALIZE) {
 377                 clear_imask(host);
 378                 if (host->pio_active != XFER_NONE) {
 379                         dbg(host, dbg_err, "unfinished %s "
 380                             "- pio_count:[%u] pio_bytes:[%u]\n",
 381                             (host->pio_active == XFER_READ) ? "read" : "write",
 382                             host->pio_count, host->pio_bytes);
 383
 384                         if (host->mrq->data)
 385                                 host->mrq->data->error = -EINVAL;
 386                 }
 387
 388                 finalize_request(host);
 389         } else
 390                 enable_irq(host->irq);
 391 }
 392
 393 /*
 394  * ISR for SDI Interface IRQ
 395  * Communication between driver and ISR works as follows:
 396  *   host->mrq                  points to current request
 397  *   host->complete_what        Indicates when the request is considered done
 398  *     COMPLETION_CMDSENT         when the command was sent
 399  *     COMPLETION_RSPFIN          when a response was received
 400  *     COMPLETION_XFERFINISH      when the data transfer is finished
 401  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 402  *   host->complete_request     is the completion-object the driver waits for
 403  *
 404  * 1) Driver sets up host->mrq and host->complete_what
 405  * 2) Driver prepares the transfer
 406  * 3) Driver enables interrupts
 407  * 4) Driver starts transfer
 408  * 5) Driver waits for host->complete_rquest
 409  * 6) ISR checks for request status (errors and success)
 410  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 411  * 7) ISR completes host->complete_request
 412  * 8) ISR disables interrupts
 413  * 9) Driver wakes up and takes care of the request
 414  *
 415  * Note: "->error"-fields are expected to be set to 0 before the request
 416  *       was issued by mmc.c - therefore they are only set, when an error
 417  *       contition comes up
 418  */
 419
 420 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 421 {
 422         struct s3cmci_host *host = dev_id;
 423         struct mmc_command *cmd;
 424         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 425         u32 mci_cclear, mci_dclear;
 426         unsigned long iflags;
 427
 428         spin_lock_irqsave(&host->complete_lock, iflags);
 429
 430         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 431         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 432         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 433         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 434         mci_imsk = readl(host->base + host->sdiimsk);
 435         mci_cclear = 0;
 436         mci_dclear = 0;
 437
 438         if ((host->complete_what == COMPLETION_NONE) ||
 439             (host->complete_what == COMPLETION_FINALIZE)) {
 440                 host->status = "nothing to complete";
 441                 clear_imask(host);
 442                 goto irq_out;
 443         }
 444
 445         if (!host->mrq) {
 446                 host->status = "no active mrq";
 447                 clear_imask(host);
 448                 goto irq_out;
 449         }
 450
 451         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 452
 453         if (!cmd) {
 454                 host->status = "no active cmd";
 455                 clear_imask(host);
 456                 goto irq_out;
 457         }
 458
 459         if (!host->dodma) {
 460                 if ((host->pio_active == XFER_WRITE) &&
 461                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 462
 463                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 464                         tasklet_schedule(&host->pio_tasklet);
 465                         host->status = "pio tx";
 466                 }
 467
 468                 if ((host->pio_active == XFER_READ) &&
 469                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 470
 471                         disable_imask(host,
 472                                       S3C2410_SDIIMSK_RXFIFOHALF |
 473                                       S3C2410_SDIIMSK_RXFIFOLAST);
 474
 475                         tasklet_schedule(&host->pio_tasklet);
 476                         host->status = "pio rx";
 477                 }
 478         }
 479
 480         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 481                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 482                 cmd->error = -ETIMEDOUT;
 483                 host->status = "error: command timeout";
 484                 goto fail_transfer;
 485         }
 486
 487         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 488                 if (host->complete_what == COMPLETION_CMDSENT) {
 489                         host->status = "ok: command sent";
 490                         goto close_transfer;
 491                 }
 492
 493                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 494         }
 495
 496         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 497                 if (cmd->flags & MMC_RSP_CRC) {
 498                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 499                                 dbg(host, dbg_irq,
 500                                     "fixup: ignore CRC fail with long rsp\n");
 501                         } else {
 502                                 /* note, we used to fail the transfer
 503                                  * here, but it seems that this is just
 504                                  * the hardware getting it wrong.
 505                                  *
 506                                  * cmd->error = -EILSEQ;
 507                                  * host->status = "error: bad command crc";
 508                                  * goto fail_transfer;
 509                                 */
 510                         }
 511                 }
 512
 513                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 514         }
 515
 516         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 517                 if (host->complete_what == COMPLETION_RSPFIN) {
 518                         host->status = "ok: command response received";
 519                         goto close_transfer;
 520                 }
 521
 522                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 523                         host->complete_what = COMPLETION_XFERFINISH;
 524
 525                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 526         }
 527
 528         /* errors handled after this point are only relevant
 529            when a data transfer is in progress */
 530
 531         if (!cmd->data)
 532                 goto clear_status_bits;
 533
 534         /* Check for FIFO failure */
 535         if (host->is2440) {
 536                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 537                         dbg(host, dbg_err, "FIFO failure\n");
 538                         host->mrq->data->error = -EILSEQ;
 539                         host->status = "error: 2440 fifo failure";
 540                         goto fail_transfer;
 541                 }
 542         } else {
 543                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 544                         dbg(host, dbg_err, "FIFO failure\n");
 545                         cmd->data->error = -EILSEQ;
 546                         host->status = "error:  fifo failure";
 547                         goto fail_transfer;
 548                 }
 549         }
 550
 551         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 552                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 553                 cmd->data->error = -EILSEQ;
 554                 host->status = "error: bad data crc (outgoing)";
 555                 goto fail_transfer;
 556         }
 557
 558         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 559                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 560                 cmd->data->error = -EILSEQ;
 561                 host->status = "error: bad data crc (incoming)";
 562                 goto fail_transfer;
 563         }
 564
 565         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 566                 dbg(host, dbg_err, "data timeout\n");
 567                 cmd->data->error = -ETIMEDOUT;
 568                 host->status = "error: data timeout";
 569                 goto fail_transfer;
 570         }
 571
 572         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 573                 if (host->complete_what == COMPLETION_XFERFINISH) {
 574                         host->status = "ok: data transfer completed";
 575                         goto close_transfer;
 576                 }
 577
 578                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 579                         host->complete_what = COMPLETION_RSPFIN;
 580
 581                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 582         }
 583
 584 clear_status_bits:
 585         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 586         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 587
 588         goto irq_out;
 589
 590 fail_transfer:
 591         host->pio_active = XFER_NONE;
 592
 593 close_transfer:
 594         host->complete_what = COMPLETION_FINALIZE;
 595
 596         clear_imask(host);
 597         tasklet_schedule(&host->pio_tasklet);
 598
 599         goto irq_out;
 600
 601 irq_out:
 602         dbg(host, dbg_irq,
 603             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 604             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 605
 606         spin_unlock_irqrestore(&host->complete_lock, iflags);
 607         return IRQ_HANDLED;
 608
 609 }
 610
 611 /*
 612  * ISR for the CardDetect Pin
 613 */
 614
 615 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 616 {
 617         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 618
 619         dbg(host, dbg_irq, "card detect\n");
 620
 621         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 622
 623         return IRQ_HANDLED;
 624 }
 625
 626 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
 627                                      void *buf_id, int size,
 628                                      enum s3c2410_dma_buffresult result)
 629 {
 630         struct s3cmci_host *host = buf_id;
 631         unsigned long iflags;
 632         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
 633
 634         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 635         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 636         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 637         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 638
 639         BUG_ON(!host->mrq);
 640         BUG_ON(!host->mrq->data);
 641         BUG_ON(!host->dmatogo);
 642
 643         spin_lock_irqsave(&host->complete_lock, iflags);
 644
 645         if (result != S3C2410_RES_OK) {
 646                 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
 647                         "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
 648                         mci_csta, mci_dsta, mci_fsta,
 649                         mci_dcnt, result, host->dmatogo);
 650
 651                 goto fail_request;
 652         }
 653
 654         host->dmatogo--;
 655         if (host->dmatogo) {
 656                 dbg(host, dbg_dma, "DMA DONE  Size:%i DSTA:[%08x] "
 657                         "DCNT:[%08x] toGo:%u\n",
 658                         size, mci_dsta, mci_dcnt, host->dmatogo);
 659
 660                 goto out;
 661         }
 662
 663         dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
 664                 size, mci_dsta, mci_dcnt);
 665
 666         host->complete_what = COMPLETION_FINALIZE;
 667
 668 out:
 669         tasklet_schedule(&host->pio_tasklet);
 670         spin_unlock_irqrestore(&host->complete_lock, iflags);
 671         return;
 672
 673 fail_request:
 674         host->mrq->data->error = -EINVAL;
 675         host->complete_what = COMPLETION_FINALIZE;
 676         writel(0, host->base + host->sdiimsk);
 677         goto out;
 678
 679 }
 680
 681 static void finalize_request(struct s3cmci_host *host)
 682 {
 683         struct mmc_request *mrq = host->mrq;
 684         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 685         int debug_as_failure = 0;
 686
 687         if (host->complete_what != COMPLETION_FINALIZE)
 688                 return;
 689
 690         if (!mrq)
 691                 return;
 692
 693         if (cmd->data && (cmd->error == 0) &&
 694             (cmd->data->error == 0)) {
 695                 if (host->dodma && (!host->dma_complete)) {
 696                         dbg(host, dbg_dma, "DMA Missing!\n");
 697                         return;
 698                 }
 699         }
 700
 701         /* Read response from controller. */
 702         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 703         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 704         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 705         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 706
 707         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 708
 709         if (cmd->error)
 710                 debug_as_failure = 1;
 711
 712         if (cmd->data && cmd->data->error)
 713                 debug_as_failure = 1;
 714
 715         dbg_dumpcmd(host, cmd, debug_as_failure);
 716
 717         /* Cleanup controller */
 718         writel(0, host->base + S3C2410_SDICMDARG);
 719         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 720         writel(0, host->base + S3C2410_SDICMDCON);
 721         writel(0, host->base + host->sdiimsk);
 722
 723         if (cmd->data && cmd->error)
 724                 cmd->data->error = cmd->error;
 725
 726         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 727                 host->cmd_is_stop = 1;
 728                 s3cmci_send_request(host->mmc);
 729                 return;
 730         }
 731
 732         /* If we have no data transfer we are finished here */
 733         if (!mrq->data)
 734                 goto request_done;
 735
 736         /* Calulate the amout of bytes transfer if there was no error */
 737         if (mrq->data->error == 0) {
 738                 mrq->data->bytes_xfered =
 739                         (mrq->data->blocks * mrq->data->blksz);
 740         } else {
 741                 mrq->data->bytes_xfered = 0;
 742         }
 743
 744         /* If we had an error while transfering data we flush the
 745          * DMA channel and the fifo to clear out any garbage. */
 746         if (mrq->data->error != 0) {
 747                 if (host->dodma)
 748                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 749
 750                 if (host->is2440) {
 751                         /* Clear failure register and reset fifo. */
 752                         writel(S3C2440_SDIFSTA_FIFORESET |
 753                                S3C2440_SDIFSTA_FIFOFAIL,
 754                                host->base + S3C2410_SDIFSTA);
 755                 } else {
 756                         u32 mci_con;
 757
 758                         /* reset fifo */
 759                         mci_con = readl(host->base + S3C2410_SDICON);
 760                         mci_con |= S3C2410_SDICON_FIFORESET;
 761
 762                         writel(mci_con, host->base + S3C2410_SDICON);
 763                 }
 764         }
 765
 766 request_done:
 767         host->complete_what = COMPLETION_NONE;
 768         host->mrq = NULL;
 769         mmc_request_done(host->mmc, mrq);
 770 }
 771
 772 static void s3cmci_dma_setup(struct s3cmci_host *host,
 773                              enum s3c2410_dmasrc source)
 774 {
 775         static enum s3c2410_dmasrc last_source = -1;
 776         static int setup_ok;
 777
 778         if (last_source == source)
 779                 return;
 780
 781         last_source = source;
 782
 783         s3c2410_dma_devconfig(host->dma, source, 3,
 784                               host->mem->start + host->sdidata);
 785
 786         if (!setup_ok) {
 787                 s3c2410_dma_config(host->dma, 4,
 788                         (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI));
 789                 s3c2410_dma_set_buffdone_fn(host->dma,
 790                                             s3cmci_dma_done_callback);
 791                 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
 792                 setup_ok = 1;
 793         }
 794 }
 795
 796 static void s3cmci_send_command(struct s3cmci_host *host,
 797                                         struct mmc_command *cmd)
 798 {
 799         u32 ccon, imsk;
 800
 801         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 802                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 803                 S3C2410_SDIIMSK_RESPONSECRC;
 804
 805         enable_imask(host, imsk);
 806
 807         if (cmd->data)
 808                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 809         else if (cmd->flags & MMC_RSP_PRESENT)
 810                 host->complete_what = COMPLETION_RSPFIN;
 811         else
 812                 host->complete_what = COMPLETION_CMDSENT;
 813
 814         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 815
 816         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 817         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 818
 819         if (cmd->flags & MMC_RSP_PRESENT)
 820                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 821
 822         if (cmd->flags & MMC_RSP_136)
 823                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 824
 825         writel(ccon, host->base + S3C2410_SDICMDCON);
 826 }
 827
 828 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 829 {
 830         u32 dcon, imsk, stoptries = 3;
 831
 832         /* write DCON register */
 833
 834         if (!data) {
 835                 writel(0, host->base + S3C2410_SDIDCON);
 836                 return 0;
 837         }
 838
 839         if ((data->blksz & 3) != 0) {
 840                 /* We cannot deal with unaligned blocks with more than
 841                  * one block being transfered. */
 842
 843                 if (data->blocks > 1) {
 844                         pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
 845                         return -EINVAL;
 846                 }
 847         }
 848
 849         while (readl(host->base + S3C2410_SDIDSTA) &
 850                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 851
 852                 dbg(host, dbg_err,
 853                     "mci_setup_data() transfer stillin progress.\n");
 854
 855                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 856                 s3cmci_reset(host);
 857
 858                 if ((stoptries--) == 0) {
 859                         dbg_dumpregs(host, "DRF");
 860                         return -EINVAL;
 861                 }
 862         }
 863
 864         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 865
 866         if (host->dodma)
 867                 dcon |= S3C2410_SDIDCON_DMAEN;
 868
 869         if (host->bus_width == MMC_BUS_WIDTH_4)
 870                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 871
 872         if (!(data->flags & MMC_DATA_STREAM))
 873                 dcon |= S3C2410_SDIDCON_BLOCKMODE;
 874
 875         if (data->flags & MMC_DATA_WRITE) {
 876                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 877                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
 878         }
 879
 880         if (data->flags & MMC_DATA_READ) {
 881                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
 882                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
 883         }
 884
 885         if (host->is2440) {
 886                 dcon |= S3C2440_SDIDCON_DS_WORD;
 887                 dcon |= S3C2440_SDIDCON_DATSTART;
 888         }
 889
 890         writel(dcon, host->base + S3C2410_SDIDCON);
 891
 892         /* write BSIZE register */
 893
 894         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
 895
 896         /* add to IMASK register */
 897         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
 898                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
 899
 900         enable_imask(host, imsk);
 901
 902         /* write TIMER register */
 903
 904         if (host->is2440) {
 905                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
 906         } else {
 907                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
 908
 909                 /* FIX: set slow clock to prevent timeouts on read */
 910                 if (data->flags & MMC_DATA_READ)
 911                         writel(0xFF, host->base + S3C2410_SDIPRE);
 912         }
 913
 914         return 0;
 915 }
 916
 917 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
 918
 919 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
 920 {
 921         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 922
 923         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 924
 925         host->pio_sgptr = 0;
 926         host->pio_bytes = 0;
 927         host->pio_count = 0;
 928         host->pio_active = rw ? XFER_WRITE : XFER_READ;
 929
 930         if (rw) {
 931                 do_pio_write(host);
 932                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 933         } else {
 934                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
 935                              | S3C2410_SDIIMSK_RXFIFOLAST);
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
 942 {
 943         int dma_len, i;
 944         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 945
 946         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 947
 948         s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
 949         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 950
 951         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 952                              (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 953
 954         if (dma_len == 0)
 955                 return -ENOMEM;
 956
 957         host->dma_complete = 0;
 958         host->dmatogo = dma_len;
 959
 960         for (i = 0; i < dma_len; i++) {
 961                 int res;
 962
 963                 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
 964                         sg_dma_address(&data->sg[i]),
 965                         sg_dma_len(&data->sg[i]));
 966
 967                 res = s3c2410_dma_enqueue(host->dma, (void *) host,
 968                                           sg_dma_address(&data->sg[i]),
 969                                           sg_dma_len(&data->sg[i]));
 970
 971                 if (res) {
 972                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 973                         return -EBUSY;
 974                 }
 975         }
 976
 977         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
 978
 979         return 0;
 980 }
 981
 982 static void s3cmci_send_request(struct mmc_host *mmc)
 983 {
 984         struct s3cmci_host *host = mmc_priv(mmc);
 985         struct mmc_request *mrq = host->mrq;
 986         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 987
 988         host->ccnt++;
 989         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
 990
 991         /* Clear command, data and fifo status registers
 992            Fifo clear only necessary on 2440, but doesn't hurt on 2410
 993         */
 994         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
 995         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
 996         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
 997
 998         if (cmd->data) {
 999                 int res = s3cmci_setup_data(host, cmd->data);
1000
1001                 host->dcnt++;
1002
1003                 if (res) {
1004                         dbg(host, dbg_err, "setup data error %d\n", res);
1005                         cmd->error = res;
1006                         cmd->data->error = res;
1007
1008                         mmc_request_done(mmc, mrq);
1009                         return;
1010                 }
1011
1012                 if (host->dodma)
1013                         res = s3cmci_prepare_dma(host, cmd->data);
1014                 else
1015                         res = s3cmci_prepare_pio(host, cmd->data);
1016
1017                 if (res) {
1018                         dbg(host, dbg_err, "data prepare error %d\n", res);
1019                         cmd->error = res;
1020                         cmd->data->error = res;
1021
1022                         mmc_request_done(mmc, mrq);
1023                         return;
1024                 }
1025         }
1026
1027         /* Send command */
1028         s3cmci_send_command(host, cmd);
1029
1030         /* Enable Interrupt */
1031         enable_irq(host->irq);
1032 }
1033
1034 static int s3cmci_card_present(struct mmc_host *mmc)
1035 {
1036         struct s3cmci_host *host = mmc_priv(mmc);
1037         struct s3c24xx_mci_pdata *pdata = host->pdata;
1038         int ret;
1039
1040         if (pdata->gpio_detect == 0)
1041                 return -ENOSYS;
1042
1043         ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1;
1044         return ret ^ pdata->detect_invert;
1045 }
1046
1047 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1048 {
1049         struct s3cmci_host *host = mmc_priv(mmc);
1050
1051         host->status = "mmc request";
1052         host->cmd_is_stop = 0;
1053         host->mrq = mrq;
1054
1055         if (s3cmci_card_present(mmc) == 0) {
1056                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1057                 host->mrq->cmd->error = -ENOMEDIUM;
1058                 mmc_request_done(mmc, mrq);
1059         } else
1060                 s3cmci_send_request(mmc);
1061 }
1062
1063 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1064 {
1065         u32 mci_psc;
1066
1067         /* Set clock */
1068         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1069                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1070
1071                 if (host->real_rate <= ios->clock)
1072                         break;
1073         }
1074
1075         if (mci_psc > 255)
1076                 mci_psc = 255;
1077
1078         host->prescaler = mci_psc;
1079         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1080
1081         /* If requested clock is 0, real_rate will be 0, too */
1082         if (ios->clock == 0)
1083                 host->real_rate = 0;
1084 }
1085
1086 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1087 {
1088         struct s3cmci_host *host = mmc_priv(mmc);
1089         u32 mci_con;
1090
1091         /* Set the power state */
1092
1093         mci_con = readl(host->base + S3C2410_SDICON);
1094
1095         switch (ios->power_mode) {
1096         case MMC_POWER_ON:
1097         case MMC_POWER_UP:
1098                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
1099                 s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
1100                 s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
1101                 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
1102                 s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
1103                 s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
1104
1105                 if (host->pdata->set_power)
1106                         host->pdata->set_power(ios->power_mode, ios->vdd);
1107
1108                 if (!host->is2440)
1109                         mci_con |= S3C2410_SDICON_FIFORESET;
1110
1111                 break;
1112
1113         case MMC_POWER_OFF:
1114         default:
1115                 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1116                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP);
1117
1118                 if (host->is2440)
1119                         mci_con |= S3C2440_SDICON_SDRESET;
1120
1121                 if (host->pdata->set_power)
1122                         host->pdata->set_power(ios->power_mode, ios->vdd);
1123
1124                 break;
1125         }
1126
1127         s3cmci_set_clk(host, ios);
1128
1129         /* Set CLOCK_ENABLE */
1130         if (ios->clock)
1131                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1132         else
1133                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1134
1135         writel(mci_con, host->base + S3C2410_SDICON);
1136
1137         if ((ios->power_mode == MMC_POWER_ON) ||
1138             (ios->power_mode == MMC_POWER_UP)) {
1139                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1140                         host->real_rate/1000, ios->clock/1000);
1141         } else {
1142                 dbg(host, dbg_conf, "powered down.\n");
1143         }
1144
1145         host->bus_width = ios->bus_width;
1146 }
1147
1148 static void s3cmci_reset(struct s3cmci_host *host)
1149 {
1150         u32 con = readl(host->base + S3C2410_SDICON);
1151
1152         con |= S3C2440_SDICON_SDRESET;
1153         writel(con, host->base + S3C2410_SDICON);
1154 }
1155
1156 static int s3cmci_get_ro(struct mmc_host *mmc)
1157 {
1158         struct s3cmci_host *host = mmc_priv(mmc);
1159         struct s3c24xx_mci_pdata *pdata = host->pdata;
1160         int ret;
1161
1162         if (pdata->gpio_wprotect == 0)
1163                 return 0;
1164
1165         ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
1166
1167         if (pdata->wprotect_invert)
1168                 ret = !ret;
1169
1170         return ret;
1171 }
1172
1173 static struct mmc_host_ops s3cmci_ops = {
1174         .request        = s3cmci_request,
1175         .set_ios        = s3cmci_set_ios,
1176         .get_ro         = s3cmci_get_ro,
1177         .get_cd         = s3cmci_card_present,
1178 };
1179
1180 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1181         /* This is currently here to avoid a number of if (host->pdata)
1182          * checks. Any zero fields to ensure reaonable defaults are picked. */
1183 };
1184
1185 #ifdef CONFIG_CPU_FREQ
1186
1187 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1188                                      unsigned long val, void *data)
1189 {
1190         struct s3cmci_host *host;
1191         struct mmc_host *mmc;
1192         unsigned long newclk;
1193         unsigned long flags;
1194
1195         host = container_of(nb, struct s3cmci_host, freq_transition);
1196         newclk = clk_get_rate(host->clk);
1197         mmc = host->mmc;
1198
1199         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1200             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1201                 spin_lock_irqsave(&mmc->lock, flags);
1202
1203                 host->clk_rate = newclk;
1204
1205                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1206                     mmc->ios.clock != 0)
1207                         s3cmci_set_clk(host, &mmc->ios);
1208
1209                 spin_unlock_irqrestore(&mmc->lock, flags);
1210         }
1211
1212         return 0;
1213 }
1214
1215 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1216 {
1217         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1218
1219         return cpufreq_register_notifier(&host->freq_transition,
1220                                          CPUFREQ_TRANSITION_NOTIFIER);
1221 }
1222
1223 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1224 {
1225         cpufreq_unregister_notifier(&host->freq_transition,
1226                                     CPUFREQ_TRANSITION_NOTIFIER);
1227 }
1228
1229 #else
1230 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1231 {
1232         return 0;
1233 }
1234
1235 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1236 {
1237 }
1238 #endif
1239
1240 static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
1241 {
1242         struct s3cmci_host *host;
1243         struct mmc_host *mmc;
1244         int ret;
1245
1246         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1247         if (!mmc) {
1248                 ret = -ENOMEM;
1249                 goto probe_out;
1250         }
1251
1252         host = mmc_priv(mmc);
1253         host->mmc       = mmc;
1254         host->pdev      = pdev;
1255         host->is2440    = is2440;
1256
1257         host->pdata = pdev->dev.platform_data;
1258         if (!host->pdata) {
1259                 pdev->dev.platform_data = &s3cmci_def_pdata;
1260                 host->pdata = &s3cmci_def_pdata;
1261         }
1262
1263         spin_lock_init(&host->complete_lock);
1264         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1265
1266         if (is2440) {
1267                 host->sdiimsk   = S3C2440_SDIIMSK;
1268                 host->sdidata   = S3C2440_SDIDATA;
1269                 host->clk_div   = 1;
1270         } else {
1271                 host->sdiimsk   = S3C2410_SDIIMSK;
1272                 host->sdidata   = S3C2410_SDIDATA;
1273                 host->clk_div   = 2;
1274         }
1275
1276         host->dodma             = 0;
1277         host->complete_what     = COMPLETION_NONE;
1278         host->pio_active        = XFER_NONE;
1279
1280         host->dma               = S3CMCI_DMA;
1281
1282         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1283         if (!host->mem) {
1284                 dev_err(&pdev->dev,
1285                         "failed to get io memory region resouce.\n");
1286
1287                 ret = -ENOENT;
1288                 goto probe_free_host;
1289         }
1290
1291         host->mem = request_mem_region(host->mem->start,
1292                                        RESSIZE(host->mem), pdev->name);
1293
1294         if (!host->mem) {
1295                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1296                 ret = -ENOENT;
1297                 goto probe_free_host;
1298         }
1299
1300         host->base = ioremap(host->mem->start, RESSIZE(host->mem));
1301         if (!host->base) {
1302                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1303                 ret = -EINVAL;
1304                 goto probe_free_mem_region;
1305         }
1306
1307         host->irq = platform_get_irq(pdev, 0);
1308         if (host->irq == 0) {
1309                 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1310                 ret = -EINVAL;
1311                 goto probe_iounmap;
1312         }
1313
1314         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1315                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1316                 ret = -ENOENT;
1317                 goto probe_iounmap;
1318         }
1319
1320         /* We get spurious interrupts even when we have set the IMSK
1321          * register to ignore everything, so use disable_irq() to make
1322          * ensure we don't lock the system with un-serviceable requests. */
1323
1324         disable_irq(host->irq);
1325
1326         host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
1327
1328         if (host->irq_cd >= 0) {
1329                 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1330                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1331                                 DRIVER_NAME, host)) {
1332                         dev_err(&pdev->dev, "can't get card detect irq.\n");
1333                         ret = -ENOENT;
1334                         goto probe_free_irq;
1335                 }
1336         } else {
1337                 dev_warn(&pdev->dev, "host detect has no irq available\n");
1338                 s3c2410_gpio_cfgpin(host->pdata->gpio_detect,
1339                                     S3C2410_GPIO_INPUT);
1340         }
1341
1342         if (host->pdata->gpio_wprotect)
1343                 s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect,
1344                                     S3C2410_GPIO_INPUT);
1345
1346         if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
1347                 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1348                 ret = -EBUSY;
1349                 goto probe_free_irq_cd;
1350         }
1351
1352         host->clk = clk_get(&pdev->dev, "sdi");
1353         if (IS_ERR(host->clk)) {
1354                 dev_err(&pdev->dev, "failed to find clock source.\n");
1355                 ret = PTR_ERR(host->clk);
1356                 host->clk = NULL;
1357                 goto probe_free_host;
1358         }
1359
1360         ret = clk_enable(host->clk);
1361         if (ret) {
1362                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1363                 goto clk_free;
1364         }
1365
1366         host->clk_rate = clk_get_rate(host->clk);
1367
1368         mmc->ops        = &s3cmci_ops;
1369         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1370         mmc->caps       = MMC_CAP_4_BIT_DATA;
1371         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1372         mmc->f_max      = host->clk_rate / host->clk_div;
1373
1374         if (host->pdata->ocr_avail)
1375                 mmc->ocr_avail = host->pdata->ocr_avail;
1376
1377         mmc->max_blk_count      = 4095;
1378         mmc->max_blk_size       = 4095;
1379         mmc->max_req_size       = 4095 * 512;
1380         mmc->max_seg_size       = mmc->max_req_size;
1381
1382         mmc->max_phys_segs      = 128;
1383         mmc->max_hw_segs        = 128;
1384
1385         dbg(host, dbg_debug,
1386             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1387             (host->is2440?"2440":""),
1388             host->base, host->irq, host->irq_cd, host->dma);
1389
1390         ret = s3cmci_cpufreq_register(host);
1391         if (ret) {
1392                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1393                 goto free_dmabuf;
1394         }
1395
1396         ret = mmc_add_host(mmc);
1397         if (ret) {
1398                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1399                 goto free_cpufreq;
1400         }
1401
1402         platform_set_drvdata(pdev, mmc);
1403         dev_info(&pdev->dev, "initialisation done.\n");
1404
1405         return 0;
1406
1407  free_cpufreq:
1408         s3cmci_cpufreq_deregister(host);
1409
1410  free_dmabuf:
1411         clk_disable(host->clk);
1412
1413  clk_free:
1414         clk_put(host->clk);
1415
1416  probe_free_irq_cd:
1417         if (host->irq_cd >= 0)
1418                 free_irq(host->irq_cd, host);
1419
1420  probe_free_irq:
1421         free_irq(host->irq, host);
1422
1423  probe_iounmap:
1424         iounmap(host->base);
1425
1426  probe_free_mem_region:
1427         release_mem_region(host->mem->start, RESSIZE(host->mem));
1428
1429  probe_free_host:
1430         mmc_free_host(mmc);
1431  probe_out:
1432         return ret;
1433 }
1434
1435 static void s3cmci_shutdown(struct platform_device *pdev)
1436 {
1437         struct mmc_host *mmc = platform_get_drvdata(pdev);
1438         struct s3cmci_host *host = mmc_priv(mmc);
1439
1440         if (host->irq_cd >= 0)
1441                 free_irq(host->irq_cd, host);
1442
1443         s3cmci_cpufreq_deregister(host);
1444         mmc_remove_host(mmc);
1445         clk_disable(host->clk);
1446 }
1447
1448 static int __devexit s3cmci_remove(struct platform_device *pdev)
1449 {
1450         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1451         struct s3cmci_host      *host = mmc_priv(mmc);
1452
1453         s3cmci_shutdown(pdev);
1454
1455         clk_put(host->clk);
1456
1457         tasklet_disable(&host->pio_tasklet);
1458         s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
1459
1460         free_irq(host->irq, host);
1461
1462         iounmap(host->base);
1463         release_mem_region(host->mem->start, RESSIZE(host->mem));
1464
1465         mmc_free_host(mmc);
1466         return 0;
1467 }
1468
1469 static int __devinit s3cmci_2410_probe(struct platform_device *dev)
1470 {
1471         return s3cmci_probe(dev, 0);
1472 }
1473
1474 static int __devinit s3cmci_2412_probe(struct platform_device *dev)
1475 {
1476         return s3cmci_probe(dev, 1);
1477 }
1478
1479 static int __devinit s3cmci_2440_probe(struct platform_device *dev)
1480 {
1481         return s3cmci_probe(dev, 1);
1482 }
1483
1484 #ifdef CONFIG_PM
1485
1486 static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
1487 {
1488         struct mmc_host *mmc = platform_get_drvdata(dev);
1489
1490         return  mmc_suspend_host(mmc, state);
1491 }
1492
1493 static int s3cmci_resume(struct platform_device *dev)
1494 {
1495         struct mmc_host *mmc = platform_get_drvdata(dev);
1496
1497         return mmc_resume_host(mmc);
1498 }
1499
1500 #else /* CONFIG_PM */
1501 #define s3cmci_suspend NULL
1502 #define s3cmci_resume NULL
1503 #endif /* CONFIG_PM */
1504
1505
1506 static struct platform_driver s3cmci_2410_driver = {
1507         .driver.name    = "s3c2410-sdi",
1508         .driver.owner   = THIS_MODULE,
1509         .probe          = s3cmci_2410_probe,
1510         .remove         = __devexit_p(s3cmci_remove),
1511         .shutdown       = s3cmci_shutdown,
1512         .suspend        = s3cmci_suspend,
1513         .resume         = s3cmci_resume,
1514 };
1515
1516 static struct platform_driver s3cmci_2412_driver = {
1517         .driver.name    = "s3c2412-sdi",
1518         .driver.owner   = THIS_MODULE,
1519         .probe          = s3cmci_2412_probe,
1520         .remove         = __devexit_p(s3cmci_remove),
1521         .shutdown       = s3cmci_shutdown,
1522         .suspend        = s3cmci_suspend,
1523         .resume         = s3cmci_resume,
1524 };
1525
1526 static struct platform_driver s3cmci_2440_driver = {
1527         .driver.name    = "s3c2440-sdi",
1528         .driver.owner   = THIS_MODULE,
1529         .probe          = s3cmci_2440_probe,
1530         .remove         = __devexit_p(s3cmci_remove),
1531         .shutdown       = s3cmci_shutdown,
1532         .suspend        = s3cmci_suspend,
1533         .resume         = s3cmci_resume,
1534 };
1535
1536
1537 static int __init s3cmci_init(void)
1538 {
1539         platform_driver_register(&s3cmci_2410_driver);
1540         platform_driver_register(&s3cmci_2412_driver);
1541         platform_driver_register(&s3cmci_2440_driver);
1542         return 0;
1543 }
1544
1545 static void __exit s3cmci_exit(void)
1546 {
1547         platform_driver_unregister(&s3cmci_2410_driver);
1548         platform_driver_unregister(&s3cmci_2412_driver);
1549         platform_driver_unregister(&s3cmci_2440_driver);
1550 }
1551
1552 module_init(s3cmci_init);
1553 module_exit(s3cmci_exit);
1554
1555 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1556 MODULE_LICENSE("GPL v2");
1557 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>");
1558 MODULE_ALIAS("platform:s3c2410-sdi");
1559 MODULE_ALIAS("platform:s3c2412-sdi");
1560 MODULE_ALIAS("platform:s3c2440-sdi");