Merge branch 'devel' into next
[linux-2.6] / arch / powerpc / boot / dts / mpc8315erdb.dts
1 /*
2  * MPC8315E RDB Device Tree Source
3  *
4  * Copyright 2007 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         compatible = "fsl,mpc8315erdb";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 ethernet0 = &enet0;
21                 ethernet1 = &enet1;
22                 serial0 = &serial0;
23                 serial1 = &serial1;
24                 pci0 = &pci0;
25         };
26
27         cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
30
31                 PowerPC,8315@0 {
32                         device_type = "cpu";
33                         reg = <0x0>;
34                         d-cache-line-size = <32>;
35                         i-cache-line-size = <32>;
36                         d-cache-size = <16384>;
37                         i-cache-size = <16384>;
38                         timebase-frequency = <0>;       // from bootloader
39                         bus-frequency = <0>;            // from bootloader
40                         clock-frequency = <0>;          // from bootloader
41                 };
42         };
43
44         memory {
45                 device_type = "memory";
46                 reg = <0x00000000 0x08000000>;  // 128MB at 0
47         };
48
49         localbus@e0005000 {
50                 #address-cells = <2>;
51                 #size-cells = <1>;
52                 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53                 reg = <0xe0005000 0x1000>;
54                 interrupts = <77 0x8>;
55                 interrupt-parent = <&ipic>;
56
57                 // CS0 and CS1 are swapped when
58                 // booting from nand, but the
59                 // addresses are the same.
60                 ranges = <0x0 0x0 0xfe000000 0x00800000
61                           0x1 0x0 0xe0600000 0x00002000
62                           0x2 0x0 0xf0000000 0x00020000
63                           0x3 0x0 0xfa000000 0x00008000>;
64
65                 flash@0,0 {
66                         #address-cells = <1>;
67                         #size-cells = <1>;
68                         compatible = "cfi-flash";
69                         reg = <0x0 0x0 0x800000>;
70                         bank-width = <2>;
71                         device-width = <1>;
72                 };
73
74                 nand@1,0 {
75                         #address-cells = <1>;
76                         #size-cells = <1>;
77                         compatible = "fsl,mpc8315-fcm-nand",
78                                      "fsl,elbc-fcm-nand";
79                         reg = <0x1 0x0 0x2000>;
80
81                         u-boot@0 {
82                                 reg = <0x0 0x100000>;
83                                 read-only;
84                         };
85
86                         kernel@100000 {
87                                 reg = <0x100000 0x300000>;
88                         };
89                         fs@400000 {
90                                 reg = <0x400000 0x1c00000>;
91                         };
92                 };
93         };
94
95         immr@e0000000 {
96                 #address-cells = <1>;
97                 #size-cells = <1>;
98                 device_type = "soc";
99                 compatible = "fsl,mpc8315-immr", "simple-bus";
100                 ranges = <0 0xe0000000 0x00100000>;
101                 reg = <0xe0000000 0x00000200>;
102                 bus-frequency = <0>;
103
104                 wdt@200 {
105                         device_type = "watchdog";
106                         compatible = "mpc83xx_wdt";
107                         reg = <0x200 0x100>;
108                 };
109
110                 i2c@3000 {
111                         #address-cells = <1>;
112                         #size-cells = <0>;
113                         cell-index = <0>;
114                         compatible = "fsl-i2c";
115                         reg = <0x3000 0x100>;
116                         interrupts = <14 0x8>;
117                         interrupt-parent = <&ipic>;
118                         dfsrr;
119                         rtc@68 {
120                                 compatible = "dallas,ds1339";
121                                 reg = <0x68>;
122                         };
123
124                         mcu_pio: mcu@a {
125                                 #gpio-cells = <2>;
126                                 compatible = "fsl,mc9s08qg8-mpc8315erdb",
127                                              "fsl,mcu-mpc8349emitx";
128                                 reg = <0x0a>;
129                                 gpio-controller;
130                         };
131                 };
132
133                 spi@7000 {
134                         cell-index = <0>;
135                         compatible = "fsl,spi";
136                         reg = <0x7000 0x1000>;
137                         interrupts = <16 0x8>;
138                         interrupt-parent = <&ipic>;
139                         mode = "cpu";
140                 };
141
142                 dma@82a8 {
143                         #address-cells = <1>;
144                         #size-cells = <1>;
145                         compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
146                         reg = <0x82a8 4>;
147                         ranges = <0 0x8100 0x1a8>;
148                         interrupt-parent = <&ipic>;
149                         interrupts = <71 8>;
150                         cell-index = <0>;
151                         dma-channel@0 {
152                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
153                                 reg = <0 0x80>;
154                                 cell-index = <0>;
155                                 interrupt-parent = <&ipic>;
156                                 interrupts = <71 8>;
157                         };
158                         dma-channel@80 {
159                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
160                                 reg = <0x80 0x80>;
161                                 cell-index = <1>;
162                                 interrupt-parent = <&ipic>;
163                                 interrupts = <71 8>;
164                         };
165                         dma-channel@100 {
166                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
167                                 reg = <0x100 0x80>;
168                                 cell-index = <2>;
169                                 interrupt-parent = <&ipic>;
170                                 interrupts = <71 8>;
171                         };
172                         dma-channel@180 {
173                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
174                                 reg = <0x180 0x28>;
175                                 cell-index = <3>;
176                                 interrupt-parent = <&ipic>;
177                                 interrupts = <71 8>;
178                         };
179                 };
180
181                 usb@23000 {
182                         compatible = "fsl-usb2-dr";
183                         reg = <0x23000 0x1000>;
184                         #address-cells = <1>;
185                         #size-cells = <0>;
186                         interrupt-parent = <&ipic>;
187                         interrupts = <38 0x8>;
188                         phy_type = "utmi";
189                 };
190
191                 mdio@24520 {
192                         #address-cells = <1>;
193                         #size-cells = <0>;
194                         compatible = "fsl,gianfar-mdio";
195                         reg = <0x24520 0x20>;
196                         phy0: ethernet-phy@0 {
197                                 interrupt-parent = <&ipic>;
198                                 interrupts = <20 0x8>;
199                                 reg = <0x0>;
200                                 device_type = "ethernet-phy";
201                         };
202                         phy1: ethernet-phy@1 {
203                                 interrupt-parent = <&ipic>;
204                                 interrupts = <19 0x8>;
205                                 reg = <0x1>;
206                                 device_type = "ethernet-phy";
207                         };
208                         tbi0: tbi-phy@11 {
209                                 reg = <0x11>;
210                                 device_type = "tbi-phy";
211                         };
212                 };
213
214                 mdio@25520 {
215                         #address-cells = <1>;
216                         #size-cells = <0>;
217                         compatible = "fsl,gianfar-tbi";
218                         reg = <0x25520 0x20>;
219
220                         tbi1: tbi-phy@11 {
221                                 reg = <0x11>;
222                                 device_type = "tbi-phy";
223                         };
224                 };
225
226
227                 enet0: ethernet@24000 {
228                         cell-index = <0>;
229                         device_type = "network";
230                         model = "eTSEC";
231                         compatible = "gianfar";
232                         reg = <0x24000 0x1000>;
233                         local-mac-address = [ 00 00 00 00 00 00 ];
234                         interrupts = <32 0x8 33 0x8 34 0x8>;
235                         interrupt-parent = <&ipic>;
236                         tbi-handle = <&tbi0>;
237                         phy-handle = < &phy0 >;
238                 };
239
240                 enet1: ethernet@25000 {
241                         cell-index = <1>;
242                         device_type = "network";
243                         model = "eTSEC";
244                         compatible = "gianfar";
245                         reg = <0x25000 0x1000>;
246                         local-mac-address = [ 00 00 00 00 00 00 ];
247                         interrupts = <35 0x8 36 0x8 37 0x8>;
248                         interrupt-parent = <&ipic>;
249                         tbi-handle = <&tbi1>;
250                         phy-handle = < &phy1 >;
251                 };
252
253                 serial0: serial@4500 {
254                         cell-index = <0>;
255                         device_type = "serial";
256                         compatible = "ns16550";
257                         reg = <0x4500 0x100>;
258                         clock-frequency = <0>;
259                         interrupts = <9 0x8>;
260                         interrupt-parent = <&ipic>;
261                 };
262
263                 serial1: serial@4600 {
264                         cell-index = <1>;
265                         device_type = "serial";
266                         compatible = "ns16550";
267                         reg = <0x4600 0x100>;
268                         clock-frequency = <0>;
269                         interrupts = <10 0x8>;
270                         interrupt-parent = <&ipic>;
271                 };
272
273                 crypto@30000 {
274                         compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
275                                      "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
276                                      "fsl,sec2.0";
277                         reg = <0x30000 0x10000>;
278                         interrupts = <11 0x8>;
279                         interrupt-parent = <&ipic>;
280                         fsl,num-channels = <4>;
281                         fsl,channel-fifo-len = <24>;
282                         fsl,exec-units-mask = <0x97c>;
283                         fsl,descriptor-types-mask = <0x3ab0abf>;
284                 };
285
286                 sata@18000 {
287                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
288                         reg = <0x18000 0x1000>;
289                         cell-index = <1>;
290                         interrupts = <44 0x8>;
291                         interrupt-parent = <&ipic>;
292                 };
293
294                 sata@19000 {
295                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
296                         reg = <0x19000 0x1000>;
297                         cell-index = <2>;
298                         interrupts = <45 0x8>;
299                         interrupt-parent = <&ipic>;
300                 };
301
302                 /* IPIC
303                  * interrupts cell = <intr #, sense>
304                  * sense values match linux IORESOURCE_IRQ_* defines:
305                  * sense == 8: Level, low assertion
306                  * sense == 2: Edge, high-to-low change
307                  */
308                 ipic: interrupt-controller@700 {
309                         interrupt-controller;
310                         #address-cells = <0>;
311                         #interrupt-cells = <2>;
312                         reg = <0x700 0x100>;
313                         device_type = "ipic";
314                 };
315         };
316
317         pci0: pci@e0008500 {
318                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
319                 interrupt-map = <
320                                 /* IDSEL 0x0E -mini PCI */
321                                  0x7000 0x0 0x0 0x1 &ipic 18 0x8
322                                  0x7000 0x0 0x0 0x2 &ipic 18 0x8
323                                  0x7000 0x0 0x0 0x3 &ipic 18 0x8
324                                  0x7000 0x0 0x0 0x4 &ipic 18 0x8
325
326                                 /* IDSEL 0x0F -mini PCI */
327                                  0x7800 0x0 0x0 0x1 &ipic 17 0x8
328                                  0x7800 0x0 0x0 0x2 &ipic 17 0x8
329                                  0x7800 0x0 0x0 0x3 &ipic 17 0x8
330                                  0x7800 0x0 0x0 0x4 &ipic 17 0x8
331
332                                 /* IDSEL 0x10 - PCI slot */
333                                  0x8000 0x0 0x0 0x1 &ipic 48 0x8
334                                  0x8000 0x0 0x0 0x2 &ipic 17 0x8
335                                  0x8000 0x0 0x0 0x3 &ipic 48 0x8
336                                  0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
337                 interrupt-parent = <&ipic>;
338                 interrupts = <66 0x8>;
339                 bus-range = <0x0 0x0>;
340                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
341                           0x42000000 0 0x80000000 0x80000000 0 0x10000000
342                           0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
343                 clock-frequency = <66666666>;
344                 #interrupt-cells = <1>;
345                 #size-cells = <2>;
346                 #address-cells = <3>;
347                 reg = <0xe0008500 0x100         /* internal registers */
348                        0xe0008300 0x8>;         /* config space access registers */
349                 compatible = "fsl,mpc8349-pci";
350                 device_type = "pci";
351         };
352 };