1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
33 #include <asm/irq_regs.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 #include <asm/mdesc.h>
45 extern void calibrate_delay(void);
47 int sparc64_multi_core __read_mostly;
49 /* Please don't make this stuff initdata!!! --DaveM */
50 unsigned char boot_cpu_id;
52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
53 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
54 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
55 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
56 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
57 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
58 static cpumask_t smp_commenced_mask;
59 static cpumask_t cpu_callout_map;
61 void smp_info(struct seq_file *m)
65 seq_printf(m, "State:\n");
66 for_each_online_cpu(i)
67 seq_printf(m, "CPU%d:\t\tonline\n", i);
70 void smp_bogo(struct seq_file *m)
74 for_each_online_cpu(i)
76 "Cpu%dBogo\t: %lu.%02lu\n"
77 "Cpu%dClkTck\t: %016lx\n",
78 i, cpu_data(i).udelay_val / (500000/HZ),
79 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
80 i, cpu_data(i).clock_tick);
83 extern void setup_sparc64_timer(void);
85 static volatile unsigned long callin_flag = 0;
87 void __init smp_callin(void)
89 int cpuid = hard_smp_processor_id();
91 __local_per_cpu_offset = __per_cpu_offset(cpuid);
93 if (tlb_type == hypervisor)
94 sun4v_ktsb_register();
98 setup_sparc64_timer();
100 if (cheetah_pcache_forced_on)
101 cheetah_enable_pcache();
106 cpu_data(cpuid).udelay_val = loops_per_jiffy;
108 __asm__ __volatile__("membar #Sync\n\t"
109 "flush %%g6" : : : "memory");
111 /* Clear this or we will die instantly when we
112 * schedule back to this idler...
114 current_thread_info()->new_child = 0;
116 /* Attach to the address space of init_task. */
117 atomic_inc(&init_mm.mm_count);
118 current->active_mm = &init_mm;
120 while (!cpu_isset(cpuid, smp_commenced_mask))
123 cpu_set(cpuid, cpu_online_map);
125 /* idle thread is expected to have preempt disabled */
131 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
132 panic("SMP bolixed\n");
135 /* This tick register synchronization scheme is taken entirely from
136 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
138 * The only change I've made is to rework it so that the master
139 * initiates the synchonization instead of the slave. -DaveM
143 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
145 #define NUM_ROUNDS 64 /* magic value */
146 #define NUM_ITERS 5 /* likewise */
148 static DEFINE_SPINLOCK(itc_sync_lock);
149 static unsigned long go[SLAVE + 1];
151 #define DEBUG_TICK_SYNC 0
153 static inline long get_delta (long *rt, long *master)
155 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
156 unsigned long tcenter, t0, t1, tm;
159 for (i = 0; i < NUM_ITERS; i++) {
160 t0 = tick_ops->get_tick();
163 while (!(tm = go[SLAVE]))
167 t1 = tick_ops->get_tick();
169 if (t1 - t0 < best_t1 - best_t0)
170 best_t0 = t0, best_t1 = t1, best_tm = tm;
173 *rt = best_t1 - best_t0;
174 *master = best_tm - best_t0;
176 /* average best_t0 and best_t1 without overflow: */
177 tcenter = (best_t0/2 + best_t1/2);
178 if (best_t0 % 2 + best_t1 % 2 == 2)
180 return tcenter - best_tm;
183 void smp_synchronize_tick_client(void)
185 long i, delta, adj, adjust_latency = 0, done = 0;
186 unsigned long flags, rt, master_time_stamp, bound;
189 long rt; /* roundtrip time */
190 long master; /* master's timestamp */
191 long diff; /* difference between midpoint and master's timestamp */
192 long lat; /* estimate of itc adjustment latency */
201 local_irq_save(flags);
203 for (i = 0; i < NUM_ROUNDS; i++) {
204 delta = get_delta(&rt, &master_time_stamp);
206 done = 1; /* let's lock on to this... */
212 adjust_latency += -delta;
213 adj = -delta + adjust_latency/4;
217 tick_ops->add_tick(adj);
221 t[i].master = master_time_stamp;
223 t[i].lat = adjust_latency/4;
227 local_irq_restore(flags);
230 for (i = 0; i < NUM_ROUNDS; i++)
231 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
232 t[i].rt, t[i].master, t[i].diff, t[i].lat);
235 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
236 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
239 static void smp_start_sync_tick_client(int cpu);
241 static void smp_synchronize_one_tick(int cpu)
243 unsigned long flags, i;
247 smp_start_sync_tick_client(cpu);
249 /* wait for client to be ready */
253 /* now let the client proceed into his loop */
257 spin_lock_irqsave(&itc_sync_lock, flags);
259 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
264 go[SLAVE] = tick_ops->get_tick();
268 spin_unlock_irqrestore(&itc_sync_lock, flags);
271 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
273 extern unsigned long sparc64_cpu_startup;
275 /* The OBP cpu startup callback truncates the 3rd arg cookie to
276 * 32-bits (I think) so to be safe we have it read the pointer
277 * contained here so we work on >4GB machines. -DaveM
279 static struct thread_info *cpu_new_thread = NULL;
281 static int __devinit smp_boot_one_cpu(unsigned int cpu)
283 unsigned long entry =
284 (unsigned long)(&sparc64_cpu_startup);
285 unsigned long cookie =
286 (unsigned long)(&cpu_new_thread);
287 struct task_struct *p;
292 cpu_new_thread = task_thread_info(p);
293 cpu_set(cpu, cpu_callout_map);
295 if (tlb_type == hypervisor) {
296 /* Alloc the mondo queues, cpu will load them. */
297 sun4v_init_mondo_queues(0, cpu, 1, 0);
299 prom_startcpu_cpuid(cpu, entry, cookie);
301 struct device_node *dp = of_find_node_by_cpuid(cpu);
303 prom_startcpu(dp->node, entry, cookie);
306 for (timeout = 0; timeout < 5000000; timeout++) {
315 printk("Processor %d is stuck.\n", cpu);
316 cpu_clear(cpu, cpu_callout_map);
319 cpu_new_thread = NULL;
324 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
329 if (this_is_starfire) {
330 /* map to real upaid */
331 cpu = (((cpu & 0x3c) << 1) |
332 ((cpu & 0x40) >> 4) |
336 target = (cpu << 14) | 0x70;
338 /* Ok, this is the real Spitfire Errata #54.
339 * One must read back from a UDB internal register
340 * after writes to the UDB interrupt dispatch, but
341 * before the membar Sync for that write.
342 * So we use the high UDB control register (ASI 0x7f,
343 * ADDR 0x20) for the dummy read. -DaveM
346 __asm__ __volatile__(
347 "wrpr %1, %2, %%pstate\n\t"
348 "stxa %4, [%0] %3\n\t"
349 "stxa %5, [%0+%8] %3\n\t"
351 "stxa %6, [%0+%8] %3\n\t"
353 "stxa %%g0, [%7] %3\n\t"
356 "ldxa [%%g1] 0x7f, %%g0\n\t"
359 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
360 "r" (data0), "r" (data1), "r" (data2), "r" (target),
361 "r" (0x10), "0" (tmp)
364 /* NOTE: PSTATE_IE is still clear. */
367 __asm__ __volatile__("ldxa [%%g0] %1, %0"
369 : "i" (ASI_INTR_DISPATCH_STAT));
371 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
378 } while (result & 0x1);
379 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
382 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
383 smp_processor_id(), result);
390 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
395 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
396 for_each_cpu_mask(i, mask)
397 spitfire_xcall_helper(data0, data1, data2, pstate, i);
400 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
401 * packet, but we have no use for that. However we do take advantage of
402 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
404 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
407 int nack_busy_id, is_jbus, need_more;
409 if (cpus_empty(mask))
412 /* Unfortunately, someone at Sun had the brilliant idea to make the
413 * busy/nack fields hard-coded by ITID number for this Ultra-III
414 * derivative processor.
416 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
417 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
418 (ver >> 32) == __SERRANO_ID);
420 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
424 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
425 : : "r" (pstate), "i" (PSTATE_IE));
427 /* Setup the dispatch data registers. */
428 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
429 "stxa %1, [%4] %6\n\t"
430 "stxa %2, [%5] %6\n\t"
433 : "r" (data0), "r" (data1), "r" (data2),
434 "r" (0x40), "r" (0x50), "r" (0x60),
441 for_each_cpu_mask(i, mask) {
442 u64 target = (i << 14) | 0x70;
445 target |= (nack_busy_id << 24);
446 __asm__ __volatile__(
447 "stxa %%g0, [%0] %1\n\t"
450 : "r" (target), "i" (ASI_INTR_W));
452 if (nack_busy_id == 32) {
459 /* Now, poll for completion. */
464 stuck = 100000 * nack_busy_id;
466 __asm__ __volatile__("ldxa [%%g0] %1, %0"
467 : "=r" (dispatch_stat)
468 : "i" (ASI_INTR_DISPATCH_STAT));
469 if (dispatch_stat == 0UL) {
470 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
472 if (unlikely(need_more)) {
474 for_each_cpu_mask(i, mask) {
486 } while (dispatch_stat & 0x5555555555555555UL);
488 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
491 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
492 /* Busy bits will not clear, continue instead
493 * of freezing up on this cpu.
495 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
496 smp_processor_id(), dispatch_stat);
498 int i, this_busy_nack = 0;
500 /* Delay some random time with interrupts enabled
501 * to prevent deadlock.
503 udelay(2 * nack_busy_id);
505 /* Clear out the mask bits for cpus which did not
508 for_each_cpu_mask(i, mask) {
512 check_mask = (0x2UL << (2*i));
514 check_mask = (0x2UL <<
516 if ((dispatch_stat & check_mask) == 0)
519 if (this_busy_nack == 64)
528 /* Multi-cpu list version. */
529 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
531 struct trap_per_cpu *tb;
534 cpumask_t error_mask;
535 unsigned long flags, status;
536 int cnt, retries, this_cpu, prev_sent, i;
538 if (cpus_empty(mask))
541 /* We have to do this whole thing with interrupts fully disabled.
542 * Otherwise if we send an xcall from interrupt context it will
543 * corrupt both our mondo block and cpu list state.
545 * One consequence of this is that we cannot use timeout mechanisms
546 * that depend upon interrupts being delivered locally. So, for
547 * example, we cannot sample jiffies and expect it to advance.
549 * Fortunately, udelay() uses %stick/%tick so we can use that.
551 local_irq_save(flags);
553 this_cpu = smp_processor_id();
554 tb = &trap_block[this_cpu];
556 mondo = __va(tb->cpu_mondo_block_pa);
562 cpu_list = __va(tb->cpu_list_pa);
564 /* Setup the initial cpu list. */
566 for_each_cpu_mask(i, mask)
569 cpus_clear(error_mask);
573 int forward_progress, n_sent;
575 status = sun4v_cpu_mondo_send(cnt,
577 tb->cpu_mondo_block_pa);
579 /* HV_EOK means all cpus received the xcall, we're done. */
580 if (likely(status == HV_EOK))
583 /* First, see if we made any forward progress.
585 * The hypervisor indicates successful sends by setting
586 * cpu list entries to the value 0xffff.
589 for (i = 0; i < cnt; i++) {
590 if (likely(cpu_list[i] == 0xffff))
594 forward_progress = 0;
595 if (n_sent > prev_sent)
596 forward_progress = 1;
600 /* If we get a HV_ECPUERROR, then one or more of the cpus
601 * in the list are in error state. Use the cpu_state()
602 * hypervisor call to find out which cpus are in error state.
604 if (unlikely(status == HV_ECPUERROR)) {
605 for (i = 0; i < cnt; i++) {
613 err = sun4v_cpu_state(cpu);
615 err == HV_CPU_STATE_ERROR) {
616 cpu_list[i] = 0xffff;
617 cpu_set(cpu, error_mask);
620 } else if (unlikely(status != HV_EWOULDBLOCK))
621 goto fatal_mondo_error;
623 /* Don't bother rewriting the CPU list, just leave the
624 * 0xffff and non-0xffff entries in there and the
625 * hypervisor will do the right thing.
627 * Only advance timeout state if we didn't make any
630 if (unlikely(!forward_progress)) {
631 if (unlikely(++retries > 10000))
632 goto fatal_mondo_timeout;
634 /* Delay a little bit to let other cpus catch up
635 * on their cpu mondo queue work.
641 local_irq_restore(flags);
643 if (unlikely(!cpus_empty(error_mask)))
644 goto fatal_mondo_cpu_error;
648 fatal_mondo_cpu_error:
649 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
650 "were in error state\n",
652 printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
653 for_each_cpu_mask(i, error_mask)
659 local_irq_restore(flags);
660 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
661 " progress after %d retries.\n",
663 goto dump_cpu_list_and_out;
666 local_irq_restore(flags);
667 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
669 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
670 "mondo_block_pa(%lx)\n",
671 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
673 dump_cpu_list_and_out:
674 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
675 for (i = 0; i < cnt; i++)
676 printk("%u ", cpu_list[i]);
680 /* Send cross call to all processors mentioned in MASK
683 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
685 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
686 int this_cpu = get_cpu();
688 cpus_and(mask, mask, cpu_online_map);
689 cpu_clear(this_cpu, mask);
691 if (tlb_type == spitfire)
692 spitfire_xcall_deliver(data0, data1, data2, mask);
693 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
694 cheetah_xcall_deliver(data0, data1, data2, mask);
696 hypervisor_xcall_deliver(data0, data1, data2, mask);
697 /* NOTE: Caller runs local copy on master. */
702 extern unsigned long xcall_sync_tick;
704 static void smp_start_sync_tick_client(int cpu)
706 cpumask_t mask = cpumask_of_cpu(cpu);
708 smp_cross_call_masked(&xcall_sync_tick,
712 /* Send cross call to all processors except self. */
713 #define smp_cross_call(func, ctx, data1, data2) \
714 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
716 struct call_data_struct {
717 void (*func) (void *info);
723 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
724 static struct call_data_struct *call_data;
726 extern unsigned long xcall_call_function;
729 * smp_call_function(): Run a function on all other CPUs.
730 * @func: The function to run. This must be fast and non-blocking.
731 * @info: An arbitrary pointer to pass to the function.
732 * @nonatomic: currently unused.
733 * @wait: If true, wait (atomically) until function has completed on other CPUs.
735 * Returns 0 on success, else a negative status code. Does not return until
736 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
738 * You must not call this function with disabled interrupts or from a
739 * hardware interrupt handler or from a bottom half handler.
741 static int smp_call_function_mask(void (*func)(void *info), void *info,
742 int nonatomic, int wait, cpumask_t mask)
744 struct call_data_struct data;
747 /* Can deadlock when called with interrupts disabled */
748 WARN_ON(irqs_disabled());
752 atomic_set(&data.finished, 0);
755 spin_lock(&call_lock);
757 cpu_clear(smp_processor_id(), mask);
758 cpus = cpus_weight(mask);
765 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
767 /* Wait for response */
768 while (atomic_read(&data.finished) != cpus)
772 spin_unlock(&call_lock);
777 int smp_call_function(void (*func)(void *info), void *info,
778 int nonatomic, int wait)
780 return smp_call_function_mask(func, info, nonatomic, wait,
784 void smp_call_function_client(int irq, struct pt_regs *regs)
786 void (*func) (void *info) = call_data->func;
787 void *info = call_data->info;
789 clear_softint(1 << irq);
790 if (call_data->wait) {
791 /* let initiator proceed only after completion */
793 atomic_inc(&call_data->finished);
795 /* let initiator proceed after getting data */
796 atomic_inc(&call_data->finished);
801 static void tsb_sync(void *info)
803 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
804 struct mm_struct *mm = info;
806 /* It is not valid to test "currrent->active_mm == mm" here.
808 * The value of "current" is not changed atomically with
809 * switch_mm(). But that's OK, we just need to check the
810 * current cpu's trap block PGD physical address.
812 if (tp->pgd_paddr == __pa(mm->pgd))
813 tsb_context_switch(mm);
816 void smp_tsb_sync(struct mm_struct *mm)
818 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
821 extern unsigned long xcall_flush_tlb_mm;
822 extern unsigned long xcall_flush_tlb_pending;
823 extern unsigned long xcall_flush_tlb_kernel_range;
824 extern unsigned long xcall_report_regs;
825 extern unsigned long xcall_receive_signal;
826 extern unsigned long xcall_new_mmu_context_version;
828 #ifdef DCACHE_ALIASING_POSSIBLE
829 extern unsigned long xcall_flush_dcache_page_cheetah;
831 extern unsigned long xcall_flush_dcache_page_spitfire;
833 #ifdef CONFIG_DEBUG_DCFLUSH
834 extern atomic_t dcpage_flushes;
835 extern atomic_t dcpage_flushes_xcall;
838 static __inline__ void __local_flush_dcache_page(struct page *page)
840 #ifdef DCACHE_ALIASING_POSSIBLE
841 __flush_dcache_page(page_address(page),
842 ((tlb_type == spitfire) &&
843 page_mapping(page) != NULL));
845 if (page_mapping(page) != NULL &&
846 tlb_type == spitfire)
847 __flush_icache_page(__pa(page_address(page)));
851 void smp_flush_dcache_page_impl(struct page *page, int cpu)
853 cpumask_t mask = cpumask_of_cpu(cpu);
856 if (tlb_type == hypervisor)
859 #ifdef CONFIG_DEBUG_DCFLUSH
860 atomic_inc(&dcpage_flushes);
863 this_cpu = get_cpu();
865 if (cpu == this_cpu) {
866 __local_flush_dcache_page(page);
867 } else if (cpu_online(cpu)) {
868 void *pg_addr = page_address(page);
871 if (tlb_type == spitfire) {
873 ((u64)&xcall_flush_dcache_page_spitfire);
874 if (page_mapping(page) != NULL)
875 data0 |= ((u64)1 << 32);
876 spitfire_xcall_deliver(data0,
880 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
881 #ifdef DCACHE_ALIASING_POSSIBLE
883 ((u64)&xcall_flush_dcache_page_cheetah);
884 cheetah_xcall_deliver(data0,
889 #ifdef CONFIG_DEBUG_DCFLUSH
890 atomic_inc(&dcpage_flushes_xcall);
897 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
899 void *pg_addr = page_address(page);
900 cpumask_t mask = cpu_online_map;
904 if (tlb_type == hypervisor)
907 this_cpu = get_cpu();
909 cpu_clear(this_cpu, mask);
911 #ifdef CONFIG_DEBUG_DCFLUSH
912 atomic_inc(&dcpage_flushes);
914 if (cpus_empty(mask))
916 if (tlb_type == spitfire) {
917 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
918 if (page_mapping(page) != NULL)
919 data0 |= ((u64)1 << 32);
920 spitfire_xcall_deliver(data0,
924 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
925 #ifdef DCACHE_ALIASING_POSSIBLE
926 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
927 cheetah_xcall_deliver(data0,
932 #ifdef CONFIG_DEBUG_DCFLUSH
933 atomic_inc(&dcpage_flushes_xcall);
936 __local_flush_dcache_page(page);
941 static void __smp_receive_signal_mask(cpumask_t mask)
943 smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
946 void smp_receive_signal(int cpu)
948 cpumask_t mask = cpumask_of_cpu(cpu);
951 __smp_receive_signal_mask(mask);
954 void smp_receive_signal_client(int irq, struct pt_regs *regs)
956 clear_softint(1 << irq);
959 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
961 struct mm_struct *mm;
964 clear_softint(1 << irq);
966 /* See if we need to allocate a new TLB context because
967 * the version of the one we are using is now out of date.
969 mm = current->active_mm;
970 if (unlikely(!mm || (mm == &init_mm)))
973 spin_lock_irqsave(&mm->context.lock, flags);
975 if (unlikely(!CTX_VALID(mm->context)))
976 get_new_mmu_context(mm);
978 spin_unlock_irqrestore(&mm->context.lock, flags);
980 load_secondary_context(mm);
981 __flush_tlb_mm(CTX_HWBITS(mm->context),
985 void smp_new_mmu_context_version(void)
987 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
990 void smp_report_regs(void)
992 smp_cross_call(&xcall_report_regs, 0, 0, 0);
995 /* We know that the window frames of the user have been flushed
996 * to the stack before we get here because all callers of us
997 * are flush_tlb_*() routines, and these run after flush_cache_*()
998 * which performs the flushw.
1000 * The SMP TLB coherency scheme we use works as follows:
1002 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1003 * space has (potentially) executed on, this is the heuristic
1004 * we use to avoid doing cross calls.
1006 * Also, for flushing from kswapd and also for clones, we
1007 * use cpu_vm_mask as the list of cpus to make run the TLB.
1009 * 2) TLB context numbers are shared globally across all processors
1010 * in the system, this allows us to play several games to avoid
1013 * One invariant is that when a cpu switches to a process, and
1014 * that processes tsk->active_mm->cpu_vm_mask does not have the
1015 * current cpu's bit set, that tlb context is flushed locally.
1017 * If the address space is non-shared (ie. mm->count == 1) we avoid
1018 * cross calls when we want to flush the currently running process's
1019 * tlb state. This is done by clearing all cpu bits except the current
1020 * processor's in current->active_mm->cpu_vm_mask and performing the
1021 * flush locally only. This will force any subsequent cpus which run
1022 * this task to flush the context from the local tlb if the process
1023 * migrates to another cpu (again).
1025 * 3) For shared address spaces (threads) and swapping we bite the
1026 * bullet for most cases and perform the cross call (but only to
1027 * the cpus listed in cpu_vm_mask).
1029 * The performance gain from "optimizing" away the cross call for threads is
1030 * questionable (in theory the big win for threads is the massive sharing of
1031 * address space state across processors).
1034 /* This currently is only used by the hugetlb arch pre-fault
1035 * hook on UltraSPARC-III+ and later when changing the pagesize
1036 * bits of the context register for an address space.
1038 void smp_flush_tlb_mm(struct mm_struct *mm)
1040 u32 ctx = CTX_HWBITS(mm->context);
1041 int cpu = get_cpu();
1043 if (atomic_read(&mm->mm_users) == 1) {
1044 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1045 goto local_flush_and_out;
1048 smp_cross_call_masked(&xcall_flush_tlb_mm,
1052 local_flush_and_out:
1053 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1058 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1060 u32 ctx = CTX_HWBITS(mm->context);
1061 int cpu = get_cpu();
1063 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1064 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1066 smp_cross_call_masked(&xcall_flush_tlb_pending,
1067 ctx, nr, (unsigned long) vaddrs,
1070 __flush_tlb_pending(ctx, nr, vaddrs);
1075 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1078 end = PAGE_ALIGN(end);
1080 smp_cross_call(&xcall_flush_tlb_kernel_range,
1083 __flush_tlb_kernel_range(start, end);
1088 /* #define CAPTURE_DEBUG */
1089 extern unsigned long xcall_capture;
1091 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1092 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1093 static unsigned long penguins_are_doing_time;
1095 void smp_capture(void)
1097 int result = atomic_add_ret(1, &smp_capture_depth);
1100 int ncpus = num_online_cpus();
1102 #ifdef CAPTURE_DEBUG
1103 printk("CPU[%d]: Sending penguins to jail...",
1104 smp_processor_id());
1106 penguins_are_doing_time = 1;
1107 membar_storestore_loadstore();
1108 atomic_inc(&smp_capture_registry);
1109 smp_cross_call(&xcall_capture, 0, 0, 0);
1110 while (atomic_read(&smp_capture_registry) != ncpus)
1112 #ifdef CAPTURE_DEBUG
1118 void smp_release(void)
1120 if (atomic_dec_and_test(&smp_capture_depth)) {
1121 #ifdef CAPTURE_DEBUG
1122 printk("CPU[%d]: Giving pardon to "
1123 "imprisoned penguins\n",
1124 smp_processor_id());
1126 penguins_are_doing_time = 0;
1127 membar_storeload_storestore();
1128 atomic_dec(&smp_capture_registry);
1132 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1133 * can service tlb flush xcalls...
1135 extern void prom_world(int);
1137 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1139 clear_softint(1 << irq);
1143 __asm__ __volatile__("flushw");
1145 atomic_inc(&smp_capture_registry);
1146 membar_storeload_storestore();
1147 while (penguins_are_doing_time)
1149 atomic_dec(&smp_capture_registry);
1155 void __init smp_tick_init(void)
1157 boot_cpu_id = hard_smp_processor_id();
1160 /* /proc/profile writes can call this, don't __init it please. */
1161 int setup_profiling_timer(unsigned int multiplier)
1166 static void __init smp_tune_scheduling(void)
1168 unsigned int smallest = ~0U;
1171 for (i = 0; i < NR_CPUS; i++) {
1172 unsigned int val = cpu_data(i).ecache_size;
1174 if (val && val < smallest)
1178 /* Any value less than 256K is nonsense. */
1179 if (smallest < (256U * 1024U))
1180 smallest = 256 * 1024;
1182 max_cache_size = smallest;
1184 if (smallest < 1U * 1024U * 1024U)
1185 printk(KERN_INFO "Using max_cache_size of %uKB\n",
1188 printk(KERN_INFO "Using max_cache_size of %uMB\n",
1189 smallest / 1024U / 1024U);
1192 /* Constrain the number of cpus to max_cpus. */
1193 void __init smp_prepare_cpus(unsigned int max_cpus)
1197 if (num_possible_cpus() > max_cpus) {
1198 for_each_possible_cpu(i) {
1199 if (i != boot_cpu_id) {
1200 cpu_clear(i, phys_cpu_present_map);
1201 cpu_clear(i, cpu_present_map);
1202 if (num_possible_cpus() <= max_cpus)
1208 cpu_data(boot_cpu_id).udelay_val = loops_per_jiffy;
1209 smp_tune_scheduling();
1212 void __devinit smp_prepare_boot_cpu(void)
1216 void __devinit smp_fill_in_sib_core_maps(void)
1220 for_each_possible_cpu(i) {
1223 if (cpu_data(i).core_id == 0) {
1224 cpu_set(i, cpu_core_map[i]);
1228 for_each_possible_cpu(j) {
1229 if (cpu_data(i).core_id ==
1230 cpu_data(j).core_id)
1231 cpu_set(j, cpu_core_map[i]);
1235 for_each_possible_cpu(i) {
1238 if (cpu_data(i).proc_id == -1) {
1239 cpu_set(i, cpu_sibling_map[i]);
1243 for_each_possible_cpu(j) {
1244 if (cpu_data(i).proc_id ==
1245 cpu_data(j).proc_id)
1246 cpu_set(j, cpu_sibling_map[i]);
1251 int __cpuinit __cpu_up(unsigned int cpu)
1253 int ret = smp_boot_one_cpu(cpu);
1256 cpu_set(cpu, smp_commenced_mask);
1257 while (!cpu_isset(cpu, cpu_online_map))
1259 if (!cpu_isset(cpu, cpu_online_map)) {
1262 /* On SUN4V, writes to %tick and %stick are
1265 if (tlb_type != hypervisor)
1266 smp_synchronize_one_tick(cpu);
1272 void __init smp_cpus_done(unsigned int max_cpus)
1274 unsigned long bogosum = 0;
1277 for_each_online_cpu(i)
1278 bogosum += cpu_data(i).udelay_val;
1279 printk("Total of %ld processors activated "
1280 "(%lu.%02lu BogoMIPS).\n",
1281 (long) num_online_cpus(),
1282 bogosum/(500000/HZ),
1283 (bogosum/(5000/HZ))%100);
1286 void smp_send_reschedule(int cpu)
1288 smp_receive_signal(cpu);
1291 /* This is a nop because we capture all other cpus
1292 * anyways when making the PROM active.
1294 void smp_send_stop(void)
1298 unsigned long __per_cpu_base __read_mostly;
1299 unsigned long __per_cpu_shift __read_mostly;
1301 EXPORT_SYMBOL(__per_cpu_base);
1302 EXPORT_SYMBOL(__per_cpu_shift);
1304 void __init real_setup_per_cpu_areas(void)
1306 unsigned long goal, size, i;
1309 /* Copy section for each CPU (we discard the original) */
1310 goal = PERCPU_ENOUGH_ROOM;
1312 __per_cpu_shift = PAGE_SHIFT;
1313 for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1316 ptr = alloc_bootmem_pages(size * NR_CPUS);
1318 __per_cpu_base = ptr - __per_cpu_start;
1320 for (i = 0; i < NR_CPUS; i++, ptr += size)
1321 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1323 /* Setup %g5 for the boot cpu. */
1324 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());