git.oblomov.eu Git - linux-2.6/blob - arch/sparc64/kernel/irq.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/irq.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/prom.h>
  37 #include <asm/timer.h>
  38 #include <asm/smp.h>
  39 #include <asm/starfire.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/cache.h>
  42 #include <asm/cpudata.h>
  43 #include <asm/auxio.h>
  44 #include <asm/head.h>
  45 #include <asm/hypervisor.h>
  46 #include <asm/cacheflush.h>
  47
  48 #include "entry.h"
  49
  50 #define NUM_IVECS       (IMAP_INR + 1)
  51
  52 struct ino_bucket *ivector_table;
  53 unsigned long ivector_table_pa;
  54
  55 /* On several sun4u processors, it is illegal to mix bypass and
  56  * non-bypass accesses.  Therefore we access all INO buckets
  57  * using bypass accesses only.
  58  */
  59 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  60 {
  61         unsigned long ret;
  62
  63         __asm__ __volatile__("ldxa      [%1] %2, %0"
  64                              : "=&r" (ret)
  65                              : "r" (bucket_pa +
  66                                     offsetof(struct ino_bucket,
  67                                              __irq_chain_pa)),
  68                                "i" (ASI_PHYS_USE_EC));
  69
  70         return ret;
  71 }
  72
  73 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  74 {
  75         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  76                              : /* no outputs */
  77                              : "r" (bucket_pa +
  78                                     offsetof(struct ino_bucket,
  79                                              __irq_chain_pa)),
  80                                "i" (ASI_PHYS_USE_EC));
  81 }
  82
  83 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
  84 {
  85         unsigned int ret;
  86
  87         __asm__ __volatile__("lduwa     [%1] %2, %0"
  88                              : "=&r" (ret)
  89                              : "r" (bucket_pa +
  90                                     offsetof(struct ino_bucket,
  91                                              __virt_irq)),
  92                                "i" (ASI_PHYS_USE_EC));
  93
  94         return ret;
  95 }
  96
  97 static void bucket_set_virt_irq(unsigned long bucket_pa,
  98                                 unsigned int virt_irq)
  99 {
 100         __asm__ __volatile__("stwa      %0, [%1] %2"
 101                              : /* no outputs */
 102                              : "r" (virt_irq),
 103                                "r" (bucket_pa +
 104                                     offsetof(struct ino_bucket,
 105                                              __virt_irq)),
 106                                "i" (ASI_PHYS_USE_EC));
 107 }
 108
 109 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 110
 111 static struct {
 112         unsigned int dev_handle;
 113         unsigned int dev_ino;
 114         unsigned int in_use;
 115 } virt_irq_table[NR_IRQS];
 116 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
 117
 118 unsigned char virt_irq_alloc(unsigned int dev_handle,
 119                              unsigned int dev_ino)
 120 {
 121         unsigned long flags;
 122         unsigned char ent;
 123
 124         BUILD_BUG_ON(NR_IRQS >= 256);
 125
 126         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 127
 128         for (ent = 1; ent < NR_IRQS; ent++) {
 129                 if (!virt_irq_table[ent].in_use)
 130                         break;
 131         }
 132         if (ent >= NR_IRQS) {
 133                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 134                 ent = 0;
 135         } else {
 136                 virt_irq_table[ent].dev_handle = dev_handle;
 137                 virt_irq_table[ent].dev_ino = dev_ino;
 138                 virt_irq_table[ent].in_use = 1;
 139         }
 140
 141         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 142
 143         return ent;
 144 }
 145
 146 #ifdef CONFIG_PCI_MSI
 147 void virt_irq_free(unsigned int virt_irq)
 148 {
 149         unsigned long flags;
 150
 151         if (virt_irq >= NR_IRQS)
 152                 return;
 153
 154         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 155
 156         virt_irq_table[virt_irq].in_use = 0;
 157
 158         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 159 }
 160 #endif
 161
 162 /*
 163  * /proc/interrupts printing:
 164  */
 165
 166 int show_interrupts(struct seq_file *p, void *v)
 167 {
 168         int i = *(loff_t *) v, j;
 169         struct irqaction * action;
 170         unsigned long flags;
 171
 172         if (i == 0) {
 173                 seq_printf(p, "           ");
 174                 for_each_online_cpu(j)
 175                         seq_printf(p, "CPU%d       ",j);
 176                 seq_putc(p, '\n');
 177         }
 178
 179         if (i < NR_IRQS) {
 180                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 181                 action = irq_desc[i].action;
 182                 if (!action)
 183                         goto skip;
 184                 seq_printf(p, "%3d: ",i);
 185 #ifndef CONFIG_SMP
 186                 seq_printf(p, "%10u ", kstat_irqs(i));
 187 #else
 188                 for_each_online_cpu(j)
 189                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 190 #endif
 191                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
 192                 seq_printf(p, "  %s", action->name);
 193
 194                 for (action=action->next; action; action = action->next)
 195                         seq_printf(p, ", %s", action->name);
 196
 197                 seq_putc(p, '\n');
 198 skip:
 199                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 200         }
 201         return 0;
 202 }
 203
 204 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 205 {
 206         unsigned int tid;
 207
 208         if (this_is_starfire) {
 209                 tid = starfire_translate(imap, cpuid);
 210                 tid <<= IMAP_TID_SHIFT;
 211                 tid &= IMAP_TID_UPA;
 212         } else {
 213                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 214                         unsigned long ver;
 215
 216                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 217                         if ((ver >> 32UL) == __JALAPENO_ID ||
 218                             (ver >> 32UL) == __SERRANO_ID) {
 219                                 tid = cpuid << IMAP_TID_SHIFT;
 220                                 tid &= IMAP_TID_JBUS;
 221                         } else {
 222                                 unsigned int a = cpuid & 0x1f;
 223                                 unsigned int n = (cpuid >> 5) & 0x1f;
 224
 225                                 tid = ((a << IMAP_AID_SHIFT) |
 226                                        (n << IMAP_NID_SHIFT));
 227                                 tid &= (IMAP_AID_SAFARI |
 228                                         IMAP_NID_SAFARI);;
 229                         }
 230                 } else {
 231                         tid = cpuid << IMAP_TID_SHIFT;
 232                         tid &= IMAP_TID_UPA;
 233                 }
 234         }
 235
 236         return tid;
 237 }
 238
 239 struct irq_handler_data {
 240         unsigned long   iclr;
 241         unsigned long   imap;
 242
 243         void            (*pre_handler)(unsigned int, void *, void *);
 244         void            *arg1;
 245         void            *arg2;
 246 };
 247
 248 #ifdef CONFIG_SMP
 249 static int irq_choose_cpu(unsigned int virt_irq)
 250 {
 251         cpumask_t mask = irq_desc[virt_irq].affinity;
 252         int cpuid;
 253
 254         if (cpus_equal(mask, CPU_MASK_ALL)) {
 255                 static int irq_rover;
 256                 static DEFINE_SPINLOCK(irq_rover_lock);
 257                 unsigned long flags;
 258
 259                 /* Round-robin distribution... */
 260         do_round_robin:
 261                 spin_lock_irqsave(&irq_rover_lock, flags);
 262
 263                 while (!cpu_online(irq_rover)) {
 264                         if (++irq_rover >= NR_CPUS)
 265                                 irq_rover = 0;
 266                 }
 267                 cpuid = irq_rover;
 268                 do {
 269                         if (++irq_rover >= NR_CPUS)
 270                                 irq_rover = 0;
 271                 } while (!cpu_online(irq_rover));
 272
 273                 spin_unlock_irqrestore(&irq_rover_lock, flags);
 274         } else {
 275                 cpumask_t tmp;
 276
 277                 cpus_and(tmp, cpu_online_map, mask);
 278
 279                 if (cpus_empty(tmp))
 280                         goto do_round_robin;
 281
 282                 cpuid = first_cpu(tmp);
 283         }
 284
 285         return cpuid;
 286 }
 287 #else
 288 static int irq_choose_cpu(unsigned int virt_irq)
 289 {
 290         return real_hard_smp_processor_id();
 291 }
 292 #endif
 293
 294 static void sun4u_irq_enable(unsigned int virt_irq)
 295 {
 296         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 297
 298         if (likely(data)) {
 299                 unsigned long cpuid, imap, val;
 300                 unsigned int tid;
 301
 302                 cpuid = irq_choose_cpu(virt_irq);
 303                 imap = data->imap;
 304
 305                 tid = sun4u_compute_tid(imap, cpuid);
 306
 307                 val = upa_readq(imap);
 308                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 309                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 310                 val |= tid | IMAP_VALID;
 311                 upa_writeq(val, imap);
 312                 upa_writeq(ICLR_IDLE, data->iclr);
 313         }
 314 }
 315
 316 static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
 317 {
 318         sun4u_irq_enable(virt_irq);
 319 }
 320
 321 static void sun4u_irq_disable(unsigned int virt_irq)
 322 {
 323         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 324
 325         if (likely(data)) {
 326                 unsigned long imap = data->imap;
 327                 unsigned long tmp = upa_readq(imap);
 328
 329                 tmp &= ~IMAP_VALID;
 330                 upa_writeq(tmp, imap);
 331         }
 332 }
 333
 334 static void sun4u_irq_eoi(unsigned int virt_irq)
 335 {
 336         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 337         struct irq_desc *desc = irq_desc + virt_irq;
 338
 339         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 340                 return;
 341
 342         if (likely(data))
 343                 upa_writeq(ICLR_IDLE, data->iclr);
 344 }
 345
 346 static void sun4v_irq_enable(unsigned int virt_irq)
 347 {
 348         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 349         unsigned long cpuid = irq_choose_cpu(virt_irq);
 350         int err;
 351
 352         err = sun4v_intr_settarget(ino, cpuid);
 353         if (err != HV_EOK)
 354                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 355                        "err(%d)\n", ino, cpuid, err);
 356         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 357         if (err != HV_EOK)
 358                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 359                        "err(%d)\n", ino, err);
 360         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 361         if (err != HV_EOK)
 362                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 363                        ino, err);
 364 }
 365
 366 static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
 367 {
 368         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 369         unsigned long cpuid = irq_choose_cpu(virt_irq);
 370         int err;
 371
 372         err = sun4v_intr_settarget(ino, cpuid);
 373         if (err != HV_EOK)
 374                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 375                        "err(%d)\n", ino, cpuid, err);
 376 }
 377
 378 static void sun4v_irq_disable(unsigned int virt_irq)
 379 {
 380         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 381         int err;
 382
 383         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 384         if (err != HV_EOK)
 385                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 386                        "err(%d)\n", ino, err);
 387 }
 388
 389 static void sun4v_irq_eoi(unsigned int virt_irq)
 390 {
 391         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 392         struct irq_desc *desc = irq_desc + virt_irq;
 393         int err;
 394
 395         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 396                 return;
 397
 398         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 399         if (err != HV_EOK)
 400                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 401                        "err(%d)\n", ino, err);
 402 }
 403
 404 static void sun4v_virq_enable(unsigned int virt_irq)
 405 {
 406         unsigned long cpuid, dev_handle, dev_ino;
 407         int err;
 408
 409         cpuid = irq_choose_cpu(virt_irq);
 410
 411         dev_handle = virt_irq_table[virt_irq].dev_handle;
 412         dev_ino = virt_irq_table[virt_irq].dev_ino;
 413
 414         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 415         if (err != HV_EOK)
 416                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 417                        "err(%d)\n",
 418                        dev_handle, dev_ino, cpuid, err);
 419         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 420                                     HV_INTR_STATE_IDLE);
 421         if (err != HV_EOK)
 422                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 423                        "HV_INTR_STATE_IDLE): err(%d)\n",
 424                        dev_handle, dev_ino, err);
 425         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 426                                     HV_INTR_ENABLED);
 427         if (err != HV_EOK)
 428                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 429                        "HV_INTR_ENABLED): err(%d)\n",
 430                        dev_handle, dev_ino, err);
 431 }
 432
 433 static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
 434 {
 435         unsigned long cpuid, dev_handle, dev_ino;
 436         int err;
 437
 438         cpuid = irq_choose_cpu(virt_irq);
 439
 440         dev_handle = virt_irq_table[virt_irq].dev_handle;
 441         dev_ino = virt_irq_table[virt_irq].dev_ino;
 442
 443         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 444         if (err != HV_EOK)
 445                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 446                        "err(%d)\n",
 447                        dev_handle, dev_ino, cpuid, err);
 448 }
 449
 450 static void sun4v_virq_disable(unsigned int virt_irq)
 451 {
 452         unsigned long dev_handle, dev_ino;
 453         int err;
 454
 455         dev_handle = virt_irq_table[virt_irq].dev_handle;
 456         dev_ino = virt_irq_table[virt_irq].dev_ino;
 457
 458         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 459                                     HV_INTR_DISABLED);
 460         if (err != HV_EOK)
 461                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 462                        "HV_INTR_DISABLED): err(%d)\n",
 463                        dev_handle, dev_ino, err);
 464 }
 465
 466 static void sun4v_virq_eoi(unsigned int virt_irq)
 467 {
 468         struct irq_desc *desc = irq_desc + virt_irq;
 469         unsigned long dev_handle, dev_ino;
 470         int err;
 471
 472         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 473                 return;
 474
 475         dev_handle = virt_irq_table[virt_irq].dev_handle;
 476         dev_ino = virt_irq_table[virt_irq].dev_ino;
 477
 478         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 479                                     HV_INTR_STATE_IDLE);
 480         if (err != HV_EOK)
 481                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 482                        "HV_INTR_STATE_IDLE): err(%d)\n",
 483                        dev_handle, dev_ino, err);
 484 }
 485
 486 static struct irq_chip sun4u_irq = {
 487         .typename       = "sun4u",
 488         .enable         = sun4u_irq_enable,
 489         .disable        = sun4u_irq_disable,
 490         .eoi            = sun4u_irq_eoi,
 491         .set_affinity   = sun4u_set_affinity,
 492 };
 493
 494 static struct irq_chip sun4v_irq = {
 495         .typename       = "sun4v",
 496         .enable         = sun4v_irq_enable,
 497         .disable        = sun4v_irq_disable,
 498         .eoi            = sun4v_irq_eoi,
 499         .set_affinity   = sun4v_set_affinity,
 500 };
 501
 502 static struct irq_chip sun4v_virq = {
 503         .typename       = "vsun4v",
 504         .enable         = sun4v_virq_enable,
 505         .disable        = sun4v_virq_disable,
 506         .eoi            = sun4v_virq_eoi,
 507         .set_affinity   = sun4v_virt_set_affinity,
 508 };
 509
 510 static void pre_flow_handler(unsigned int virt_irq,
 511                                       struct irq_desc *desc)
 512 {
 513         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 514         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 515
 516         data->pre_handler(ino, data->arg1, data->arg2);
 517
 518         handle_fasteoi_irq(virt_irq, desc);
 519 }
 520
 521 void irq_install_pre_handler(int virt_irq,
 522                              void (*func)(unsigned int, void *, void *),
 523                              void *arg1, void *arg2)
 524 {
 525         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 526         struct irq_desc *desc = irq_desc + virt_irq;
 527
 528         data->pre_handler = func;
 529         data->arg1 = arg1;
 530         data->arg2 = arg2;
 531
 532         desc->handle_irq = pre_flow_handler;
 533 }
 534
 535 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 536 {
 537         struct ino_bucket *bucket;
 538         struct irq_handler_data *data;
 539         unsigned int virt_irq;
 540         int ino;
 541
 542         BUG_ON(tlb_type == hypervisor);
 543
 544         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 545         bucket = &ivector_table[ino];
 546         virt_irq = bucket_get_virt_irq(__pa(bucket));
 547         if (!virt_irq) {
 548                 virt_irq = virt_irq_alloc(0, ino);
 549                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 550                 set_irq_chip_and_handler_name(virt_irq,
 551                                               &sun4u_irq,
 552                                               handle_fasteoi_irq,
 553                                               "IVEC");
 554         }
 555
 556         data = get_irq_chip_data(virt_irq);
 557         if (unlikely(data))
 558                 goto out;
 559
 560         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 561         if (unlikely(!data)) {
 562                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 563                 prom_halt();
 564         }
 565         set_irq_chip_data(virt_irq, data);
 566
 567         data->imap  = imap;
 568         data->iclr  = iclr;
 569
 570 out:
 571         return virt_irq;
 572 }
 573
 574 static unsigned int sun4v_build_common(unsigned long sysino,
 575                                        struct irq_chip *chip)
 576 {
 577         struct ino_bucket *bucket;
 578         struct irq_handler_data *data;
 579         unsigned int virt_irq;
 580
 581         BUG_ON(tlb_type != hypervisor);
 582
 583         bucket = &ivector_table[sysino];
 584         virt_irq = bucket_get_virt_irq(__pa(bucket));
 585         if (!virt_irq) {
 586                 virt_irq = virt_irq_alloc(0, sysino);
 587                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 588                 set_irq_chip_and_handler_name(virt_irq, chip,
 589                                               handle_fasteoi_irq,
 590                                               "IVEC");
 591         }
 592
 593         data = get_irq_chip_data(virt_irq);
 594         if (unlikely(data))
 595                 goto out;
 596
 597         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 598         if (unlikely(!data)) {
 599                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 600                 prom_halt();
 601         }
 602         set_irq_chip_data(virt_irq, data);
 603
 604         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 605          * is done by hypervisor calls on sun4v platforms, not by direct
 606          * register accesses.
 607          */
 608         data->imap = ~0UL;
 609         data->iclr = ~0UL;
 610
 611 out:
 612         return virt_irq;
 613 }
 614
 615 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 616 {
 617         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 618
 619         return sun4v_build_common(sysino, &sun4v_irq);
 620 }
 621
 622 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 623 {
 624         struct irq_handler_data *data;
 625         unsigned long hv_err, cookie;
 626         struct ino_bucket *bucket;
 627         struct irq_desc *desc;
 628         unsigned int virt_irq;
 629
 630         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 631         if (unlikely(!bucket))
 632                 return 0;
 633         __flush_dcache_range((unsigned long) bucket,
 634                              ((unsigned long) bucket +
 635                               sizeof(struct ino_bucket)));
 636
 637         virt_irq = virt_irq_alloc(devhandle, devino);
 638         bucket_set_virt_irq(__pa(bucket), virt_irq);
 639
 640         set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
 641                                       handle_fasteoi_irq,
 642                                       "IVEC");
 643
 644         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 645         if (unlikely(!data))
 646                 return 0;
 647
 648         /* In order to make the LDC channel startup sequence easier,
 649          * especially wrt. locking, we do not let request_irq() enable
 650          * the interrupt.
 651          */
 652         desc = irq_desc + virt_irq;
 653         desc->status |= IRQ_NOAUTOEN;
 654
 655         set_irq_chip_data(virt_irq, data);
 656
 657         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 658          * is done by hypervisor calls on sun4v platforms, not by direct
 659          * register accesses.
 660          */
 661         data->imap = ~0UL;
 662         data->iclr = ~0UL;
 663
 664         cookie = ~__pa(bucket);
 665         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 666         if (hv_err) {
 667                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 668                             "err=%lu\n", devhandle, devino, hv_err);
 669                 prom_halt();
 670         }
 671
 672         return virt_irq;
 673 }
 674
 675 void ack_bad_irq(unsigned int virt_irq)
 676 {
 677         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 678
 679         if (!ino)
 680                 ino = 0xdeadbeef;
 681
 682         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
 683                ino, virt_irq);
 684 }
 685
 686 void *hardirq_stack[NR_CPUS];
 687 void *softirq_stack[NR_CPUS];
 688
 689 static __attribute__((always_inline)) void *set_hardirq_stack(void)
 690 {
 691         void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
 692
 693         __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
 694         if (orig_sp < sp ||
 695             orig_sp > (sp + THREAD_SIZE)) {
 696                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 697                 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
 698         }
 699
 700         return orig_sp;
 701 }
 702 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
 703 {
 704         __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
 705 }
 706
 707 void handler_irq(int irq, struct pt_regs *regs)
 708 {
 709         unsigned long pstate, bucket_pa;
 710         struct pt_regs *old_regs;
 711         void *orig_sp;
 712
 713         clear_softint(1 << irq);
 714
 715         old_regs = set_irq_regs(regs);
 716         irq_enter();
 717
 718         /* Grab an atomic snapshot of the pending IVECs.  */
 719         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 720                              "wrpr      %0, %3, %%pstate\n\t"
 721                              "ldx       [%2], %1\n\t"
 722                              "stx       %%g0, [%2]\n\t"
 723                              "wrpr      %0, 0x0, %%pstate\n\t"
 724                              : "=&r" (pstate), "=&r" (bucket_pa)
 725                              : "r" (irq_work_pa(smp_processor_id())),
 726                                "i" (PSTATE_IE)
 727                              : "memory");
 728
 729         orig_sp = set_hardirq_stack();
 730
 731         while (bucket_pa) {
 732                 struct irq_desc *desc;
 733                 unsigned long next_pa;
 734                 unsigned int virt_irq;
 735
 736                 next_pa = bucket_get_chain_pa(bucket_pa);
 737                 virt_irq = bucket_get_virt_irq(bucket_pa);
 738                 bucket_clear_chain_pa(bucket_pa);
 739
 740                 desc = irq_desc + virt_irq;
 741
 742                 desc->handle_irq(virt_irq, desc);
 743
 744                 bucket_pa = next_pa;
 745         }
 746
 747         restore_hardirq_stack(orig_sp);
 748
 749         irq_exit();
 750         set_irq_regs(old_regs);
 751 }
 752
 753 void do_softirq(void)
 754 {
 755         unsigned long flags;
 756
 757         if (in_interrupt())
 758                 return;
 759
 760         local_irq_save(flags);
 761
 762         if (local_softirq_pending()) {
 763                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 764
 765                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 766
 767                 __asm__ __volatile__("mov %%sp, %0\n\t"
 768                                      "mov %1, %%sp"
 769                                      : "=&r" (orig_sp)
 770                                      : "r" (sp));
 771                 __do_softirq();
 772                 __asm__ __volatile__("mov %0, %%sp"
 773                                      : : "r" (orig_sp));
 774         }
 775
 776         local_irq_restore(flags);
 777 }
 778
 779 #ifdef CONFIG_HOTPLUG_CPU
 780 void fixup_irqs(void)
 781 {
 782         unsigned int irq;
 783
 784         for (irq = 0; irq < NR_IRQS; irq++) {
 785                 unsigned long flags;
 786
 787                 spin_lock_irqsave(&irq_desc[irq].lock, flags);
 788                 if (irq_desc[irq].action &&
 789                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
 790                         if (irq_desc[irq].chip->set_affinity)
 791                                 irq_desc[irq].chip->set_affinity(irq,
 792                                         irq_desc[irq].affinity);
 793                 }
 794                 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
 795         }
 796
 797         tick_ops->disable_irq();
 798 }
 799 #endif
 800
 801 struct sun5_timer {
 802         u64     count0;
 803         u64     limit0;
 804         u64     count1;
 805         u64     limit1;
 806 };
 807
 808 static struct sun5_timer *prom_timers;
 809 static u64 prom_limit0, prom_limit1;
 810
 811 static void map_prom_timers(void)
 812 {
 813         struct device_node *dp;
 814         const unsigned int *addr;
 815
 816         /* PROM timer node hangs out in the top level of device siblings... */
 817         dp = of_find_node_by_path("/");
 818         dp = dp->child;
 819         while (dp) {
 820                 if (!strcmp(dp->name, "counter-timer"))
 821                         break;
 822                 dp = dp->sibling;
 823         }
 824
 825         /* Assume if node is not present, PROM uses different tick mechanism
 826          * which we should not care about.
 827          */
 828         if (!dp) {
 829                 prom_timers = (struct sun5_timer *) 0;
 830                 return;
 831         }
 832
 833         /* If PROM is really using this, it must be mapped by him. */
 834         addr = of_get_property(dp, "address", NULL);
 835         if (!addr) {
 836                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 837                 prom_timers = (struct sun5_timer *) 0;
 838                 return;
 839         }
 840         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 841 }
 842
 843 static void kill_prom_timer(void)
 844 {
 845         if (!prom_timers)
 846                 return;
 847
 848         /* Save them away for later. */
 849         prom_limit0 = prom_timers->limit0;
 850         prom_limit1 = prom_timers->limit1;
 851
 852         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 853          * We turn both off here just to be paranoid.
 854          */
 855         prom_timers->limit0 = 0;
 856         prom_timers->limit1 = 0;
 857
 858         /* Wheee, eat the interrupt packet too... */
 859         __asm__ __volatile__(
 860 "       mov     0x40, %%g2\n"
 861 "       ldxa    [%%g0] %0, %%g1\n"
 862 "       ldxa    [%%g2] %1, %%g1\n"
 863 "       stxa    %%g0, [%%g0] %0\n"
 864 "       membar  #Sync\n"
 865         : /* no outputs */
 866         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 867         : "g1", "g2");
 868 }
 869
 870 void notrace init_irqwork_curcpu(void)
 871 {
 872         int cpu = hard_smp_processor_id();
 873
 874         trap_block[cpu].irq_worklist_pa = 0UL;
 875 }
 876
 877 /* Please be very careful with register_one_mondo() and
 878  * sun4v_register_mondo_queues().
 879  *
 880  * On SMP this gets invoked from the CPU trampoline before
 881  * the cpu has fully taken over the trap table from OBP,
 882  * and it's kernel stack + %g6 thread register state is
 883  * not fully cooked yet.
 884  *
 885  * Therefore you cannot make any OBP calls, not even prom_printf,
 886  * from these two routines.
 887  */
 888 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 889 {
 890         unsigned long num_entries = (qmask + 1) / 64;
 891         unsigned long status;
 892
 893         status = sun4v_cpu_qconf(type, paddr, num_entries);
 894         if (status != HV_EOK) {
 895                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 896                             "err %lu\n", type, paddr, num_entries, status);
 897                 prom_halt();
 898         }
 899 }
 900
 901 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 902 {
 903         struct trap_per_cpu *tb = &trap_block[this_cpu];
 904
 905         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 906                            tb->cpu_mondo_qmask);
 907         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 908                            tb->dev_mondo_qmask);
 909         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 910                            tb->resum_qmask);
 911         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 912                            tb->nonresum_qmask);
 913 }
 914
 915 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
 916 {
 917         unsigned long size = PAGE_ALIGN(qmask + 1);
 918         void *p = __alloc_bootmem(size, size, 0);
 919         if (!p) {
 920                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 921                 prom_halt();
 922         }
 923
 924         *pa_ptr = __pa(p);
 925 }
 926
 927 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
 928 {
 929         unsigned long size = PAGE_ALIGN(qmask + 1);
 930         void *p = __alloc_bootmem(size, size, 0);
 931
 932         if (!p) {
 933                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 934                 prom_halt();
 935         }
 936
 937         *pa_ptr = __pa(p);
 938 }
 939
 940 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 941 {
 942 #ifdef CONFIG_SMP
 943         void *page;
 944
 945         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 946
 947         page = alloc_bootmem_pages(PAGE_SIZE);
 948         if (!page) {
 949                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 950                 prom_halt();
 951         }
 952
 953         tb->cpu_mondo_block_pa = __pa(page);
 954         tb->cpu_list_pa = __pa(page + 64);
 955 #endif
 956 }
 957
 958 /* Allocate mondo and error queues for all possible cpus.  */
 959 static void __init sun4v_init_mondo_queues(void)
 960 {
 961         int cpu;
 962
 963         for_each_possible_cpu(cpu) {
 964                 struct trap_per_cpu *tb = &trap_block[cpu];
 965
 966                 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 967                 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 968                 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
 969                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 970                 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 971                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
 972                                tb->nonresum_qmask);
 973         }
 974 }
 975
 976 static void __init init_send_mondo_info(void)
 977 {
 978         int cpu;
 979
 980         for_each_possible_cpu(cpu) {
 981                 struct trap_per_cpu *tb = &trap_block[cpu];
 982
 983                 init_cpu_send_mondo_info(tb);
 984         }
 985 }
 986
 987 static struct irqaction timer_irq_action = {
 988         .name = "timer",
 989 };
 990
 991 /* Only invoked on boot processor. */
 992 void __init init_IRQ(void)
 993 {
 994         unsigned long size;
 995
 996         map_prom_timers();
 997         kill_prom_timer();
 998
 999         size = sizeof(struct ino_bucket) * NUM_IVECS;
1000         ivector_table = alloc_bootmem(size);
1001         if (!ivector_table) {
1002                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1003                 prom_halt();
1004         }
1005         __flush_dcache_range((unsigned long) ivector_table,
1006                              ((unsigned long) ivector_table) + size);
1007
1008         ivector_table_pa = __pa(ivector_table);
1009
1010         if (tlb_type == hypervisor)
1011                 sun4v_init_mondo_queues();
1012
1013         init_send_mondo_info();
1014
1015         if (tlb_type == hypervisor) {
1016                 /* Load up the boot cpu's entries.  */
1017                 sun4v_register_mondo_queues(hard_smp_processor_id());
1018         }
1019
1020         /* We need to clear any IRQ's pending in the soft interrupt
1021          * registers, a spurious one could be left around from the
1022          * PROM timer which we just disabled.
1023          */
1024         clear_softint(get_softint());
1025
1026         /* Now that ivector table is initialized, it is safe
1027          * to receive IRQ vector traps.  We will normally take
1028          * one or two right now, in case some device PROM used
1029          * to boot us wants to speak to us.  We just ignore them.
1030          */
1031         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1032                              "or        %%g1, %0, %%g1\n\t"
1033                              "wrpr      %%g1, 0x0, %%pstate"
1034                              : /* No outputs */
1035                              : "i" (PSTATE_IE)
1036                              : "g1");
1037
1038         irq_desc[0].action = &timer_irq_action;
1039 }