2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/init.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/string.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
38 #include <asm/iommu.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/machdep.h>
41 #include <asm/abs_addr.h>
42 #include <asm/pSeries_reconfig.h>
43 #include <asm/firmware.h>
45 #include <asm/ppc-pci.h>
48 #include "plpar_wrappers.h"
52 static void tce_build_pSeries(struct iommu_table *tbl, long index,
53 long npages, unsigned long uaddr,
54 enum dma_data_direction direction)
60 proto_tce = TCE_PCI_READ; // Read allowed
62 if (direction != DMA_TO_DEVICE)
63 proto_tce |= TCE_PCI_WRITE;
65 tcep = ((u64 *)tbl->it_base) + index;
68 /* can't move this out since we might cross LMB boundary */
69 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
70 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
72 uaddr += TCE_PAGE_SIZE;
78 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
82 tcep = ((u64 *)tbl->it_base) + index;
88 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
92 tcep = ((u64 *)tbl->it_base) + index;
97 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
98 long npages, unsigned long uaddr,
99 enum dma_data_direction direction)
105 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
106 proto_tce = TCE_PCI_READ;
107 if (direction != DMA_TO_DEVICE)
108 proto_tce |= TCE_PCI_WRITE;
111 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
112 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
114 if (rc && printk_ratelimit()) {
115 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
116 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
117 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
118 printk("\ttce val = 0x%lx\n", tce );
119 show_stack(current, (unsigned long *)__get_SP());
127 static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
129 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
130 long npages, unsigned long uaddr,
131 enum dma_data_direction direction)
140 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
143 tcep = __get_cpu_var(tce_page);
145 /* This is safe to do since interrupts are off when we're called
146 * from iommu_alloc{,_sg}()
149 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
150 /* If allocation fails, fall back to the loop implementation */
152 return tce_build_pSeriesLP(tbl, tcenum, npages,
154 __get_cpu_var(tce_page) = tcep;
157 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
158 proto_tce = TCE_PCI_READ;
159 if (direction != DMA_TO_DEVICE)
160 proto_tce |= TCE_PCI_WRITE;
162 /* We can map max one pageful of TCEs at a time */
165 * Set up the page with TCE data, looping through and setting
168 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
170 for (l = 0; l < limit; l++) {
171 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
175 rc = plpar_tce_put_indirect((u64)tbl->it_index,
177 (u64)virt_to_abs(tcep),
182 } while (npages > 0 && !rc);
184 if (rc && printk_ratelimit()) {
185 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
186 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
187 printk("\tnpages = 0x%lx\n", (u64)npages);
188 printk("\ttce[0] val = 0x%lx\n", tcep[0]);
189 show_stack(current, (unsigned long *)__get_SP());
193 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
198 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
200 if (rc && printk_ratelimit()) {
201 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
202 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
203 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
204 show_stack(current, (unsigned long *)__get_SP());
212 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
216 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
218 if (rc && printk_ratelimit()) {
219 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
220 printk("\trc = %ld\n", rc);
221 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
222 printk("\tnpages = 0x%lx\n", (u64)npages);
223 show_stack(current, (unsigned long *)__get_SP());
227 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
230 unsigned long tce_ret;
232 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
234 if (rc && printk_ratelimit()) {
235 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n",
237 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
238 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
239 show_stack(current, (unsigned long *)__get_SP());
245 static void iommu_table_setparms(struct pci_controller *phb,
246 struct device_node *dn,
247 struct iommu_table *tbl)
249 struct device_node *node;
250 const unsigned long *basep;
253 node = (struct device_node *)phb->arch_data;
255 basep = get_property(node, "linux,tce-base", NULL);
256 sizep = get_property(node, "linux,tce-size", NULL);
257 if (basep == NULL || sizep == NULL) {
258 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
259 "missing tce entries !\n", dn->full_name);
263 tbl->it_base = (unsigned long)__va(*basep);
265 #ifndef CONFIG_CRASH_DUMP
266 memset((void *)tbl->it_base, 0, *sizep);
269 tbl->it_busno = phb->bus->number;
271 /* Units of tce entries */
272 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
274 /* Test if we are going over 2GB of DMA space */
275 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
276 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
277 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
280 phb->dma_window_base_cur += phb->dma_window_size;
282 /* Set the tce table size - measured in entries */
283 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
286 tbl->it_blocksize = 16;
287 tbl->it_type = TCE_PCI;
291 * iommu_table_setparms_lpar
293 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
295 static void iommu_table_setparms_lpar(struct pci_controller *phb,
296 struct device_node *dn,
297 struct iommu_table *tbl,
298 const void *dma_window)
300 unsigned long offset, size;
302 tbl->it_busno = PCI_DN(dn)->bussubno;
303 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
306 tbl->it_blocksize = 16;
307 tbl->it_type = TCE_PCI;
308 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
309 tbl->it_size = size >> IOMMU_PAGE_SHIFT;
312 static void iommu_bus_setup_pSeries(struct pci_bus *bus)
314 struct device_node *dn;
315 struct iommu_table *tbl;
316 struct device_node *isa_dn, *isa_dn_orig;
317 struct device_node *tmp;
321 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
323 dn = pci_bus_to_OF_node(bus);
327 /* This is not a root bus, any setup will be done for the
328 * device-side of the bridge in iommu_dev_setup_pSeries().
333 /* Check if the ISA bus on the system is under
336 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
338 while (isa_dn && isa_dn != dn)
339 isa_dn = isa_dn->parent;
342 of_node_put(isa_dn_orig);
344 /* Count number of direct PCI children of the PHB. */
345 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
348 DBG("Children: %d\n", children);
350 /* Calculate amount of DMA window per slot. Each window must be
351 * a power of two (due to pci_alloc_consistent requirements).
353 * Keep 256MB aside for PHBs with ISA.
357 /* No ISA/IDE - just set window size and return */
358 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
360 while (pci->phb->dma_window_size * children > 0x80000000ul)
361 pci->phb->dma_window_size >>= 1;
362 DBG("No ISA/IDE, window size is 0x%lx\n",
363 pci->phb->dma_window_size);
364 pci->phb->dma_window_base_cur = 0;
369 /* If we have ISA, then we probably have an IDE
370 * controller too. Allocate a 128MB table but
371 * skip the first 128MB to avoid stepping on ISA
374 pci->phb->dma_window_size = 0x8000000ul;
375 pci->phb->dma_window_base_cur = 0x8000000ul;
377 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
380 iommu_table_setparms(pci->phb, dn, tbl);
381 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
383 /* Divide the rest (1.75GB) among the children */
384 pci->phb->dma_window_size = 0x80000000ul;
385 while (pci->phb->dma_window_size * children > 0x70000000ul)
386 pci->phb->dma_window_size >>= 1;
388 DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
393 static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
395 struct iommu_table *tbl;
396 struct device_node *dn, *pdn;
398 const void *dma_window = NULL;
400 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
402 dn = pci_bus_to_OF_node(bus);
404 /* Find nearest ibm,dma-window, walking up the device tree */
405 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
406 dma_window = get_property(pdn, "ibm,dma-window", NULL);
407 if (dma_window != NULL)
411 if (dma_window == NULL) {
412 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
417 if (!ppci->iommu_table) {
418 /* Bussubno hasn't been copied yet.
419 * Do it now because iommu_table_setparms_lpar needs it.
422 ppci->bussubno = bus->number;
424 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
427 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
429 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
433 PCI_DN(dn)->iommu_table = ppci->iommu_table;
437 static void iommu_dev_setup_pSeries(struct pci_dev *dev)
439 struct device_node *dn, *mydn;
440 struct iommu_table *tbl;
442 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, pci_name(dev));
444 mydn = dn = pci_device_to_OF_node(dev);
446 /* If we're the direct child of a root bus, then we need to allocate
447 * an iommu table ourselves. The bus setup code should have setup
448 * the window sizes already.
450 if (!dev->bus->self) {
451 DBG(" --> first child, no bridge. Allocating iommu table.\n");
452 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
453 PCI_DN(dn)->phb->node);
454 iommu_table_setparms(PCI_DN(dn)->phb, dn, tbl);
455 PCI_DN(dn)->iommu_table = iommu_init_table(tbl,
456 PCI_DN(dn)->phb->node);
461 /* If this device is further down the bus tree, search upwards until
462 * an already allocated iommu table is found and use that.
465 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
468 if (dn && PCI_DN(dn)) {
469 PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table;
471 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, pci_name(dev));
475 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
478 struct device_node *np = node;
479 struct pci_dn *pci = PCI_DN(np);
482 case PSERIES_RECONFIG_REMOVE:
483 if (pci && pci->iommu_table &&
484 get_property(np, "ibm,dma-window", NULL))
485 iommu_free_table(np);
494 static struct notifier_block iommu_reconfig_nb = {
495 .notifier_call = iommu_reconfig_notifier,
498 static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
500 struct device_node *pdn, *dn;
501 struct iommu_table *tbl;
502 const void *dma_window = NULL;
505 /* dev setup for LPAR is a little tricky, since the device tree might
506 * contain the dma-window properties per-device and not neccesarily
507 * for the bus. So we need to search upwards in the tree until we
508 * either hit a dma-window property, OR find a parent with a table
511 dn = pci_device_to_OF_node(dev);
513 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s) %s\n",
514 dev, pci_name(dev), dn->full_name);
516 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
518 dma_window = get_property(pdn, "ibm,dma-window", NULL);
523 /* Check for parent == NULL so we don't try to setup the empty EADS
524 * slots on POWER4 machines.
526 if (dma_window == NULL || pdn->parent == NULL) {
527 DBG("No dma window for device, linking to parent\n");
528 PCI_DN(dn)->iommu_table = PCI_DN(pdn)->iommu_table;
531 DBG("Found DMA window, allocating table\n");
535 if (!pci->iommu_table) {
536 /* iommu_table_setparms_lpar needs bussubno. */
537 pci->bussubno = pci->phb->bus->number;
539 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
542 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
544 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
548 PCI_DN(dn)->iommu_table = pci->iommu_table;
551 static void iommu_bus_setup_null(struct pci_bus *b) { }
552 static void iommu_dev_setup_null(struct pci_dev *d) { }
554 /* These are called very early. */
555 void iommu_init_early_pSeries(void)
557 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
558 /* Direct I/O, IOMMU off */
559 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
560 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
561 pci_direct_iommu_init();
566 if (firmware_has_feature(FW_FEATURE_LPAR)) {
567 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
568 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
569 ppc_md.tce_free = tce_freemulti_pSeriesLP;
571 ppc_md.tce_build = tce_build_pSeriesLP;
572 ppc_md.tce_free = tce_free_pSeriesLP;
574 ppc_md.tce_get = tce_get_pSeriesLP;
575 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
576 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
578 ppc_md.tce_build = tce_build_pSeries;
579 ppc_md.tce_free = tce_free_pSeries;
580 ppc_md.tce_get = tce_get_pseries;
581 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
582 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
586 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);