git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78         struct ixgbe_phy_info *phy = &hw->phy;
  79         s32 ret_val = 0;
  80         u16 list_offset, data_offset;
  81
  82         /* Set the bus information prior to PHY identification */
  83         mac->ops.get_bus_info(hw);
  84
  85         /* Call PHY identify routine to get the phy type */
  86         ixgbe_identify_phy_generic(hw);
  87
  88         /* PHY Init */
  89         switch (phy->type) {
  90         case ixgbe_phy_tn:
  91                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  92                 phy->ops.get_firmware_version =
  93                              &ixgbe_get_phy_firmware_version_tnx;
  94                 break;
  95         case ixgbe_phy_nl:
  96                 phy->ops.reset = &ixgbe_reset_phy_nl;
  97
  98                 /* Call SFP+ identify routine to get the SFP+ module type */
  99                 ret_val = phy->ops.identify_sfp(hw);
 100                 if (ret_val != 0)
 101                         goto out;
 102                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 103                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 104                         goto out;
 105                 }
 106
 107                 /* Check to see if SFP+ module is supported */
 108                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 109                                                               &list_offset,
 110                                                               &data_offset);
 111                 if (ret_val != 0) {
 112                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 113                         goto out;
 114                 }
 115                 break;
 116         default:
 117                 break;
 118         }
 119
 120         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 121                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 122                 mac->ops.setup_link_speed =
 123                                      &ixgbe_setup_copper_link_speed_82598;
 124                 mac->ops.get_link_capabilities =
 125                                      &ixgbe_get_copper_link_capabilities_82598;
 126         }
 127
 128         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
 129         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
 130         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
 131         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
 132         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
 133         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 134
 135 out:
 136         return ret_val;
 137 }
 138
 139 /**
 140  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 141  *  @hw: pointer to hardware structure
 142  *  @speed: pointer to link speed
 143  *  @autoneg: boolean auto-negotiation value
 144  *
 145  *  Determines the link capabilities by reading the AUTOC register.
 146  **/
 147 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 148                                              ixgbe_link_speed *speed,
 149                                              bool *autoneg)
 150 {
 151         s32 status = 0;
 152
 153         /*
 154          * Determine link capabilities based on the stored value of AUTOC,
 155          * which represents EEPROM defaults.
 156          */
 157         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 158         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 159                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 160                 *autoneg = false;
 161                 break;
 162
 163         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 164                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 165                 *autoneg = false;
 166                 break;
 167
 168         case IXGBE_AUTOC_LMS_1G_AN:
 169                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 170                 *autoneg = true;
 171                 break;
 172
 173         case IXGBE_AUTOC_LMS_KX4_AN:
 174         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 175                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 176                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 177                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 178                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 179                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 180                 *autoneg = true;
 181                 break;
 182
 183         default:
 184                 status = IXGBE_ERR_LINK_SETUP;
 185                 break;
 186         }
 187
 188         return status;
 189 }
 190
 191 /**
 192  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 193  *  @hw: pointer to hardware structure
 194  *  @speed: pointer to link speed
 195  *  @autoneg: boolean auto-negotiation value
 196  *
 197  *  Determines the link capabilities by reading the AUTOC register.
 198  **/
 199 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 200                                                     ixgbe_link_speed *speed,
 201                                                     bool *autoneg)
 202 {
 203         s32 status = IXGBE_ERR_LINK_SETUP;
 204         u16 speed_ability;
 205
 206         *speed = 0;
 207         *autoneg = true;
 208
 209         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 210                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 211                                       &speed_ability);
 212
 213         if (status == 0) {
 214                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 215                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 216                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 217                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 218         }
 219
 220         return status;
 221 }
 222
 223 /**
 224  *  ixgbe_get_media_type_82598 - Determines media type
 225  *  @hw: pointer to hardware structure
 226  *
 227  *  Returns the media type (fiber, copper, backplane)
 228  **/
 229 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 230 {
 231         enum ixgbe_media_type media_type;
 232
 233         /* Media type for I82598 is based on device ID */
 234         switch (hw->device_id) {
 235         case IXGBE_DEV_ID_82598:
 236         case IXGBE_DEV_ID_82598_BX:
 237                 media_type = ixgbe_media_type_backplane;
 238                 break;
 239         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 240         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 241         case IXGBE_DEV_ID_82598EB_CX4:
 242         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 243         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 244         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 245         case IXGBE_DEV_ID_82598EB_XF_LR:
 246         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 247                 media_type = ixgbe_media_type_fiber;
 248                 break;
 249         case IXGBE_DEV_ID_82598AT:
 250                 media_type = ixgbe_media_type_copper;
 251                 break;
 252         default:
 253                 media_type = ixgbe_media_type_unknown;
 254                 break;
 255         }
 256
 257         return media_type;
 258 }
 259
 260 /**
 261  *  ixgbe_fc_enable_82598 - Enable flow control
 262  *  @hw: pointer to hardware structure
 263  *  @packetbuf_num: packet buffer number (0-7)
 264  *
 265  *  Enable flow control according to the current settings.
 266  **/
 267 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 268 {
 269         s32 ret_val = 0;
 270         u32 fctrl_reg;
 271         u32 rmcs_reg;
 272         u32 reg;
 273
 274         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 275         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 276
 277         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 278         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 279
 280         /*
 281          * The possible values of fc.current_mode are:
 282          * 0: Flow control is completely disabled
 283          * 1: Rx flow control is enabled (we can receive pause frames,
 284          *    but not send pause frames).
 285          * 2:  Tx flow control is enabled (we can send pause frames but
 286          *     we do not support receiving pause frames).
 287          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 288          * other: Invalid.
 289          */
 290         switch (hw->fc.current_mode) {
 291         case ixgbe_fc_none:
 292                 /* Flow control completely disabled by software override. */
 293                 break;
 294         case ixgbe_fc_rx_pause:
 295                 /*
 296                  * Rx Flow control is enabled and Tx Flow control is
 297                  * disabled by software override. Since there really
 298                  * isn't a way to advertise that we are capable of RX
 299                  * Pause ONLY, we will advertise that we support both
 300                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 301                  * disable the adapter's ability to send PAUSE frames.
 302                  */
 303                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 304                 break;
 305         case ixgbe_fc_tx_pause:
 306                 /*
 307                  * Tx Flow control is enabled, and Rx Flow control is
 308                  * disabled by software override.
 309                  */
 310                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 311                 break;
 312         case ixgbe_fc_full:
 313                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 314                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 315                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 316                 break;
 317         default:
 318                 hw_dbg(hw, "Flow control param set incorrectly\n");
 319                 ret_val = -IXGBE_ERR_CONFIG;
 320                 goto out;
 321                 break;
 322         }
 323
 324         /* Enable 802.3x based flow control settings. */
 325         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 326         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 327
 328         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 329         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 330                 if (hw->fc.send_xon) {
 331                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 332                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 333                 } else {
 334                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 335                                         hw->fc.low_water);
 336                 }
 337
 338                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 339                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 340         }
 341
 342         /* Configure pause time (2 TCs per register) */
 343         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 344         if ((packetbuf_num & 1) == 0)
 345                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 346         else
 347                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 348         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 349
 350         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 351
 352 out:
 353         return ret_val;
 354 }
 355
 356 /**
 357  *  ixgbe_setup_fc_82598 - Configure flow control settings
 358  *  @hw: pointer to hardware structure
 359  *  @packetbuf_num: packet buffer number (0-7)
 360  *
 361  *  Configures the flow control settings based on SW configuration.  This
 362  *  function is used for 802.3x flow control configuration only.
 363  **/
 364 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 365 {
 366         s32 ret_val = 0;
 367         ixgbe_link_speed speed;
 368         bool link_up;
 369
 370         /* Validate the packetbuf configuration */
 371         if (packetbuf_num < 0 || packetbuf_num > 7) {
 372                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 373                           " 0-7\n", packetbuf_num);
 374                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 375                 goto out;
 376         }
 377
 378         /*
 379          * Validate the water mark configuration.  Zero water marks are invalid
 380          * because it causes the controller to just blast out fc packets.
 381          */
 382         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 383                 hw_dbg(hw, "Invalid water mark configuration\n");
 384                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 385                 goto out;
 386         }
 387
 388         /*
 389          * Validate the requested mode.  Strict IEEE mode does not allow
 390          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 391          */
 392         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 393                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 394                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 395                 goto out;
 396         }
 397
 398         /*
 399          * 10gig parts do not have a word in the EEPROM to determine the
 400          * default flow control setting, so we explicitly set it to full.
 401          */
 402         if (hw->fc.requested_mode == ixgbe_fc_default)
 403                 hw->fc.requested_mode = ixgbe_fc_full;
 404
 405         /*
 406          * Save off the requested flow control mode for use later.  Depending
 407          * on the link partner's capabilities, we may or may not use this mode.
 408          */
 409
 410         hw->fc.current_mode = hw->fc.requested_mode;
 411
 412         /* Decide whether to use autoneg or not. */
 413         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 414         if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
 415             (speed == IXGBE_LINK_SPEED_1GB_FULL))
 416                 ret_val = ixgbe_fc_autoneg(hw);
 417
 418         if (ret_val)
 419                 goto out;
 420
 421         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 422
 423 out:
 424         return ret_val;
 425 }
 426
 427 /**
 428  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 429  *  @hw: pointer to hardware structure
 430  *
 431  *  Configures link settings based on values in the ixgbe_hw struct.
 432  *  Restarts the link.  Performs autonegotiation if needed.
 433  **/
 434 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 435 {
 436         u32 autoc_reg;
 437         u32 links_reg;
 438         u32 i;
 439         s32 status = 0;
 440
 441         /* Restart link */
 442         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 443         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 444         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 445
 446         /* Only poll for autoneg to complete if specified to do so */
 447         if (hw->phy.autoneg_wait_to_complete) {
 448                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 449                      IXGBE_AUTOC_LMS_KX4_AN ||
 450                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 451                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 452                         links_reg = 0; /* Just in case Autoneg time = 0 */
 453                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 454                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 455                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 456                                         break;
 457                                 msleep(100);
 458                         }
 459                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 460                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 461                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 462                         }
 463                 }
 464         }
 465
 466         /*
 467          * We want to save off the original Flow Control configuration just in
 468          * case we get disconnected and then reconnected into a different hub
 469          * or switch with different Flow Control capabilities.
 470          */
 471         ixgbe_setup_fc_82598(hw, 0);
 472
 473         /* Add delay to filter out noises during initial link setup */
 474         msleep(50);
 475
 476         return status;
 477 }
 478
 479 /**
 480  *  ixgbe_check_mac_link_82598 - Get link/speed status
 481  *  @hw: pointer to hardware structure
 482  *  @speed: pointer to link speed
 483  *  @link_up: true is link is up, false otherwise
 484  *  @link_up_wait_to_complete: bool used to wait for link up or not
 485  *
 486  *  Reads the links register to determine if link is up and the current speed
 487  **/
 488 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 489                                       ixgbe_link_speed *speed, bool *link_up,
 490                                       bool link_up_wait_to_complete)
 491 {
 492         u32 links_reg;
 493         u32 i;
 494         u16 link_reg, adapt_comp_reg;
 495
 496         /*
 497          * SERDES PHY requires us to read link status from register 0xC79F.
 498          * Bit 0 set indicates link is up/ready; clear indicates link down.
 499          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 500          * clear indicates active; set indicates inactive.
 501          */
 502         if (hw->phy.type == ixgbe_phy_nl) {
 503                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 504                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 505                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 506                                      &adapt_comp_reg);
 507                 if (link_up_wait_to_complete) {
 508                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 509                                 if ((link_reg & 1) &&
 510                                     ((adapt_comp_reg & 1) == 0)) {
 511                                         *link_up = true;
 512                                         break;
 513                                 } else {
 514                                         *link_up = false;
 515                                 }
 516                                 msleep(100);
 517                                 hw->phy.ops.read_reg(hw, 0xC79F,
 518                                                      IXGBE_TWINAX_DEV,
 519                                                      &link_reg);
 520                                 hw->phy.ops.read_reg(hw, 0xC00C,
 521                                                      IXGBE_TWINAX_DEV,
 522                                                      &adapt_comp_reg);
 523                         }
 524                 } else {
 525                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 526                                 *link_up = true;
 527                         else
 528                                 *link_up = false;
 529                 }
 530
 531                 if (*link_up == false)
 532                         goto out;
 533         }
 534
 535         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 536         if (link_up_wait_to_complete) {
 537                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 538                         if (links_reg & IXGBE_LINKS_UP) {
 539                                 *link_up = true;
 540                                 break;
 541                         } else {
 542                                 *link_up = false;
 543                         }
 544                         msleep(100);
 545                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 546                 }
 547         } else {
 548                 if (links_reg & IXGBE_LINKS_UP)
 549                         *link_up = true;
 550                 else
 551                         *link_up = false;
 552         }
 553
 554         if (links_reg & IXGBE_LINKS_SPEED)
 555                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 556         else
 557                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 558
 559 out:
 560         return 0;
 561 }
 562
 563
 564 /**
 565  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 566  *  @hw: pointer to hardware structure
 567  *  @speed: new link speed
 568  *  @autoneg: true if auto-negotiation enabled
 569  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 570  *
 571  *  Set the link speed in the AUTOC register and restarts link.
 572  **/
 573 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 574                                            ixgbe_link_speed speed, bool autoneg,
 575                                            bool autoneg_wait_to_complete)
 576 {
 577         s32              status            = 0;
 578         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 579         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 580         u32              autoc             = curr_autoc;
 581         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 582
 583         /* Check to see if speed passed in is supported. */
 584         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 585         speed &= link_capabilities;
 586
 587         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 588                 status = IXGBE_ERR_LINK_SETUP;
 589
 590         /* Set KX4/KX support according to speed requested */
 591         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 592                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 593                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 594                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 595                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 596                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 597                         autoc |= IXGBE_AUTOC_KX_SUPP;
 598                 if (autoc != curr_autoc)
 599                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 600         }
 601
 602         if (status == 0) {
 603                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 604
 605                 /*
 606                  * Setup and restart the link based on the new values in
 607                  * ixgbe_hw This will write the AUTOC register based on the new
 608                  * stored values
 609                  */
 610                 status = ixgbe_setup_mac_link_82598(hw);
 611         }
 612
 613         return status;
 614 }
 615
 616
 617 /**
 618  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 619  *  @hw: pointer to hardware structure
 620  *
 621  *  Configures link settings based on values in the ixgbe_hw struct.
 622  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 623  *  phy and wait for autonegotiate to finish.  Then synchronize the
 624  *  MAC and PHY.
 625  **/
 626 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 627 {
 628         s32 status;
 629
 630         /* Restart autonegotiation on PHY */
 631         status = hw->phy.ops.setup_link(hw);
 632
 633         /* Set up MAC */
 634         ixgbe_setup_mac_link_82598(hw);
 635
 636         return status;
 637 }
 638
 639 /**
 640  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 641  *  @hw: pointer to hardware structure
 642  *  @speed: new link speed
 643  *  @autoneg: true if autonegotiation enabled
 644  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 645  *
 646  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 647  **/
 648 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 649                                                ixgbe_link_speed speed,
 650                                                bool autoneg,
 651                                                bool autoneg_wait_to_complete)
 652 {
 653         s32 status;
 654
 655         /* Setup the PHY according to input speed */
 656         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 657                                               autoneg_wait_to_complete);
 658
 659         /* Set up MAC */
 660         ixgbe_setup_mac_link_82598(hw);
 661
 662         return status;
 663 }
 664
 665 /**
 666  *  ixgbe_reset_hw_82598 - Performs hardware reset
 667  *  @hw: pointer to hardware structure
 668  *
 669  *  Resets the hardware by resetting the transmit and receive units, masks and
 670  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 671  *  reset.
 672  **/
 673 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 674 {
 675         s32 status = 0;
 676         u32 ctrl;
 677         u32 gheccr;
 678         u32 i;
 679         u32 autoc;
 680         u8  analog_val;
 681
 682         /* Call adapter stop to disable tx/rx and clear interrupts */
 683         hw->mac.ops.stop_adapter(hw);
 684
 685         /*
 686          * Power up the Atlas Tx lanes if they are currently powered down.
 687          * Atlas Tx lanes are powered down for MAC loopback tests, but
 688          * they are not automatically restored on reset.
 689          */
 690         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 691         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 692                 /* Enable Tx Atlas so packets can be transmitted again */
 693                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 694                                              &analog_val);
 695                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 696                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 697                                               analog_val);
 698
 699                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 700                                              &analog_val);
 701                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 702                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 703                                               analog_val);
 704
 705                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 706                                              &analog_val);
 707                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 708                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 709                                               analog_val);
 710
 711                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 712                                              &analog_val);
 713                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 714                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 715                                               analog_val);
 716         }
 717
 718         /* Reset PHY */
 719         if (hw->phy.reset_disable == false)
 720                 hw->phy.ops.reset(hw);
 721
 722         /*
 723          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 724          * access and verify no pending requests before reset
 725          */
 726         if (ixgbe_disable_pcie_master(hw) != 0) {
 727                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 728                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 729         }
 730
 731         /*
 732          * Issue global reset to the MAC.  This needs to be a SW reset.
 733          * If link reset is used, it might reset the MAC when mng is using it
 734          */
 735         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 736         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 737         IXGBE_WRITE_FLUSH(hw);
 738
 739         /* Poll for reset bit to self-clear indicating reset is complete */
 740         for (i = 0; i < 10; i++) {
 741                 udelay(1);
 742                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 743                 if (!(ctrl & IXGBE_CTRL_RST))
 744                         break;
 745         }
 746         if (ctrl & IXGBE_CTRL_RST) {
 747                 status = IXGBE_ERR_RESET_FAILED;
 748                 hw_dbg(hw, "Reset polling failed to complete.\n");
 749         }
 750
 751         msleep(50);
 752
 753         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 754         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 755         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 756
 757         /*
 758          * Store the original AUTOC value if it has not been
 759          * stored off yet.  Otherwise restore the stored original
 760          * AUTOC value since the reset operation sets back to deaults.
 761          */
 762         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 763         if (hw->mac.orig_link_settings_stored == false) {
 764                 hw->mac.orig_autoc = autoc;
 765                 hw->mac.orig_link_settings_stored = true;
 766         } else if (autoc != hw->mac.orig_autoc) {
 767                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 768         }
 769
 770         /* Store the permanent mac address */
 771         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 772
 773         return status;
 774 }
 775
 776 /**
 777  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 778  *  @hw: pointer to hardware struct
 779  *  @rar: receive address register index to associate with a VMDq index
 780  *  @vmdq: VMDq set index
 781  **/
 782 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 783 {
 784         u32 rar_high;
 785
 786         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 787         rar_high &= ~IXGBE_RAH_VIND_MASK;
 788         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 789         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 790         return 0;
 791 }
 792
 793 /**
 794  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 795  *  @hw: pointer to hardware struct
 796  *  @rar: receive address register index to associate with a VMDq index
 797  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 798  **/
 799 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 800 {
 801         u32 rar_high;
 802         u32 rar_entries = hw->mac.num_rar_entries;
 803
 804         if (rar < rar_entries) {
 805                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 806                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 807                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 808                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 809                 }
 810         } else {
 811                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 812         }
 813
 814         return 0;
 815 }
 816
 817 /**
 818  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 819  *  @hw: pointer to hardware structure
 820  *  @vlan: VLAN id to write to VLAN filter
 821  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 822  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 823  *
 824  *  Turn on/off specified VLAN in the VLAN filter table.
 825  **/
 826 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 827                                 bool vlan_on)
 828 {
 829         u32 regindex;
 830         u32 bitindex;
 831         u32 bits;
 832         u32 vftabyte;
 833
 834         if (vlan > 4095)
 835                 return IXGBE_ERR_PARAM;
 836
 837         /* Determine 32-bit word position in array */
 838         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 839
 840         /* Determine the location of the (VMD) queue index */
 841         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 842         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 843
 844         /* Set the nibble for VMD queue index */
 845         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 846         bits &= (~(0x0F << bitindex));
 847         bits |= (vind << bitindex);
 848         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 849
 850         /* Determine the location of the bit for this VLAN id */
 851         bitindex = vlan & 0x1F;   /* lower five bits */
 852
 853         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 854         if (vlan_on)
 855                 /* Turn on this VLAN id */
 856                 bits |= (1 << bitindex);
 857         else
 858                 /* Turn off this VLAN id */
 859                 bits &= ~(1 << bitindex);
 860         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 861
 862         return 0;
 863 }
 864
 865 /**
 866  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 867  *  @hw: pointer to hardware structure
 868  *
 869  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 870  **/
 871 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 872 {
 873         u32 offset;
 874         u32 vlanbyte;
 875
 876         for (offset = 0; offset < hw->mac.vft_size; offset++)
 877                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 878
 879         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 880                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 881                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 882                                         0);
 883
 884         return 0;
 885 }
 886
 887 /**
 888  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 889  *  @hw: pointer to hardware structure
 890  *  @reg: analog register to read
 891  *  @val: read value
 892  *
 893  *  Performs read operation to Atlas analog register specified.
 894  **/
 895 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 896 {
 897         u32  atlas_ctl;
 898
 899         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 900                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 901         IXGBE_WRITE_FLUSH(hw);
 902         udelay(10);
 903         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 904         *val = (u8)atlas_ctl;
 905
 906         return 0;
 907 }
 908
 909 /**
 910  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 911  *  @hw: pointer to hardware structure
 912  *  @reg: atlas register to write
 913  *  @val: value to write
 914  *
 915  *  Performs write operation to Atlas analog register specified.
 916  **/
 917 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 918 {
 919         u32  atlas_ctl;
 920
 921         atlas_ctl = (reg << 8) | val;
 922         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 923         IXGBE_WRITE_FLUSH(hw);
 924         udelay(10);
 925
 926         return 0;
 927 }
 928
 929 /**
 930  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 931  *  over I2C interface through an intermediate phy.
 932  *  @hw: pointer to hardware structure
 933  *  @byte_offset: EEPROM byte offset to read
 934  *  @eeprom_data: value read
 935  *
 936  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 937  **/
 938 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 939                                        u8 *eeprom_data)
 940 {
 941         s32 status = 0;
 942         u16 sfp_addr = 0;
 943         u16 sfp_data = 0;
 944         u16 sfp_stat = 0;
 945         u32 i;
 946
 947         if (hw->phy.type == ixgbe_phy_nl) {
 948                 /*
 949                  * phy SDA/SCL registers are at addresses 0xC30A to
 950                  * 0xC30D.  These registers are used to talk to the SFP+
 951                  * module's EEPROM through the SDA/SCL (I2C) interface.
 952                  */
 953                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
 954                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
 955                 hw->phy.ops.write_reg(hw,
 956                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
 957                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 958                                       sfp_addr);
 959
 960                 /* Poll status */
 961                 for (i = 0; i < 100; i++) {
 962                         hw->phy.ops.read_reg(hw,
 963                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
 964                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 965                                              &sfp_stat);
 966                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
 967                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
 968                                 break;
 969                         msleep(10);
 970                 }
 971
 972                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
 973                         hw_dbg(hw, "EEPROM read did not pass.\n");
 974                         status = IXGBE_ERR_SFP_NOT_PRESENT;
 975                         goto out;
 976                 }
 977
 978                 /* Read data */
 979                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
 980                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
 981
 982                 *eeprom_data = (u8)(sfp_data >> 8);
 983         } else {
 984                 status = IXGBE_ERR_PHY;
 985                 goto out;
 986         }
 987
 988 out:
 989         return status;
 990 }
 991
 992 /**
 993  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
 994  *  @hw: pointer to hardware structure
 995  *
 996  *  Determines physical layer capabilities of the current configuration.
 997  **/
 998 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
 999 {
1000         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1001
1002         switch (hw->device_id) {
1003         case IXGBE_DEV_ID_82598:
1004                 /* Default device ID is mezzanine card KX/KX4 */
1005                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1006                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1007                 break;
1008         case IXGBE_DEV_ID_82598_BX:
1009                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1010         case IXGBE_DEV_ID_82598EB_CX4:
1011         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1012                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1013                 break;
1014         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1015                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1016                 break;
1017         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1018         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1019         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1020                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1021                 break;
1022         case IXGBE_DEV_ID_82598EB_XF_LR:
1023                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1024                 break;
1025         case IXGBE_DEV_ID_82598AT:
1026                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1027                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1028                 break;
1029         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1030                 hw->phy.ops.identify_sfp(hw);
1031
1032                 switch (hw->phy.sfp_type) {
1033                 case ixgbe_sfp_type_da_cu:
1034                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1035                         break;
1036                 case ixgbe_sfp_type_sr:
1037                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1038                         break;
1039                 case ixgbe_sfp_type_lr:
1040                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1041                         break;
1042                 default:
1043                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1044                         break;
1045                 }
1046                 break;
1047
1048         default:
1049                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1050                 break;
1051         }
1052
1053         return physical_layer;
1054 }
1055
1056 static struct ixgbe_mac_operations mac_ops_82598 = {
1057         .init_hw                = &ixgbe_init_hw_generic,
1058         .reset_hw               = &ixgbe_reset_hw_82598,
1059         .start_hw               = &ixgbe_start_hw_generic,
1060         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1061         .get_media_type         = &ixgbe_get_media_type_82598,
1062         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1063         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1064         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1065         .stop_adapter           = &ixgbe_stop_adapter_generic,
1066         .get_bus_info           = &ixgbe_get_bus_info_generic,
1067         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1068         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1069         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1070         .setup_link             = &ixgbe_setup_mac_link_82598,
1071         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1072         .check_link             = &ixgbe_check_mac_link_82598,
1073         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1074         .led_on                 = &ixgbe_led_on_generic,
1075         .led_off                = &ixgbe_led_off_generic,
1076         .blink_led_start        = &ixgbe_blink_led_start_generic,
1077         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1078         .set_rar                = &ixgbe_set_rar_generic,
1079         .clear_rar              = &ixgbe_clear_rar_generic,
1080         .set_vmdq               = &ixgbe_set_vmdq_82598,
1081         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1082         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1083         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1084         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1085         .enable_mc              = &ixgbe_enable_mc_generic,
1086         .disable_mc             = &ixgbe_disable_mc_generic,
1087         .clear_vfta             = &ixgbe_clear_vfta_82598,
1088         .set_vfta               = &ixgbe_set_vfta_82598,
1089         .setup_fc               = &ixgbe_setup_fc_82598,
1090 };
1091
1092 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1093         .init_params            = &ixgbe_init_eeprom_params_generic,
1094         .read                   = &ixgbe_read_eeprom_generic,
1095         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1096         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1097 };
1098
1099 static struct ixgbe_phy_operations phy_ops_82598 = {
1100         .identify               = &ixgbe_identify_phy_generic,
1101         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1102         .reset                  = &ixgbe_reset_phy_generic,
1103         .read_reg               = &ixgbe_read_phy_reg_generic,
1104         .write_reg              = &ixgbe_write_phy_reg_generic,
1105         .setup_link             = &ixgbe_setup_phy_link_generic,
1106         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1107         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1108 };
1109
1110 struct ixgbe_info ixgbe_82598_info = {
1111         .mac                    = ixgbe_mac_82598EB,
1112         .get_invariants         = &ixgbe_get_invariants_82598,
1113         .mac_ops                = &mac_ops_82598,
1114         .eeprom_ops             = &eeprom_ops_82598,
1115         .phy_ops                = &phy_ops_82598,
1116 };
1117