git.oblomov.eu Git - linux-2.6/blob - drivers/video/sunxvr500.c

   1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/slab.h>
   9 #include <linux/fb.h>
  10 #include <linux/pci.h>
  11 #include <linux/init.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/prom.h>
  15 #include <asm/of_device.h>
  16
  17 /* XXX This device has a 'dev-comm' property which aparently is
  18  * XXX a pointer into the openfirmware's address space which is
  19  * XXX a shared area the kernel driver can use to keep OBP
  20  * XXX informed about the current resolution setting.  The idea
  21  * XXX is that the kernel can change resolutions, and as long
  22  * XXX as the values in the 'dev-comm' area are accurate then
  23  * XXX OBP can still render text properly to the console.
  24  * XXX
  25  * XXX I'm still working out the layout of this and whether there
  26  * XXX are any signatures we need to look for etc.
  27  */
  28 struct e3d_info {
  29         struct fb_info          *info;
  30         struct pci_dev          *pdev;
  31
  32         spinlock_t              lock;
  33
  34         char __iomem            *fb_base;
  35         unsigned long           fb_base_phys;
  36
  37         unsigned long           fb8_buf_diff;
  38         unsigned long           regs_base_phys;
  39
  40         void __iomem            *ramdac;
  41
  42         struct device_node      *of_node;
  43
  44         unsigned int            width;
  45         unsigned int            height;
  46         unsigned int            depth;
  47         unsigned int            fb_size;
  48
  49         u32                     fb_base_reg;
  50         u32                     fb8_0_off;
  51         u32                     fb8_1_off;
  52
  53         u32                     pseudo_palette[16];
  54 };
  55
  56 static int __devinit e3d_get_props(struct e3d_info *ep)
  57 {
  58         ep->width = of_getintprop_default(ep->of_node, "width", 0);
  59         ep->height = of_getintprop_default(ep->of_node, "height", 0);
  60         ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
  61
  62         if (!ep->width || !ep->height) {
  63                 printk(KERN_ERR "e3d: Critical properties missing for %s\n",
  64                        pci_name(ep->pdev));
  65                 return -EINVAL;
  66         }
  67
  68         return 0;
  69 }
  70
  71 /* My XVR-500 comes up, at 1280x768 and a FB base register value of
  72  * 0x04000000, the following video layout register values:
  73  *
  74  * RAMDAC_VID_WH        0x03ff04ff
  75  * RAMDAC_VID_CFG       0x1a0b0088
  76  * RAMDAC_VID_32FB_0    0x04000000
  77  * RAMDAC_VID_32FB_1    0x04800000
  78  * RAMDAC_VID_8FB_0     0x05000000
  79  * RAMDAC_VID_8FB_1     0x05200000
  80  * RAMDAC_VID_XXXFB     0x05400000
  81  * RAMDAC_VID_YYYFB     0x05c00000
  82  * RAMDAC_VID_ZZZFB     0x05e00000
  83  */
  84 /* Video layout registers */
  85 #define RAMDAC_VID_WH           0x00000070UL /* (height-1)<<16 | (width-1) */
  86 #define RAMDAC_VID_CFG          0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
  87 #define RAMDAC_VID_32FB_0       0x00000078UL /* PCI base 32bpp FB buffer 0 */
  88 #define RAMDAC_VID_32FB_1       0x0000007cUL /* PCI base 32bpp FB buffer 1 */
  89 #define RAMDAC_VID_8FB_0        0x00000080UL /* PCI base 8bpp FB buffer 0 */
  90 #define RAMDAC_VID_8FB_1        0x00000084UL /* PCI base 8bpp FB buffer 1 */
  91 #define RAMDAC_VID_XXXFB        0x00000088UL /* PCI base of XXX FB */
  92 #define RAMDAC_VID_YYYFB        0x0000008cUL /* PCI base of YYY FB */
  93 #define RAMDAC_VID_ZZZFB        0x00000090UL /* PCI base of ZZZ FB */
  94
  95 /* CLUT registers */
  96 #define RAMDAC_INDEX            0x000000bcUL
  97 #define RAMDAC_DATA             0x000000c0UL
  98
  99 static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
 100 {
 101         void __iomem *ramdac = ep->ramdac;
 102         unsigned long flags;
 103
 104         spin_lock_irqsave(&ep->lock, flags);
 105
 106         writel(index, ramdac + RAMDAC_INDEX);
 107         writel(val, ramdac + RAMDAC_DATA);
 108
 109         spin_unlock_irqrestore(&ep->lock, flags);
 110 }
 111
 112 static int e3d_setcolreg(unsigned regno,
 113                          unsigned red, unsigned green, unsigned blue,
 114                          unsigned transp, struct fb_info *info)
 115 {
 116         struct e3d_info *ep = info->par;
 117         u32 red_8, green_8, blue_8;
 118         u32 red_10, green_10, blue_10;
 119         u32 value;
 120
 121         if (regno >= 256)
 122                 return 1;
 123
 124         red_8 = red >> 8;
 125         green_8 = green >> 8;
 126         blue_8 = blue >> 8;
 127
 128         value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);
 129
 130         if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
 131                 ((u32 *)info->pseudo_palette)[regno] = value;
 132
 133
 134         red_10 = red >> 6;
 135         green_10 = green >> 6;
 136         blue_10 = blue >> 6;
 137
 138         value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
 139         e3d_clut_write(ep, regno, value);
 140
 141         return 0;
 142 }
 143
 144 /* XXX This is a bit of a hack.  I can't figure out exactly how the
 145  * XXX two 8bpp areas of the framebuffer work.  I imagine there is
 146  * XXX a WID attribute somewhere else in the framebuffer which tells
 147  * XXX the ramdac which of the two 8bpp framebuffer regions to take
 148  * XXX the pixel from.  So, for now, render into both regions to make
 149  * XXX sure the pixel shows up.
 150  */
 151 static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
 152 {
 153         struct e3d_info *ep = info->par;
 154         unsigned long flags;
 155
 156         spin_lock_irqsave(&ep->lock, flags);
 157         cfb_imageblit(info, image);
 158         info->screen_base += ep->fb8_buf_diff;
 159         cfb_imageblit(info, image);
 160         info->screen_base -= ep->fb8_buf_diff;
 161         spin_unlock_irqrestore(&ep->lock, flags);
 162 }
 163
 164 static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 165 {
 166         struct e3d_info *ep = info->par;
 167         unsigned long flags;
 168
 169         spin_lock_irqsave(&ep->lock, flags);
 170         cfb_fillrect(info, rect);
 171         info->screen_base += ep->fb8_buf_diff;
 172         cfb_fillrect(info, rect);
 173         info->screen_base -= ep->fb8_buf_diff;
 174         spin_unlock_irqrestore(&ep->lock, flags);
 175 }
 176
 177 static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
 178 {
 179         struct e3d_info *ep = info->par;
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ep->lock, flags);
 183         cfb_copyarea(info, area);
 184         info->screen_base += ep->fb8_buf_diff;
 185         cfb_copyarea(info, area);
 186         info->screen_base -= ep->fb8_buf_diff;
 187         spin_unlock_irqrestore(&ep->lock, flags);
 188 }
 189
 190 static struct fb_ops e3d_ops = {
 191         .owner                  = THIS_MODULE,
 192         .fb_setcolreg           = e3d_setcolreg,
 193         .fb_fillrect            = e3d_fillrect,
 194         .fb_copyarea            = e3d_copyarea,
 195         .fb_imageblit           = e3d_imageblit,
 196 };
 197
 198 static int __devinit e3d_set_fbinfo(struct e3d_info *ep)
 199 {
 200         struct fb_info *info = ep->info;
 201         struct fb_var_screeninfo *var = &info->var;
 202
 203         info->flags = FBINFO_DEFAULT;
 204         info->fbops = &e3d_ops;
 205         info->screen_base = ep->fb_base;
 206         info->screen_size = ep->fb_size;
 207
 208         info->pseudo_palette = ep->pseudo_palette;
 209
 210         /* Fill fix common fields */
 211         strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
 212         info->fix.smem_start = ep->fb_base_phys;
 213         info->fix.smem_len = ep->fb_size;
 214         info->fix.type = FB_TYPE_PACKED_PIXELS;
 215         if (ep->depth == 32 || ep->depth == 24)
 216                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 217         else
 218                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 219
 220         var->xres = ep->width;
 221         var->yres = ep->height;
 222         var->xres_virtual = var->xres;
 223         var->yres_virtual = var->yres;
 224         var->bits_per_pixel = ep->depth;
 225
 226         var->red.offset = 8;
 227         var->red.length = 8;
 228         var->green.offset = 16;
 229         var->green.length = 8;
 230         var->blue.offset = 24;
 231         var->blue.length = 8;
 232         var->transp.offset = 0;
 233         var->transp.length = 0;
 234
 235         if (fb_alloc_cmap(&info->cmap, 256, 0)) {
 236                 printk(KERN_ERR "e3d: Cannot allocate color map.\n");
 237                 return -ENOMEM;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int __devinit e3d_pci_register(struct pci_dev *pdev,
 244                                       const struct pci_device_id *ent)
 245 {
 246         struct fb_info *info;
 247         struct e3d_info *ep;
 248         unsigned int line_length;
 249         int err;
 250
 251         err = pci_enable_device(pdev);
 252         if (err < 0) {
 253                 printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
 254                        pci_name(pdev));
 255                 goto err_out;
 256         }
 257
 258         info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
 259         if (!info) {
 260                 printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
 261                 err = -ENOMEM;
 262                 goto err_disable;
 263         }
 264
 265         ep = info->par;
 266         ep->info = info;
 267         ep->pdev = pdev;
 268         spin_lock_init(&ep->lock);
 269         ep->of_node = pci_device_to_OF_node(pdev);
 270         if (!ep->of_node) {
 271                 printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
 272                        pci_name(pdev));
 273                 err = -ENODEV;
 274                 goto err_release_fb;
 275         }
 276
 277         /* Read the PCI base register of the frame buffer, which we
 278          * need in order to interpret the RAMDAC_VID_*FB* values in
 279          * the ramdac correctly.
 280          */
 281         pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
 282                               &ep->fb_base_reg);
 283         ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
 284
 285         ep->regs_base_phys = pci_resource_start (pdev, 1);
 286         err = pci_request_region(pdev, 1, "e3d regs");
 287         if (err < 0) {
 288                 printk("e3d: Cannot request region 1 for %s\n",
 289                        pci_name(pdev));
 290                 goto err_release_fb;
 291         }
 292         ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
 293         if (!ep->ramdac)
 294                 goto err_release_pci1;
 295
 296         ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
 297         ep->fb8_0_off -= ep->fb_base_reg;
 298
 299         ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
 300         ep->fb8_1_off -= ep->fb_base_reg;
 301
 302         ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
 303
 304         ep->fb_base_phys = pci_resource_start (pdev, 0);
 305         ep->fb_base_phys += ep->fb8_0_off;
 306
 307         err = pci_request_region(pdev, 0, "e3d framebuffer");
 308         if (err < 0) {
 309                 printk("e3d: Cannot request region 0 for %s\n",
 310                        pci_name(pdev));
 311                 goto err_unmap_ramdac;
 312         }
 313
 314         err = e3d_get_props(ep);
 315         if (err)
 316                 goto err_release_pci0;
 317
 318         line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
 319         line_length = 1 << line_length;
 320
 321         switch (ep->depth) {
 322         case 8:
 323                 info->fix.line_length = line_length;
 324                 break;
 325         case 16:
 326                 info->fix.line_length = line_length * 2;
 327                 break;
 328         case 24:
 329                 info->fix.line_length = line_length * 3;
 330                 break;
 331         case 32:
 332                 info->fix.line_length = line_length * 4;
 333                 break;
 334         }
 335         ep->fb_size = info->fix.line_length * ep->height;
 336
 337         ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
 338         if (!ep->fb_base)
 339                 goto err_release_pci0;
 340
 341         err = e3d_set_fbinfo(ep);
 342         if (err)
 343                 goto err_unmap_fb;
 344
 345         pci_set_drvdata(pdev, info);
 346
 347         printk("e3d: Found device at %s\n", pci_name(pdev));
 348
 349         err = register_framebuffer(info);
 350         if (err < 0) {
 351                 printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
 352                        pci_name(pdev));
 353                 goto err_unmap_fb;
 354         }
 355
 356         return 0;
 357
 358 err_unmap_fb:
 359         iounmap(ep->fb_base);
 360
 361 err_release_pci0:
 362         pci_release_region(pdev, 0);
 363
 364 err_unmap_ramdac:
 365         iounmap(ep->ramdac);
 366
 367 err_release_pci1:
 368         pci_release_region(pdev, 1);
 369
 370 err_release_fb:
 371         framebuffer_release(info);
 372
 373 err_disable:
 374         pci_disable_device(pdev);
 375
 376 err_out:
 377         return err;
 378 }
 379
 380 static void __devexit e3d_pci_unregister(struct pci_dev *pdev)
 381 {
 382         struct fb_info *info = pci_get_drvdata(pdev);
 383         struct e3d_info *ep = info->par;
 384
 385         unregister_framebuffer(info);
 386
 387         iounmap(ep->ramdac);
 388         iounmap(ep->fb_base);
 389
 390         pci_release_region(pdev, 0);
 391         pci_release_region(pdev, 1);
 392
 393         framebuffer_release(info);
 394
 395         pci_disable_device(pdev);
 396 }
 397
 398 static struct pci_device_id e3d_pci_table[] = {
 399         {       PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0),        },
 400         {       PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2),        },
 401         {       .vendor = PCI_VENDOR_ID_3DLABS,
 402                 .device = PCI_ANY_ID,
 403                 .subvendor = PCI_VENDOR_ID_3DLABS,
 404                 .subdevice = 0x0108,
 405         },
 406         {       .vendor = PCI_VENDOR_ID_3DLABS,
 407                 .device = PCI_ANY_ID,
 408                 .subvendor = PCI_VENDOR_ID_3DLABS,
 409                 .subdevice = 0x0140,
 410         },
 411         {       .vendor = PCI_VENDOR_ID_3DLABS,
 412                 .device = PCI_ANY_ID,
 413                 .subvendor = PCI_VENDOR_ID_3DLABS,
 414                 .subdevice = 0x1024,
 415         },
 416         { 0, }
 417 };
 418
 419 static struct pci_driver e3d_driver = {
 420         .name           = "e3d",
 421         .id_table       = e3d_pci_table,
 422         .probe          = e3d_pci_register,
 423         .remove         = __devexit_p(e3d_pci_unregister),
 424 };
 425
 426 static int __init e3d_init(void)
 427 {
 428         if (fb_get_options("e3d", NULL))
 429                 return -ENODEV;
 430
 431         return pci_register_driver(&e3d_driver);
 432 }
 433
 434 static void __exit e3d_exit(void)
 435 {
 436         pci_unregister_driver(&e3d_driver);
 437 }
 438
 439 module_init(e3d_init);
 440 module_exit(e3d_exit);
 441
 442 MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
 443 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
 444 MODULE_VERSION("1.0");
 445 MODULE_LICENSE("GPL");