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   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit.  Without NAPI, the packet(s) will be handled
  48  *  immediately.  Both methods will start at the last known empty
  49  *  descriptor, and process every subsequent descriptor until there
  50  *  are none left with data (NAPI will stop after a set number of
  51  *  packets to give time to other tasks, but will eventually
  52  *  process all the packets).  The data arrives inside a
  53  *  pre-allocated skb, and so after the skb is passed up to the
  54  *  stack, a new skb must be allocated, and the address field in
  55  *  the buffer descriptor must be updated to indicate this new
  56  *  skb.
  57  *
  58  *  When the kernel requests that a packet be transmitted, the
  59  *  driver starts where it left off last time, and points the
  60  *  descriptor at the buffer which was passed in.  The driver
  61  *  then informs the DMA engine that there are packets ready to
  62  *  be transmitted.  Once the controller is finished transmitting
  63  *  the packet, an interrupt may be triggered (under the same
  64  *  conditions as for reception, but depending on the TXF bit).
  65  *  The driver then cleans up the buffer.
  66  */
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/platform_device.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96
  97 #include "gianfar.h"
  98 #include "gianfar_mii.h"
  99
 100 #define TX_TIMEOUT      (1*HZ)
 101 #define SKB_ALLOC_TIMEOUT 1000000
 102 #undef BRIEF_GFAR_ERRORS
 103 #undef VERBOSE_GFAR_ERRORS
 104
 105 #ifdef CONFIG_GFAR_NAPI
 106 #define RECEIVE(x) netif_receive_skb(x)
 107 #else
 108 #define RECEIVE(x) netif_rx(x)
 109 #endif
 110
 111 const char gfar_driver_name[] = "Gianfar Ethernet";
 112 const char gfar_driver_version[] = "1.3";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_timeout(struct net_device *dev);
 117 static int gfar_close(struct net_device *dev);
 118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
 119 static int gfar_set_mac_address(struct net_device *dev);
 120 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 121 static irqreturn_t gfar_error(int irq, void *dev_id);
 122 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 123 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 124 static void adjust_link(struct net_device *dev);
 125 static void init_registers(struct net_device *dev);
 126 static int init_phy(struct net_device *dev);
 127 static int gfar_probe(struct platform_device *pdev);
 128 static int gfar_remove(struct platform_device *pdev);
 129 static void free_skb_resources(struct gfar_private *priv);
 130 static void gfar_set_multi(struct net_device *dev);
 131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 132 static void gfar_configure_serdes(struct net_device *dev);
 133 extern int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id, int regnum, u16 value);
 134 extern int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum);
 135 #ifdef CONFIG_GFAR_NAPI
 136 static int gfar_poll(struct napi_struct *napi, int budget);
 137 #endif
 138 #ifdef CONFIG_NET_POLL_CONTROLLER
 139 static void gfar_netpoll(struct net_device *dev);
 140 #endif
 141 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 142 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 143 static void gfar_vlan_rx_register(struct net_device *netdev,
 144                                 struct vlan_group *grp);
 145 void gfar_halt(struct net_device *dev);
 146 void gfar_start(struct net_device *dev);
 147 static void gfar_clear_exact_match(struct net_device *dev);
 148 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 149
 150 extern const struct ethtool_ops gfar_ethtool_ops;
 151
 152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 154 MODULE_LICENSE("GPL");
 155
 156 /* Returns 1 if incoming frames use an FCB */
 157 static inline int gfar_uses_fcb(struct gfar_private *priv)
 158 {
 159         return (priv->vlan_enable || priv->rx_csum_enable);
 160 }
 161
 162 /* Set up the ethernet device structure, private data,
 163  * and anything else we need before we start */
 164 static int gfar_probe(struct platform_device *pdev)
 165 {
 166         u32 tempval;
 167         struct net_device *dev = NULL;
 168         struct gfar_private *priv = NULL;
 169         struct gianfar_platform_data *einfo;
 170         struct resource *r;
 171         int idx;
 172         int err = 0;
 173
 174         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 175
 176         if (NULL == einfo) {
 177                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 178                        pdev->id);
 179
 180                 return -ENODEV;
 181         }
 182
 183         /* Create an ethernet device instance */
 184         dev = alloc_etherdev(sizeof (*priv));
 185
 186         if (NULL == dev)
 187                 return -ENOMEM;
 188
 189         priv = netdev_priv(dev);
 190         priv->dev = dev;
 191
 192         /* Set the info in the priv to the current info */
 193         priv->einfo = einfo;
 194
 195         /* fill out IRQ fields */
 196         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 197                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 198                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 199                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 200                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 201                         goto regs_fail;
 202         } else {
 203                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 204                 if (priv->interruptTransmit < 0)
 205                         goto regs_fail;
 206         }
 207
 208         /* get a pointer to the register memory */
 209         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 210         priv->regs = ioremap(r->start, sizeof (struct gfar));
 211
 212         if (NULL == priv->regs) {
 213                 err = -ENOMEM;
 214                 goto regs_fail;
 215         }
 216
 217         spin_lock_init(&priv->txlock);
 218         spin_lock_init(&priv->rxlock);
 219
 220         platform_set_drvdata(pdev, dev);
 221
 222         /* Stop the DMA engine now, in case it was running before */
 223         /* (The firmware could have used it, and left it running). */
 224         /* To do this, we write Graceful Receive Stop and Graceful */
 225         /* Transmit Stop, and then wait until the corresponding bits */
 226         /* in IEVENT indicate the stops have completed. */
 227         tempval = gfar_read(&priv->regs->dmactrl);
 228         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 229         gfar_write(&priv->regs->dmactrl, tempval);
 230
 231         tempval = gfar_read(&priv->regs->dmactrl);
 232         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 233         gfar_write(&priv->regs->dmactrl, tempval);
 234
 235         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 236                 cpu_relax();
 237
 238         /* Reset MAC layer */
 239         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 240
 241         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 242         gfar_write(&priv->regs->maccfg1, tempval);
 243
 244         /* Initialize MACCFG2. */
 245         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 246
 247         /* Initialize ECNTRL */
 248         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 249
 250         /* Copy the station address into the dev structure, */
 251         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 252
 253         /* Set the dev->base_addr to the gfar reg region */
 254         dev->base_addr = (unsigned long) (priv->regs);
 255
 256         SET_NETDEV_DEV(dev, &pdev->dev);
 257
 258         /* Fill in the dev structure */
 259         dev->open = gfar_enet_open;
 260         dev->hard_start_xmit = gfar_start_xmit;
 261         dev->tx_timeout = gfar_timeout;
 262         dev->watchdog_timeo = TX_TIMEOUT;
 263         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 264 #ifdef CONFIG_NET_POLL_CONTROLLER
 265         dev->poll_controller = gfar_netpoll;
 266 #endif
 267         dev->stop = gfar_close;
 268         dev->change_mtu = gfar_change_mtu;
 269         dev->mtu = 1500;
 270         dev->set_multicast_list = gfar_set_multi;
 271
 272         dev->ethtool_ops = &gfar_ethtool_ops;
 273
 274         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 275                 priv->rx_csum_enable = 1;
 276                 dev->features |= NETIF_F_IP_CSUM;
 277         } else
 278                 priv->rx_csum_enable = 0;
 279
 280         priv->vlgrp = NULL;
 281
 282         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 283                 dev->vlan_rx_register = gfar_vlan_rx_register;
 284
 285                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 286
 287                 priv->vlan_enable = 1;
 288         }
 289
 290         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 291                 priv->extended_hash = 1;
 292                 priv->hash_width = 9;
 293
 294                 priv->hash_regs[0] = &priv->regs->igaddr0;
 295                 priv->hash_regs[1] = &priv->regs->igaddr1;
 296                 priv->hash_regs[2] = &priv->regs->igaddr2;
 297                 priv->hash_regs[3] = &priv->regs->igaddr3;
 298                 priv->hash_regs[4] = &priv->regs->igaddr4;
 299                 priv->hash_regs[5] = &priv->regs->igaddr5;
 300                 priv->hash_regs[6] = &priv->regs->igaddr6;
 301                 priv->hash_regs[7] = &priv->regs->igaddr7;
 302                 priv->hash_regs[8] = &priv->regs->gaddr0;
 303                 priv->hash_regs[9] = &priv->regs->gaddr1;
 304                 priv->hash_regs[10] = &priv->regs->gaddr2;
 305                 priv->hash_regs[11] = &priv->regs->gaddr3;
 306                 priv->hash_regs[12] = &priv->regs->gaddr4;
 307                 priv->hash_regs[13] = &priv->regs->gaddr5;
 308                 priv->hash_regs[14] = &priv->regs->gaddr6;
 309                 priv->hash_regs[15] = &priv->regs->gaddr7;
 310
 311         } else {
 312                 priv->extended_hash = 0;
 313                 priv->hash_width = 8;
 314
 315                 priv->hash_regs[0] = &priv->regs->gaddr0;
 316                 priv->hash_regs[1] = &priv->regs->gaddr1;
 317                 priv->hash_regs[2] = &priv->regs->gaddr2;
 318                 priv->hash_regs[3] = &priv->regs->gaddr3;
 319                 priv->hash_regs[4] = &priv->regs->gaddr4;
 320                 priv->hash_regs[5] = &priv->regs->gaddr5;
 321                 priv->hash_regs[6] = &priv->regs->gaddr6;
 322                 priv->hash_regs[7] = &priv->regs->gaddr7;
 323         }
 324
 325         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 326                 priv->padding = DEFAULT_PADDING;
 327         else
 328                 priv->padding = 0;
 329
 330         if (dev->features & NETIF_F_IP_CSUM)
 331                 dev->hard_header_len += GMAC_FCB_LEN;
 332
 333         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 334         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 335         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 336
 337         priv->txcoalescing = DEFAULT_TX_COALESCE;
 338         priv->txcount = DEFAULT_TXCOUNT;
 339         priv->txtime = DEFAULT_TXTIME;
 340         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 341         priv->rxcount = DEFAULT_RXCOUNT;
 342         priv->rxtime = DEFAULT_RXTIME;
 343
 344         /* Enable most messages by default */
 345         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 346
 347         err = register_netdev(dev);
 348
 349         if (err) {
 350                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 351                                 dev->name);
 352                 goto register_fail;
 353         }
 354
 355         /* Create all the sysfs files */
 356         gfar_init_sysfs(dev);
 357
 358         /* Print out the device info */
 359         printk(KERN_INFO DEVICE_NAME, dev->name);
 360         for (idx = 0; idx < 6; idx++)
 361                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
 362         printk("\n");
 363
 364         /* Even more device info helps when determining which kernel */
 365         /* provided which set of benchmarks. */
 366 #ifdef CONFIG_GFAR_NAPI
 367         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 368 #else
 369         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
 370 #endif
 371         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 372                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 373
 374         return 0;
 375
 376 register_fail:
 377         iounmap(priv->regs);
 378 regs_fail:
 379         free_netdev(dev);
 380         return err;
 381 }
 382
 383 static int gfar_remove(struct platform_device *pdev)
 384 {
 385         struct net_device *dev = platform_get_drvdata(pdev);
 386         struct gfar_private *priv = netdev_priv(dev);
 387
 388         platform_set_drvdata(pdev, NULL);
 389
 390         iounmap(priv->regs);
 391         free_netdev(dev);
 392
 393         return 0;
 394 }
 395
 396
 397 /* Reads the controller's registers to determine what interface
 398  * connects it to the PHY.
 399  */
 400 static phy_interface_t gfar_get_interface(struct net_device *dev)
 401 {
 402         struct gfar_private *priv = netdev_priv(dev);
 403         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 404
 405         if (ecntrl & ECNTRL_SGMII_MODE)
 406                 return PHY_INTERFACE_MODE_SGMII;
 407
 408         if (ecntrl & ECNTRL_TBI_MODE) {
 409                 if (ecntrl & ECNTRL_REDUCED_MODE)
 410                         return PHY_INTERFACE_MODE_RTBI;
 411                 else
 412                         return PHY_INTERFACE_MODE_TBI;
 413         }
 414
 415         if (ecntrl & ECNTRL_REDUCED_MODE) {
 416                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 417                         return PHY_INTERFACE_MODE_RMII;
 418                 else {
 419                         phy_interface_t interface = priv->einfo->interface;
 420
 421                         /*
 422                          * This isn't autodetected right now, so it must
 423                          * be set by the device tree or platform code.
 424                          */
 425                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 426                                 return PHY_INTERFACE_MODE_RGMII_ID;
 427
 428                         return PHY_INTERFACE_MODE_RGMII;
 429                 }
 430         }
 431
 432         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 433                 return PHY_INTERFACE_MODE_GMII;
 434
 435         return PHY_INTERFACE_MODE_MII;
 436 }
 437
 438
 439 /* Initializes driver's PHY state, and attaches to the PHY.
 440  * Returns 0 on success.
 441  */
 442 static int init_phy(struct net_device *dev)
 443 {
 444         struct gfar_private *priv = netdev_priv(dev);
 445         uint gigabit_support =
 446                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 447                 SUPPORTED_1000baseT_Full : 0;
 448         struct phy_device *phydev;
 449         char phy_id[BUS_ID_SIZE];
 450         phy_interface_t interface;
 451
 452         priv->oldlink = 0;
 453         priv->oldspeed = 0;
 454         priv->oldduplex = -1;
 455
 456         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 457
 458         interface = gfar_get_interface(dev);
 459
 460         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 461
 462         if (interface == PHY_INTERFACE_MODE_SGMII)
 463                 gfar_configure_serdes(dev);
 464
 465         if (IS_ERR(phydev)) {
 466                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 467                 return PTR_ERR(phydev);
 468         }
 469
 470         /* Remove any features not supported by the controller */
 471         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 472         phydev->advertising = phydev->supported;
 473
 474         priv->phydev = phydev;
 475
 476         return 0;
 477 }
 478
 479 static void gfar_configure_serdes(struct net_device *dev)
 480 {
 481         struct gfar_private *priv = netdev_priv(dev);
 482         struct gfar_mii __iomem *regs =
 483                         (void __iomem *)&priv->regs->gfar_mii_regs;
 484
 485         /* Initialise TBI i/f to communicate with serdes (lynx phy) */
 486
 487         /* Single clk mode, mii mode off(for aerdes communication) */
 488         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
 489
 490         /* Supported pause and full-duplex, no half-duplex */
 491         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
 492                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 493                         ADVERTISE_1000XPSE_ASYM);
 494
 495         /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
 496         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
 497                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 498 }
 499
 500 static void init_registers(struct net_device *dev)
 501 {
 502         struct gfar_private *priv = netdev_priv(dev);
 503
 504         /* Clear IEVENT */
 505         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 506
 507         /* Initialize IMASK */
 508         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 509
 510         /* Init hash registers to zero */
 511         gfar_write(&priv->regs->igaddr0, 0);
 512         gfar_write(&priv->regs->igaddr1, 0);
 513         gfar_write(&priv->regs->igaddr2, 0);
 514         gfar_write(&priv->regs->igaddr3, 0);
 515         gfar_write(&priv->regs->igaddr4, 0);
 516         gfar_write(&priv->regs->igaddr5, 0);
 517         gfar_write(&priv->regs->igaddr6, 0);
 518         gfar_write(&priv->regs->igaddr7, 0);
 519
 520         gfar_write(&priv->regs->gaddr0, 0);
 521         gfar_write(&priv->regs->gaddr1, 0);
 522         gfar_write(&priv->regs->gaddr2, 0);
 523         gfar_write(&priv->regs->gaddr3, 0);
 524         gfar_write(&priv->regs->gaddr4, 0);
 525         gfar_write(&priv->regs->gaddr5, 0);
 526         gfar_write(&priv->regs->gaddr6, 0);
 527         gfar_write(&priv->regs->gaddr7, 0);
 528
 529         /* Zero out the rmon mib registers if it has them */
 530         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 531                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 532
 533                 /* Mask off the CAM interrupts */
 534                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 535                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 536         }
 537
 538         /* Initialize the max receive buffer length */
 539         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 540
 541         /* Initialize the Minimum Frame Length Register */
 542         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 543
 544         /* Assign the TBI an address which won't conflict with the PHYs */
 545         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
 546 }
 547
 548
 549 /* Halt the receive and transmit queues */
 550 void gfar_halt(struct net_device *dev)
 551 {
 552         struct gfar_private *priv = netdev_priv(dev);
 553         struct gfar __iomem *regs = priv->regs;
 554         u32 tempval;
 555
 556         /* Mask all interrupts */
 557         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 558
 559         /* Clear all interrupts */
 560         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 561
 562         /* Stop the DMA, and wait for it to stop */
 563         tempval = gfar_read(&priv->regs->dmactrl);
 564         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 565             != (DMACTRL_GRS | DMACTRL_GTS)) {
 566                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 567                 gfar_write(&priv->regs->dmactrl, tempval);
 568
 569                 while (!(gfar_read(&priv->regs->ievent) &
 570                          (IEVENT_GRSC | IEVENT_GTSC)))
 571                         cpu_relax();
 572         }
 573
 574         /* Disable Rx and Tx */
 575         tempval = gfar_read(&regs->maccfg1);
 576         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 577         gfar_write(&regs->maccfg1, tempval);
 578 }
 579
 580 void stop_gfar(struct net_device *dev)
 581 {
 582         struct gfar_private *priv = netdev_priv(dev);
 583         struct gfar __iomem *regs = priv->regs;
 584         unsigned long flags;
 585
 586         phy_stop(priv->phydev);
 587
 588         /* Lock it down */
 589         spin_lock_irqsave(&priv->txlock, flags);
 590         spin_lock(&priv->rxlock);
 591
 592         gfar_halt(dev);
 593
 594         spin_unlock(&priv->rxlock);
 595         spin_unlock_irqrestore(&priv->txlock, flags);
 596
 597         /* Free the IRQs */
 598         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 599                 free_irq(priv->interruptError, dev);
 600                 free_irq(priv->interruptTransmit, dev);
 601                 free_irq(priv->interruptReceive, dev);
 602         } else {
 603                 free_irq(priv->interruptTransmit, dev);
 604         }
 605
 606         free_skb_resources(priv);
 607
 608         dma_free_coherent(NULL,
 609                         sizeof(struct txbd8)*priv->tx_ring_size
 610                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 611                         priv->tx_bd_base,
 612                         gfar_read(&regs->tbase0));
 613 }
 614
 615 /* If there are any tx skbs or rx skbs still around, free them.
 616  * Then free tx_skbuff and rx_skbuff */
 617 static void free_skb_resources(struct gfar_private *priv)
 618 {
 619         struct rxbd8 *rxbdp;
 620         struct txbd8 *txbdp;
 621         int i;
 622
 623         /* Go through all the buffer descriptors and free their data buffers */
 624         txbdp = priv->tx_bd_base;
 625
 626         for (i = 0; i < priv->tx_ring_size; i++) {
 627
 628                 if (priv->tx_skbuff[i]) {
 629                         dma_unmap_single(NULL, txbdp->bufPtr,
 630                                         txbdp->length,
 631                                         DMA_TO_DEVICE);
 632                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 633                         priv->tx_skbuff[i] = NULL;
 634                 }
 635         }
 636
 637         kfree(priv->tx_skbuff);
 638
 639         rxbdp = priv->rx_bd_base;
 640
 641         /* rx_skbuff is not guaranteed to be allocated, so only
 642          * free it and its contents if it is allocated */
 643         if(priv->rx_skbuff != NULL) {
 644                 for (i = 0; i < priv->rx_ring_size; i++) {
 645                         if (priv->rx_skbuff[i]) {
 646                                 dma_unmap_single(NULL, rxbdp->bufPtr,
 647                                                 priv->rx_buffer_size,
 648                                                 DMA_FROM_DEVICE);
 649
 650                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 651                                 priv->rx_skbuff[i] = NULL;
 652                         }
 653
 654                         rxbdp->status = 0;
 655                         rxbdp->length = 0;
 656                         rxbdp->bufPtr = 0;
 657
 658                         rxbdp++;
 659                 }
 660
 661                 kfree(priv->rx_skbuff);
 662         }
 663 }
 664
 665 void gfar_start(struct net_device *dev)
 666 {
 667         struct gfar_private *priv = netdev_priv(dev);
 668         struct gfar __iomem *regs = priv->regs;
 669         u32 tempval;
 670
 671         /* Enable Rx and Tx in MACCFG1 */
 672         tempval = gfar_read(&regs->maccfg1);
 673         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 674         gfar_write(&regs->maccfg1, tempval);
 675
 676         /* Initialize DMACTRL to have WWR and WOP */
 677         tempval = gfar_read(&priv->regs->dmactrl);
 678         tempval |= DMACTRL_INIT_SETTINGS;
 679         gfar_write(&priv->regs->dmactrl, tempval);
 680
 681         /* Make sure we aren't stopped */
 682         tempval = gfar_read(&priv->regs->dmactrl);
 683         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 684         gfar_write(&priv->regs->dmactrl, tempval);
 685
 686         /* Clear THLT/RHLT, so that the DMA starts polling now */
 687         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 688         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 689
 690         /* Unmask the interrupts we look for */
 691         gfar_write(&regs->imask, IMASK_DEFAULT);
 692 }
 693
 694 /* Bring the controller up and running */
 695 int startup_gfar(struct net_device *dev)
 696 {
 697         struct txbd8 *txbdp;
 698         struct rxbd8 *rxbdp;
 699         dma_addr_t addr;
 700         unsigned long vaddr;
 701         int i;
 702         struct gfar_private *priv = netdev_priv(dev);
 703         struct gfar __iomem *regs = priv->regs;
 704         int err = 0;
 705         u32 rctrl = 0;
 706         u32 attrs = 0;
 707
 708         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 709
 710         /* Allocate memory for the buffer descriptors */
 711         vaddr = (unsigned long) dma_alloc_coherent(NULL,
 712                         sizeof (struct txbd8) * priv->tx_ring_size +
 713                         sizeof (struct rxbd8) * priv->rx_ring_size,
 714                         &addr, GFP_KERNEL);
 715
 716         if (vaddr == 0) {
 717                 if (netif_msg_ifup(priv))
 718                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 719                                         dev->name);
 720                 return -ENOMEM;
 721         }
 722
 723         priv->tx_bd_base = (struct txbd8 *) vaddr;
 724
 725         /* enet DMA only understands physical addresses */
 726         gfar_write(&regs->tbase0, addr);
 727
 728         /* Start the rx descriptor ring where the tx ring leaves off */
 729         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 730         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 731         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 732         gfar_write(&regs->rbase0, addr);
 733
 734         /* Setup the skbuff rings */
 735         priv->tx_skbuff =
 736             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 737                                         priv->tx_ring_size, GFP_KERNEL);
 738
 739         if (NULL == priv->tx_skbuff) {
 740                 if (netif_msg_ifup(priv))
 741                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 742                                         dev->name);
 743                 err = -ENOMEM;
 744                 goto tx_skb_fail;
 745         }
 746
 747         for (i = 0; i < priv->tx_ring_size; i++)
 748                 priv->tx_skbuff[i] = NULL;
 749
 750         priv->rx_skbuff =
 751             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 752                                         priv->rx_ring_size, GFP_KERNEL);
 753
 754         if (NULL == priv->rx_skbuff) {
 755                 if (netif_msg_ifup(priv))
 756                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 757                                         dev->name);
 758                 err = -ENOMEM;
 759                 goto rx_skb_fail;
 760         }
 761
 762         for (i = 0; i < priv->rx_ring_size; i++)
 763                 priv->rx_skbuff[i] = NULL;
 764
 765         /* Initialize some variables in our dev structure */
 766         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 767         priv->cur_rx = priv->rx_bd_base;
 768         priv->skb_curtx = priv->skb_dirtytx = 0;
 769         priv->skb_currx = 0;
 770
 771         /* Initialize Transmit Descriptor Ring */
 772         txbdp = priv->tx_bd_base;
 773         for (i = 0; i < priv->tx_ring_size; i++) {
 774                 txbdp->status = 0;
 775                 txbdp->length = 0;
 776                 txbdp->bufPtr = 0;
 777                 txbdp++;
 778         }
 779
 780         /* Set the last descriptor in the ring to indicate wrap */
 781         txbdp--;
 782         txbdp->status |= TXBD_WRAP;
 783
 784         rxbdp = priv->rx_bd_base;
 785         for (i = 0; i < priv->rx_ring_size; i++) {
 786                 struct sk_buff *skb = NULL;
 787
 788                 rxbdp->status = 0;
 789
 790                 skb = gfar_new_skb(dev, rxbdp);
 791
 792                 priv->rx_skbuff[i] = skb;
 793
 794                 rxbdp++;
 795         }
 796
 797         /* Set the last descriptor in the ring to wrap */
 798         rxbdp--;
 799         rxbdp->status |= RXBD_WRAP;
 800
 801         /* If the device has multiple interrupts, register for
 802          * them.  Otherwise, only register for the one */
 803         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 804                 /* Install our interrupt handlers for Error,
 805                  * Transmit, and Receive */
 806                 if (request_irq(priv->interruptError, gfar_error,
 807                                 0, "enet_error", dev) < 0) {
 808                         if (netif_msg_intr(priv))
 809                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 810                                         dev->name, priv->interruptError);
 811
 812                         err = -1;
 813                         goto err_irq_fail;
 814                 }
 815
 816                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 817                                 0, "enet_tx", dev) < 0) {
 818                         if (netif_msg_intr(priv))
 819                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 820                                         dev->name, priv->interruptTransmit);
 821
 822                         err = -1;
 823
 824                         goto tx_irq_fail;
 825                 }
 826
 827                 if (request_irq(priv->interruptReceive, gfar_receive,
 828                                 0, "enet_rx", dev) < 0) {
 829                         if (netif_msg_intr(priv))
 830                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 831                                                 dev->name, priv->interruptReceive);
 832
 833                         err = -1;
 834                         goto rx_irq_fail;
 835                 }
 836         } else {
 837                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 838                                 0, "gfar_interrupt", dev) < 0) {
 839                         if (netif_msg_intr(priv))
 840                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 841                                         dev->name, priv->interruptError);
 842
 843                         err = -1;
 844                         goto err_irq_fail;
 845                 }
 846         }
 847
 848         phy_start(priv->phydev);
 849
 850         /* Configure the coalescing support */
 851         if (priv->txcoalescing)
 852                 gfar_write(&regs->txic,
 853                            mk_ic_value(priv->txcount, priv->txtime));
 854         else
 855                 gfar_write(&regs->txic, 0);
 856
 857         if (priv->rxcoalescing)
 858                 gfar_write(&regs->rxic,
 859                            mk_ic_value(priv->rxcount, priv->rxtime));
 860         else
 861                 gfar_write(&regs->rxic, 0);
 862
 863         if (priv->rx_csum_enable)
 864                 rctrl |= RCTRL_CHECKSUMMING;
 865
 866         if (priv->extended_hash) {
 867                 rctrl |= RCTRL_EXTHASH;
 868
 869                 gfar_clear_exact_match(dev);
 870                 rctrl |= RCTRL_EMEN;
 871         }
 872
 873         if (priv->vlan_enable)
 874                 rctrl |= RCTRL_VLAN;
 875
 876         if (priv->padding) {
 877                 rctrl &= ~RCTRL_PAL_MASK;
 878                 rctrl |= RCTRL_PADDING(priv->padding);
 879         }
 880
 881         /* Init rctrl based on our settings */
 882         gfar_write(&priv->regs->rctrl, rctrl);
 883
 884         if (dev->features & NETIF_F_IP_CSUM)
 885                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 886
 887         /* Set the extraction length and index */
 888         attrs = ATTRELI_EL(priv->rx_stash_size) |
 889                 ATTRELI_EI(priv->rx_stash_index);
 890
 891         gfar_write(&priv->regs->attreli, attrs);
 892
 893         /* Start with defaults, and add stashing or locking
 894          * depending on the approprate variables */
 895         attrs = ATTR_INIT_SETTINGS;
 896
 897         if (priv->bd_stash_en)
 898                 attrs |= ATTR_BDSTASH;
 899
 900         if (priv->rx_stash_size != 0)
 901                 attrs |= ATTR_BUFSTASH;
 902
 903         gfar_write(&priv->regs->attr, attrs);
 904
 905         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
 906         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
 907         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 908
 909         /* Start the controller */
 910         gfar_start(dev);
 911
 912         return 0;
 913
 914 rx_irq_fail:
 915         free_irq(priv->interruptTransmit, dev);
 916 tx_irq_fail:
 917         free_irq(priv->interruptError, dev);
 918 err_irq_fail:
 919 rx_skb_fail:
 920         free_skb_resources(priv);
 921 tx_skb_fail:
 922         dma_free_coherent(NULL,
 923                         sizeof(struct txbd8)*priv->tx_ring_size
 924                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 925                         priv->tx_bd_base,
 926                         gfar_read(&regs->tbase0));
 927
 928         return err;
 929 }
 930
 931 /* Called when something needs to use the ethernet device */
 932 /* Returns 0 for success. */
 933 static int gfar_enet_open(struct net_device *dev)
 934 {
 935         int err;
 936
 937         napi_enable(&priv->napi);
 938
 939         /* Initialize a bunch of registers */
 940         init_registers(dev);
 941
 942         gfar_set_mac_address(dev);
 943
 944         err = init_phy(dev);
 945
 946         if(err) {
 947                 napi_disable(&priv->napi);
 948                 return err;
 949         }
 950
 951         err = startup_gfar(dev);
 952         if (err)
 953                 napi_disable(&priv->napi);
 954
 955         netif_start_queue(dev);
 956
 957         return err;
 958 }
 959
 960 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
 961 {
 962         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
 963
 964         memset(fcb, 0, GMAC_FCB_LEN);
 965
 966         return fcb;
 967 }
 968
 969 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 970 {
 971         u8 flags = 0;
 972
 973         /* If we're here, it's a IP packet with a TCP or UDP
 974          * payload.  We set it to checksum, using a pseudo-header
 975          * we provide
 976          */
 977         flags = TXFCB_DEFAULT;
 978
 979         /* Tell the controller what the protocol is */
 980         /* And provide the already calculated phcs */
 981         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
 982                 flags |= TXFCB_UDP;
 983                 fcb->phcs = udp_hdr(skb)->check;
 984         } else
 985                 fcb->phcs = tcp_hdr(skb)->check;
 986
 987         /* l3os is the distance between the start of the
 988          * frame (skb->data) and the start of the IP hdr.
 989          * l4os is the distance between the start of the
 990          * l3 hdr and the l4 hdr */
 991         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
 992         fcb->l4os = skb_network_header_len(skb);
 993
 994         fcb->flags = flags;
 995 }
 996
 997 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
 998 {
 999         fcb->flags |= TXFCB_VLN;
1000         fcb->vlctl = vlan_tx_tag_get(skb);
1001 }
1002
1003 /* This is called by the kernel when a frame is ready for transmission. */
1004 /* It is pointed to by the dev->hard_start_xmit function pointer */
1005 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1006 {
1007         struct gfar_private *priv = netdev_priv(dev);
1008         struct txfcb *fcb = NULL;
1009         struct txbd8 *txbdp;
1010         u16 status;
1011         unsigned long flags;
1012
1013         /* Update transmit stats */
1014         dev->stats.tx_bytes += skb->len;
1015
1016         /* Lock priv now */
1017         spin_lock_irqsave(&priv->txlock, flags);
1018
1019         /* Point at the first free tx descriptor */
1020         txbdp = priv->cur_tx;
1021
1022         /* Clear all but the WRAP status flags */
1023         status = txbdp->status & TXBD_WRAP;
1024
1025         /* Set up checksumming */
1026         if (likely((dev->features & NETIF_F_IP_CSUM)
1027                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1028                 fcb = gfar_add_fcb(skb, txbdp);
1029                 status |= TXBD_TOE;
1030                 gfar_tx_checksum(skb, fcb);
1031         }
1032
1033         if (priv->vlan_enable &&
1034                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1035                 if (unlikely(NULL == fcb)) {
1036                         fcb = gfar_add_fcb(skb, txbdp);
1037                         status |= TXBD_TOE;
1038                 }
1039
1040                 gfar_tx_vlan(skb, fcb);
1041         }
1042
1043         /* Set buffer length and pointer */
1044         txbdp->length = skb->len;
1045         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1046                         skb->len, DMA_TO_DEVICE);
1047
1048         /* Save the skb pointer so we can free it later */
1049         priv->tx_skbuff[priv->skb_curtx] = skb;
1050
1051         /* Update the current skb pointer (wrapping if this was the last) */
1052         priv->skb_curtx =
1053             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1054
1055         /* Flag the BD as interrupt-causing */
1056         status |= TXBD_INTERRUPT;
1057
1058         /* Flag the BD as ready to go, last in frame, and  */
1059         /* in need of CRC */
1060         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1061
1062         dev->trans_start = jiffies;
1063
1064         /* The powerpc-specific eieio() is used, as wmb() has too strong
1065          * semantics (it requires synchronization between cacheable and
1066          * uncacheable mappings, which eieio doesn't provide and which we
1067          * don't need), thus requiring a more expensive sync instruction.  At
1068          * some point, the set of architecture-independent barrier functions
1069          * should be expanded to include weaker barriers.
1070          */
1071
1072         eieio();
1073         txbdp->status = status;
1074
1075         /* If this was the last BD in the ring, the next one */
1076         /* is at the beginning of the ring */
1077         if (txbdp->status & TXBD_WRAP)
1078                 txbdp = priv->tx_bd_base;
1079         else
1080                 txbdp++;
1081
1082         /* If the next BD still needs to be cleaned up, then the bds
1083            are full.  We need to tell the kernel to stop sending us stuff. */
1084         if (txbdp == priv->dirty_tx) {
1085                 netif_stop_queue(dev);
1086
1087                 dev->stats.tx_fifo_errors++;
1088         }
1089
1090         /* Update the current txbd to the next one */
1091         priv->cur_tx = txbdp;
1092
1093         /* Tell the DMA to go go go */
1094         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1095
1096         /* Unlock priv */
1097         spin_unlock_irqrestore(&priv->txlock, flags);
1098
1099         return 0;
1100 }
1101
1102 /* Stops the kernel queue, and halts the controller */
1103 static int gfar_close(struct net_device *dev)
1104 {
1105         struct gfar_private *priv = netdev_priv(dev);
1106
1107         napi_disable(&priv->napi);
1108
1109         stop_gfar(dev);
1110
1111         /* Disconnect from the PHY */
1112         phy_disconnect(priv->phydev);
1113         priv->phydev = NULL;
1114
1115         netif_stop_queue(dev);
1116
1117         return 0;
1118 }
1119
1120 /* Changes the mac address if the controller is not running. */
1121 int gfar_set_mac_address(struct net_device *dev)
1122 {
1123         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1124
1125         return 0;
1126 }
1127
1128
1129 /* Enables and disables VLAN insertion/extraction */
1130 static void gfar_vlan_rx_register(struct net_device *dev,
1131                 struct vlan_group *grp)
1132 {
1133         struct gfar_private *priv = netdev_priv(dev);
1134         unsigned long flags;
1135         u32 tempval;
1136
1137         spin_lock_irqsave(&priv->rxlock, flags);
1138
1139         priv->vlgrp = grp;
1140
1141         if (grp) {
1142                 /* Enable VLAN tag insertion */
1143                 tempval = gfar_read(&priv->regs->tctrl);
1144                 tempval |= TCTRL_VLINS;
1145
1146                 gfar_write(&priv->regs->tctrl, tempval);
1147
1148                 /* Enable VLAN tag extraction */
1149                 tempval = gfar_read(&priv->regs->rctrl);
1150                 tempval |= RCTRL_VLEX;
1151                 gfar_write(&priv->regs->rctrl, tempval);
1152         } else {
1153                 /* Disable VLAN tag insertion */
1154                 tempval = gfar_read(&priv->regs->tctrl);
1155                 tempval &= ~TCTRL_VLINS;
1156                 gfar_write(&priv->regs->tctrl, tempval);
1157
1158                 /* Disable VLAN tag extraction */
1159                 tempval = gfar_read(&priv->regs->rctrl);
1160                 tempval &= ~RCTRL_VLEX;
1161                 gfar_write(&priv->regs->rctrl, tempval);
1162         }
1163
1164         spin_unlock_irqrestore(&priv->rxlock, flags);
1165 }
1166
1167 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1168 {
1169         int tempsize, tempval;
1170         struct gfar_private *priv = netdev_priv(dev);
1171         int oldsize = priv->rx_buffer_size;
1172         int frame_size = new_mtu + ETH_HLEN;
1173
1174         if (priv->vlan_enable)
1175                 frame_size += VLAN_ETH_HLEN;
1176
1177         if (gfar_uses_fcb(priv))
1178                 frame_size += GMAC_FCB_LEN;
1179
1180         frame_size += priv->padding;
1181
1182         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1183                 if (netif_msg_drv(priv))
1184                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1185                                         dev->name);
1186                 return -EINVAL;
1187         }
1188
1189         tempsize =
1190             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1191             INCREMENTAL_BUFFER_SIZE;
1192
1193         /* Only stop and start the controller if it isn't already
1194          * stopped, and we changed something */
1195         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1196                 stop_gfar(dev);
1197
1198         priv->rx_buffer_size = tempsize;
1199
1200         dev->mtu = new_mtu;
1201
1202         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1203         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1204
1205         /* If the mtu is larger than the max size for standard
1206          * ethernet frames (ie, a jumbo frame), then set maccfg2
1207          * to allow huge frames, and to check the length */
1208         tempval = gfar_read(&priv->regs->maccfg2);
1209
1210         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1211                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1212         else
1213                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1214
1215         gfar_write(&priv->regs->maccfg2, tempval);
1216
1217         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1218                 startup_gfar(dev);
1219
1220         return 0;
1221 }
1222
1223 /* gfar_timeout gets called when a packet has not been
1224  * transmitted after a set amount of time.
1225  * For now, assume that clearing out all the structures, and
1226  * starting over will fix the problem. */
1227 static void gfar_timeout(struct net_device *dev)
1228 {
1229         struct gfar_private *priv = netdev_priv(dev);
1230
1231         dev->stats.tx_errors++;
1232
1233         if (dev->flags & IFF_UP) {
1234                 stop_gfar(dev);
1235                 startup_gfar(dev);
1236         }
1237
1238         netif_schedule(dev);
1239 }
1240
1241 /* Interrupt Handler for Transmit complete */
1242 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1243 {
1244         struct net_device *dev = (struct net_device *) dev_id;
1245         struct gfar_private *priv = netdev_priv(dev);
1246         struct txbd8 *bdp;
1247
1248         /* Clear IEVENT */
1249         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1250
1251         /* Lock priv */
1252         spin_lock(&priv->txlock);
1253         bdp = priv->dirty_tx;
1254         while ((bdp->status & TXBD_READY) == 0) {
1255                 /* If dirty_tx and cur_tx are the same, then either the */
1256                 /* ring is empty or full now (it could only be full in the beginning, */
1257                 /* obviously).  If it is empty, we are done. */
1258                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1259                         break;
1260
1261                 dev->stats.tx_packets++;
1262
1263                 /* Deferred means some collisions occurred during transmit, */
1264                 /* but we eventually sent the packet. */
1265                 if (bdp->status & TXBD_DEF)
1266                         dev->stats.collisions++;
1267
1268                 /* Free the sk buffer associated with this TxBD */
1269                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1270                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1271                 priv->skb_dirtytx =
1272                     (priv->skb_dirtytx +
1273                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1274
1275                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1276                 if (bdp->status & TXBD_WRAP)
1277                         bdp = priv->tx_bd_base;
1278                 else
1279                         bdp++;
1280
1281                 /* Move dirty_tx to be the next bd */
1282                 priv->dirty_tx = bdp;
1283
1284                 /* We freed a buffer, so now we can restart transmission */
1285                 if (netif_queue_stopped(dev))
1286                         netif_wake_queue(dev);
1287         } /* while ((bdp->status & TXBD_READY) == 0) */
1288
1289         /* If we are coalescing the interrupts, reset the timer */
1290         /* Otherwise, clear it */
1291         if (priv->txcoalescing)
1292                 gfar_write(&priv->regs->txic,
1293                            mk_ic_value(priv->txcount, priv->txtime));
1294         else
1295                 gfar_write(&priv->regs->txic, 0);
1296
1297         spin_unlock(&priv->txlock);
1298
1299         return IRQ_HANDLED;
1300 }
1301
1302 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1303 {
1304         unsigned int alignamount;
1305         struct gfar_private *priv = netdev_priv(dev);
1306         struct sk_buff *skb = NULL;
1307         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1308
1309         /* We have to allocate the skb, so keep trying till we succeed */
1310         while ((!skb) && timeout--)
1311                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1312
1313         if (NULL == skb)
1314                 return NULL;
1315
1316         alignamount = RXBUF_ALIGNMENT -
1317                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1318
1319         /* We need the data buffer to be aligned properly.  We will reserve
1320          * as many bytes as needed to align the data properly
1321          */
1322         skb_reserve(skb, alignamount);
1323
1324         bdp->bufPtr = dma_map_single(NULL, skb->data,
1325                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1326
1327         bdp->length = 0;
1328
1329         /* Mark the buffer empty */
1330         eieio();
1331         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1332
1333         return skb;
1334 }
1335
1336 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1337 {
1338         struct net_device_stats *stats = &dev->stats;
1339         struct gfar_extra_stats *estats = &priv->extra_stats;
1340
1341         /* If the packet was truncated, none of the other errors
1342          * matter */
1343         if (status & RXBD_TRUNCATED) {
1344                 stats->rx_length_errors++;
1345
1346                 estats->rx_trunc++;
1347
1348                 return;
1349         }
1350         /* Count the errors, if there were any */
1351         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1352                 stats->rx_length_errors++;
1353
1354                 if (status & RXBD_LARGE)
1355                         estats->rx_large++;
1356                 else
1357                         estats->rx_short++;
1358         }
1359         if (status & RXBD_NONOCTET) {
1360                 stats->rx_frame_errors++;
1361                 estats->rx_nonoctet++;
1362         }
1363         if (status & RXBD_CRCERR) {
1364                 estats->rx_crcerr++;
1365                 stats->rx_crc_errors++;
1366         }
1367         if (status & RXBD_OVERRUN) {
1368                 estats->rx_overrun++;
1369                 stats->rx_crc_errors++;
1370         }
1371 }
1372
1373 irqreturn_t gfar_receive(int irq, void *dev_id)
1374 {
1375         struct net_device *dev = (struct net_device *) dev_id;
1376         struct gfar_private *priv = netdev_priv(dev);
1377 #ifdef CONFIG_GFAR_NAPI
1378         u32 tempval;
1379 #else
1380         unsigned long flags;
1381 #endif
1382
1383         /* Clear IEVENT, so rx interrupt isn't called again
1384          * because of this interrupt */
1385         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1386
1387         /* support NAPI */
1388 #ifdef CONFIG_GFAR_NAPI
1389         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1390                 tempval = gfar_read(&priv->regs->imask);
1391                 tempval &= IMASK_RX_DISABLED;
1392                 gfar_write(&priv->regs->imask, tempval);
1393
1394                 __netif_rx_schedule(dev, &priv->napi);
1395         } else {
1396                 if (netif_msg_rx_err(priv))
1397                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1398                                 dev->name, gfar_read(&priv->regs->ievent),
1399                                 gfar_read(&priv->regs->imask));
1400         }
1401 #else
1402
1403         spin_lock_irqsave(&priv->rxlock, flags);
1404         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1405
1406         /* If we are coalescing interrupts, update the timer */
1407         /* Otherwise, clear it */
1408         if (priv->rxcoalescing)
1409                 gfar_write(&priv->regs->rxic,
1410                            mk_ic_value(priv->rxcount, priv->rxtime));
1411         else
1412                 gfar_write(&priv->regs->rxic, 0);
1413
1414         spin_unlock_irqrestore(&priv->rxlock, flags);
1415 #endif
1416
1417         return IRQ_HANDLED;
1418 }
1419
1420 static inline int gfar_rx_vlan(struct sk_buff *skb,
1421                 struct vlan_group *vlgrp, unsigned short vlctl)
1422 {
1423 #ifdef CONFIG_GFAR_NAPI
1424         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1425 #else
1426         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1427 #endif
1428 }
1429
1430 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1431 {
1432         /* If valid headers were found, and valid sums
1433          * were verified, then we tell the kernel that no
1434          * checksumming is necessary.  Otherwise, it is */
1435         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1436                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1437         else
1438                 skb->ip_summed = CHECKSUM_NONE;
1439 }
1440
1441
1442 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1443 {
1444         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1445
1446         /* Remove the FCB from the skb */
1447         skb_pull(skb, GMAC_FCB_LEN);
1448
1449         return fcb;
1450 }
1451
1452 /* gfar_process_frame() -- handle one incoming packet if skb
1453  * isn't NULL.  */
1454 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1455                 int length)
1456 {
1457         struct gfar_private *priv = netdev_priv(dev);
1458         struct rxfcb *fcb = NULL;
1459
1460         if (NULL == skb) {
1461                 if (netif_msg_rx_err(priv))
1462                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1463                 dev->stats.rx_dropped++;
1464                 priv->extra_stats.rx_skbmissing++;
1465         } else {
1466                 int ret;
1467
1468                 /* Prep the skb for the packet */
1469                 skb_put(skb, length);
1470
1471                 /* Grab the FCB if there is one */
1472                 if (gfar_uses_fcb(priv))
1473                         fcb = gfar_get_fcb(skb);
1474
1475                 /* Remove the padded bytes, if there are any */
1476                 if (priv->padding)
1477                         skb_pull(skb, priv->padding);
1478
1479                 if (priv->rx_csum_enable)
1480                         gfar_rx_checksum(skb, fcb);
1481
1482                 /* Tell the skb what kind of packet this is */
1483                 skb->protocol = eth_type_trans(skb, dev);
1484
1485                 /* Send the packet up the stack */
1486                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1487                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1488                 else
1489                         ret = RECEIVE(skb);
1490
1491                 if (NET_RX_DROP == ret)
1492                         priv->extra_stats.kernel_dropped++;
1493         }
1494
1495         return 0;
1496 }
1497
1498 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1499  *   until the budget/quota has been reached. Returns the number
1500  *   of frames handled
1501  */
1502 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1503 {
1504         struct rxbd8 *bdp;
1505         struct sk_buff *skb;
1506         u16 pkt_len;
1507         int howmany = 0;
1508         struct gfar_private *priv = netdev_priv(dev);
1509
1510         /* Get the first full descriptor */
1511         bdp = priv->cur_rx;
1512
1513         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1514                 rmb();
1515                 skb = priv->rx_skbuff[priv->skb_currx];
1516
1517                 if (!(bdp->status &
1518                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1519                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1520                         /* Increment the number of packets */
1521                         dev->stats.rx_packets++;
1522                         howmany++;
1523
1524                         /* Remove the FCS from the packet length */
1525                         pkt_len = bdp->length - 4;
1526
1527                         gfar_process_frame(dev, skb, pkt_len);
1528
1529                         dev->stats.rx_bytes += pkt_len;
1530                 } else {
1531                         count_errors(bdp->status, priv);
1532
1533                         if (skb)
1534                                 dev_kfree_skb_any(skb);
1535
1536                         priv->rx_skbuff[priv->skb_currx] = NULL;
1537                 }
1538
1539                 dev->last_rx = jiffies;
1540
1541                 /* Clear the status flags for this buffer */
1542                 bdp->status &= ~RXBD_STATS;
1543
1544                 /* Add another skb for the future */
1545                 skb = gfar_new_skb(dev, bdp);
1546                 priv->rx_skbuff[priv->skb_currx] = skb;
1547
1548                 /* Update to the next pointer */
1549                 if (bdp->status & RXBD_WRAP)
1550                         bdp = priv->rx_bd_base;
1551                 else
1552                         bdp++;
1553
1554                 /* update to point at the next skb */
1555                 priv->skb_currx =
1556                     (priv->skb_currx +
1557                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1558
1559         }
1560
1561         /* Update the current rxbd pointer to be the next one */
1562         priv->cur_rx = bdp;
1563
1564         return howmany;
1565 }
1566
1567 #ifdef CONFIG_GFAR_NAPI
1568 static int gfar_poll(struct napi_struct *napi, int budget)
1569 {
1570         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1571         struct net_device *dev = priv->dev;
1572         int howmany;
1573
1574         howmany = gfar_clean_rx_ring(dev, budget);
1575
1576         if (howmany < budget) {
1577                 netif_rx_complete(dev, napi);
1578
1579                 /* Clear the halt bit in RSTAT */
1580                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1581
1582                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1583
1584                 /* If we are coalescing interrupts, update the timer */
1585                 /* Otherwise, clear it */
1586                 if (priv->rxcoalescing)
1587                         gfar_write(&priv->regs->rxic,
1588                                    mk_ic_value(priv->rxcount, priv->rxtime));
1589                 else
1590                         gfar_write(&priv->regs->rxic, 0);
1591         }
1592
1593         return howmany;
1594 }
1595 #endif
1596
1597 #ifdef CONFIG_NET_POLL_CONTROLLER
1598 /*
1599  * Polling 'interrupt' - used by things like netconsole to send skbs
1600  * without having to re-enable interrupts. It's not called while
1601  * the interrupt routine is executing.
1602  */
1603 static void gfar_netpoll(struct net_device *dev)
1604 {
1605         struct gfar_private *priv = netdev_priv(dev);
1606
1607         /* If the device has multiple interrupts, run tx/rx */
1608         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1609                 disable_irq(priv->interruptTransmit);
1610                 disable_irq(priv->interruptReceive);
1611                 disable_irq(priv->interruptError);
1612                 gfar_interrupt(priv->interruptTransmit, dev);
1613                 enable_irq(priv->interruptError);
1614                 enable_irq(priv->interruptReceive);
1615                 enable_irq(priv->interruptTransmit);
1616         } else {
1617                 disable_irq(priv->interruptTransmit);
1618                 gfar_interrupt(priv->interruptTransmit, dev);
1619                 enable_irq(priv->interruptTransmit);
1620         }
1621 }
1622 #endif
1623
1624 /* The interrupt handler for devices with one interrupt */
1625 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1626 {
1627         struct net_device *dev = dev_id;
1628         struct gfar_private *priv = netdev_priv(dev);
1629
1630         /* Save ievent for future reference */
1631         u32 events = gfar_read(&priv->regs->ievent);
1632
1633         /* Check for reception */
1634         if (events & IEVENT_RX_MASK)
1635                 gfar_receive(irq, dev_id);
1636
1637         /* Check for transmit completion */
1638         if (events & IEVENT_TX_MASK)
1639                 gfar_transmit(irq, dev_id);
1640
1641         /* Check for errors */
1642         if (events & IEVENT_ERR_MASK)
1643                 gfar_error(irq, dev_id);
1644
1645         return IRQ_HANDLED;
1646 }
1647
1648 /* Called every time the controller might need to be made
1649  * aware of new link state.  The PHY code conveys this
1650  * information through variables in the phydev structure, and this
1651  * function converts those variables into the appropriate
1652  * register values, and can bring down the device if needed.
1653  */
1654 static void adjust_link(struct net_device *dev)
1655 {
1656         struct gfar_private *priv = netdev_priv(dev);
1657         struct gfar __iomem *regs = priv->regs;
1658         unsigned long flags;
1659         struct phy_device *phydev = priv->phydev;
1660         int new_state = 0;
1661
1662         spin_lock_irqsave(&priv->txlock, flags);
1663         if (phydev->link) {
1664                 u32 tempval = gfar_read(&regs->maccfg2);
1665                 u32 ecntrl = gfar_read(&regs->ecntrl);
1666
1667                 /* Now we make sure that we can be in full duplex mode.
1668                  * If not, we operate in half-duplex mode. */
1669                 if (phydev->duplex != priv->oldduplex) {
1670                         new_state = 1;
1671                         if (!(phydev->duplex))
1672                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1673                         else
1674                                 tempval |= MACCFG2_FULL_DUPLEX;
1675
1676                         priv->oldduplex = phydev->duplex;
1677                 }
1678
1679                 if (phydev->speed != priv->oldspeed) {
1680                         new_state = 1;
1681                         switch (phydev->speed) {
1682                         case 1000:
1683                                 tempval =
1684                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1685                                 break;
1686                         case 100:
1687                         case 10:
1688                                 tempval =
1689                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1690
1691                                 /* Reduced mode distinguishes
1692                                  * between 10 and 100 */
1693                                 if (phydev->speed == SPEED_100)
1694                                         ecntrl |= ECNTRL_R100;
1695                                 else
1696                                         ecntrl &= ~(ECNTRL_R100);
1697                                 break;
1698                         default:
1699                                 if (netif_msg_link(priv))
1700                                         printk(KERN_WARNING
1701                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1702                                                 dev->name, phydev->speed);
1703                                 break;
1704                         }
1705
1706                         priv->oldspeed = phydev->speed;
1707                 }
1708
1709                 gfar_write(&regs->maccfg2, tempval);
1710                 gfar_write(&regs->ecntrl, ecntrl);
1711
1712                 if (!priv->oldlink) {
1713                         new_state = 1;
1714                         priv->oldlink = 1;
1715                         netif_schedule(dev);
1716                 }
1717         } else if (priv->oldlink) {
1718                 new_state = 1;
1719                 priv->oldlink = 0;
1720                 priv->oldspeed = 0;
1721                 priv->oldduplex = -1;
1722         }
1723
1724         if (new_state && netif_msg_link(priv))
1725                 phy_print_status(phydev);
1726
1727         spin_unlock_irqrestore(&priv->txlock, flags);
1728 }
1729
1730 /* Update the hash table based on the current list of multicast
1731  * addresses we subscribe to.  Also, change the promiscuity of
1732  * the device based on the flags (this function is called
1733  * whenever dev->flags is changed */
1734 static void gfar_set_multi(struct net_device *dev)
1735 {
1736         struct dev_mc_list *mc_ptr;
1737         struct gfar_private *priv = netdev_priv(dev);
1738         struct gfar __iomem *regs = priv->regs;
1739         u32 tempval;
1740
1741         if(dev->flags & IFF_PROMISC) {
1742                 /* Set RCTRL to PROM */
1743                 tempval = gfar_read(&regs->rctrl);
1744                 tempval |= RCTRL_PROM;
1745                 gfar_write(&regs->rctrl, tempval);
1746         } else {
1747                 /* Set RCTRL to not PROM */
1748                 tempval = gfar_read(&regs->rctrl);
1749                 tempval &= ~(RCTRL_PROM);
1750                 gfar_write(&regs->rctrl, tempval);
1751         }
1752
1753         if(dev->flags & IFF_ALLMULTI) {
1754                 /* Set the hash to rx all multicast frames */
1755                 gfar_write(&regs->igaddr0, 0xffffffff);
1756                 gfar_write(&regs->igaddr1, 0xffffffff);
1757                 gfar_write(&regs->igaddr2, 0xffffffff);
1758                 gfar_write(&regs->igaddr3, 0xffffffff);
1759                 gfar_write(&regs->igaddr4, 0xffffffff);
1760                 gfar_write(&regs->igaddr5, 0xffffffff);
1761                 gfar_write(&regs->igaddr6, 0xffffffff);
1762                 gfar_write(&regs->igaddr7, 0xffffffff);
1763                 gfar_write(&regs->gaddr0, 0xffffffff);
1764                 gfar_write(&regs->gaddr1, 0xffffffff);
1765                 gfar_write(&regs->gaddr2, 0xffffffff);
1766                 gfar_write(&regs->gaddr3, 0xffffffff);
1767                 gfar_write(&regs->gaddr4, 0xffffffff);
1768                 gfar_write(&regs->gaddr5, 0xffffffff);
1769                 gfar_write(&regs->gaddr6, 0xffffffff);
1770                 gfar_write(&regs->gaddr7, 0xffffffff);
1771         } else {
1772                 int em_num;
1773                 int idx;
1774
1775                 /* zero out the hash */
1776                 gfar_write(&regs->igaddr0, 0x0);
1777                 gfar_write(&regs->igaddr1, 0x0);
1778                 gfar_write(&regs->igaddr2, 0x0);
1779                 gfar_write(&regs->igaddr3, 0x0);
1780                 gfar_write(&regs->igaddr4, 0x0);
1781                 gfar_write(&regs->igaddr5, 0x0);
1782                 gfar_write(&regs->igaddr6, 0x0);
1783                 gfar_write(&regs->igaddr7, 0x0);
1784                 gfar_write(&regs->gaddr0, 0x0);
1785                 gfar_write(&regs->gaddr1, 0x0);
1786                 gfar_write(&regs->gaddr2, 0x0);
1787                 gfar_write(&regs->gaddr3, 0x0);
1788                 gfar_write(&regs->gaddr4, 0x0);
1789                 gfar_write(&regs->gaddr5, 0x0);
1790                 gfar_write(&regs->gaddr6, 0x0);
1791                 gfar_write(&regs->gaddr7, 0x0);
1792
1793                 /* If we have extended hash tables, we need to
1794                  * clear the exact match registers to prepare for
1795                  * setting them */
1796                 if (priv->extended_hash) {
1797                         em_num = GFAR_EM_NUM + 1;
1798                         gfar_clear_exact_match(dev);
1799                         idx = 1;
1800                 } else {
1801                         idx = 0;
1802                         em_num = 0;
1803                 }
1804
1805                 if(dev->mc_count == 0)
1806                         return;
1807
1808                 /* Parse the list, and set the appropriate bits */
1809                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1810                         if (idx < em_num) {
1811                                 gfar_set_mac_for_addr(dev, idx,
1812                                                 mc_ptr->dmi_addr);
1813                                 idx++;
1814                         } else
1815                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1816                 }
1817         }
1818
1819         return;
1820 }
1821
1822
1823 /* Clears each of the exact match registers to zero, so they
1824  * don't interfere with normal reception */
1825 static void gfar_clear_exact_match(struct net_device *dev)
1826 {
1827         int idx;
1828         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1829
1830         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1831                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1832 }
1833
1834 /* Set the appropriate hash bit for the given addr */
1835 /* The algorithm works like so:
1836  * 1) Take the Destination Address (ie the multicast address), and
1837  * do a CRC on it (little endian), and reverse the bits of the
1838  * result.
1839  * 2) Use the 8 most significant bits as a hash into a 256-entry
1840  * table.  The table is controlled through 8 32-bit registers:
1841  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1842  * gaddr7.  This means that the 3 most significant bits in the
1843  * hash index which gaddr register to use, and the 5 other bits
1844  * indicate which bit (assuming an IBM numbering scheme, which
1845  * for PowerPC (tm) is usually the case) in the register holds
1846  * the entry. */
1847 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1848 {
1849         u32 tempval;
1850         struct gfar_private *priv = netdev_priv(dev);
1851         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1852         int width = priv->hash_width;
1853         u8 whichbit = (result >> (32 - width)) & 0x1f;
1854         u8 whichreg = result >> (32 - width + 5);
1855         u32 value = (1 << (31-whichbit));
1856
1857         tempval = gfar_read(priv->hash_regs[whichreg]);
1858         tempval |= value;
1859         gfar_write(priv->hash_regs[whichreg], tempval);
1860
1861         return;
1862 }
1863
1864
1865 /* There are multiple MAC Address register pairs on some controllers
1866  * This function sets the numth pair to a given address
1867  */
1868 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1869 {
1870         struct gfar_private *priv = netdev_priv(dev);
1871         int idx;
1872         char tmpbuf[MAC_ADDR_LEN];
1873         u32 tempval;
1874         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1875
1876         macptr += num*2;
1877
1878         /* Now copy it into the mac registers backwards, cuz */
1879         /* little endian is silly */
1880         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1881                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1882
1883         gfar_write(macptr, *((u32 *) (tmpbuf)));
1884
1885         tempval = *((u32 *) (tmpbuf + 4));
1886
1887         gfar_write(macptr+1, tempval);
1888 }
1889
1890 /* GFAR error interrupt handler */
1891 static irqreturn_t gfar_error(int irq, void *dev_id)
1892 {
1893         struct net_device *dev = dev_id;
1894         struct gfar_private *priv = netdev_priv(dev);
1895
1896         /* Save ievent for future reference */
1897         u32 events = gfar_read(&priv->regs->ievent);
1898
1899         /* Clear IEVENT */
1900         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1901
1902         /* Hmm... */
1903         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1904                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1905                        dev->name, events, gfar_read(&priv->regs->imask));
1906
1907         /* Update the error counters */
1908         if (events & IEVENT_TXE) {
1909                 dev->stats.tx_errors++;
1910
1911                 if (events & IEVENT_LC)
1912                         dev->stats.tx_window_errors++;
1913                 if (events & IEVENT_CRL)
1914                         dev->stats.tx_aborted_errors++;
1915                 if (events & IEVENT_XFUN) {
1916                         if (netif_msg_tx_err(priv))
1917                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1918                                        "packet dropped.\n", dev->name);
1919                         dev->stats.tx_dropped++;
1920                         priv->extra_stats.tx_underrun++;
1921
1922                         /* Reactivate the Tx Queues */
1923                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1924                 }
1925                 if (netif_msg_tx_err(priv))
1926                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1927         }
1928         if (events & IEVENT_BSY) {
1929                 dev->stats.rx_errors++;
1930                 priv->extra_stats.rx_bsy++;
1931
1932                 gfar_receive(irq, dev_id);
1933
1934 #ifndef CONFIG_GFAR_NAPI
1935                 /* Clear the halt bit in RSTAT */
1936                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1937 #endif
1938
1939                 if (netif_msg_rx_err(priv))
1940                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1941                                dev->name, gfar_read(&priv->regs->rstat));
1942         }
1943         if (events & IEVENT_BABR) {
1944                 dev->stats.rx_errors++;
1945                 priv->extra_stats.rx_babr++;
1946
1947                 if (netif_msg_rx_err(priv))
1948                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1949         }
1950         if (events & IEVENT_EBERR) {
1951                 priv->extra_stats.eberr++;
1952                 if (netif_msg_rx_err(priv))
1953                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
1954         }
1955         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1956                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1957
1958         if (events & IEVENT_BABT) {
1959                 priv->extra_stats.tx_babt++;
1960                 if (netif_msg_tx_err(priv))
1961                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1962         }
1963         return IRQ_HANDLED;
1964 }
1965
1966 /* Structure for a device driver */
1967 static struct platform_driver gfar_driver = {
1968         .probe = gfar_probe,
1969         .remove = gfar_remove,
1970         .driver = {
1971                 .name = "fsl-gianfar",
1972         },
1973 };
1974
1975 static int __init gfar_init(void)
1976 {
1977         int err = gfar_mdio_init();
1978
1979         if (err)
1980                 return err;
1981
1982         err = platform_driver_register(&gfar_driver);
1983
1984         if (err)
1985                 gfar_mdio_exit();
1986
1987         return err;
1988 }
1989
1990 static void __exit gfar_exit(void)
1991 {
1992         platform_driver_unregister(&gfar_driver);
1993         gfar_mdio_exit();
1994 }
1995
1996 module_init(gfar_init);
1997 module_exit(gfar_exit);
1998