2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020.
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/procinfo.h>
35 #include <asm/ptrace.h>
38 * This is the maximum size of an area which will be invalidated
39 * using the single invalidate entry instructions. Anything larger
40 * than this, and we go for the whole cache.
42 * This value should be chosen such that we choose the cheapest
45 #define MAX_AREA_SIZE 32768
48 * The size of one data cache line.
50 #define CACHE_DLINESIZE 32
53 * The number of data cache segments.
55 #define CACHE_DSEGMENTS 16
58 * The number of lines in a cache segment.
60 #define CACHE_DENTRIES 64
63 * This is the size at which it becomes more efficient to
64 * clean the whole cache, rather than using the individual
65 * cache line maintainence instructions.
67 #define CACHE_DLIMIT 32768
71 * cpu_arm1020_proc_init()
73 ENTRY(cpu_arm1020_proc_init)
77 * cpu_arm1020_proc_fin()
79 ENTRY(cpu_arm1020_proc_fin)
81 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
83 bl arm1020_flush_kern_cache_all
84 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
85 bic r0, r0, #0x1000 @ ...i............
86 bic r0, r0, #0x000e @ ............wca.
87 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 * cpu_arm1020_reset(loc)
93 * Perform a soft reset of the system. Put the CPU into the
94 * same state as it would be if it had been reset, and branch
95 * to what would be the reset vector.
97 * loc: location to jump to for soft reset
100 ENTRY(cpu_arm1020_reset)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
108 bic ip, ip, #0x000f @ ............wcam
109 bic ip, ip, #0x1100 @ ...i...s........
110 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 * cpu_arm1020_do_idle()
117 ENTRY(cpu_arm1020_do_idle)
118 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 /* ================================= CACHE ================================ */
125 * flush_user_cache_all()
127 * Invalidate all cache entries in a particular address
130 ENTRY(arm1020_flush_user_cache_all)
133 * flush_kern_cache_all()
135 * Clean and invalidate the entire cache.
137 ENTRY(arm1020_flush_kern_cache_all)
141 #ifndef CONFIG_CPU_DCACHE_DISABLE
142 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
144 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
145 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
146 mcr p15, 0, ip, c7, c10, 4 @ drain WB
147 subs r3, r3, #1 << 26
148 bcs 2b @ entries 63 to 0
150 bcs 1b @ segments 15 to 0
153 #ifndef CONFIG_CPU_ICACHE_DISABLE
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
156 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
160 * flush_user_cache_range(start, end, flags)
162 * Invalidate a range of cache entries in the specified
165 * - start - start address (inclusive)
166 * - end - end address (exclusive)
167 * - flags - vm_flags for this space
169 ENTRY(arm1020_flush_user_cache_range)
171 sub r3, r1, r0 @ calculate total size
172 cmp r3, #CACHE_DLIMIT
173 bhs __flush_whole_cache
175 #ifndef CONFIG_CPU_DCACHE_DISABLE
176 mcr p15, 0, ip, c7, c10, 4
177 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
178 mcr p15, 0, ip, c7, c10, 4 @ drain WB
179 add r0, r0, #CACHE_DLINESIZE
184 #ifndef CONFIG_CPU_ICACHE_DISABLE
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
191 * coherent_kern_range(start, end)
193 * Ensure coherency between the Icache and the Dcache in the
194 * region described by start. If you have non-snooping
195 * Harvard caches, you need to implement this function.
197 * - start - virtual start address
198 * - end - virtual end address
200 ENTRY(arm1020_coherent_kern_range)
204 * coherent_user_range(start, end)
206 * Ensure coherency between the Icache and the Dcache in the
207 * region described by start. If you have non-snooping
208 * Harvard caches, you need to implement this function.
210 * - start - virtual start address
211 * - end - virtual end address
213 ENTRY(arm1020_coherent_user_range)
215 bic r0, r0, #CACHE_DLINESIZE - 1
216 mcr p15, 0, ip, c7, c10, 4
218 #ifndef CONFIG_CPU_DCACHE_DISABLE
219 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
220 mcr p15, 0, ip, c7, c10, 4 @ drain WB
222 #ifndef CONFIG_CPU_ICACHE_DISABLE
223 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
225 add r0, r0, #CACHE_DLINESIZE
228 mcr p15, 0, ip, c7, c10, 4 @ drain WB
232 * flush_kern_dcache_page(void *page)
234 * Ensure no D cache aliasing occurs, either with itself or
237 * - page - page aligned address
239 ENTRY(arm1020_flush_kern_dcache_page)
241 #ifndef CONFIG_CPU_DCACHE_DISABLE
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
244 mcr p15, 0, ip, c7, c10, 4 @ drain WB
245 add r0, r0, #CACHE_DLINESIZE
249 mcr p15, 0, ip, c7, c10, 4 @ drain WB
253 * dma_inv_range(start, end)
255 * Invalidate (discard) the specified virtual address range.
256 * May not write back any entries. If 'start' or 'end'
257 * are not cache line aligned, those lines must be written
260 * - start - virtual start address
261 * - end - virtual end address
265 ENTRY(arm1020_dma_inv_range)
267 #ifndef CONFIG_CPU_DCACHE_DISABLE
268 tst r0, #CACHE_DLINESIZE - 1
269 bic r0, r0, #CACHE_DLINESIZE - 1
270 mcrne p15, 0, ip, c7, c10, 4
271 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
272 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
273 tst r1, #CACHE_DLINESIZE - 1
274 mcrne p15, 0, ip, c7, c10, 4
275 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
276 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
277 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
278 add r0, r0, #CACHE_DLINESIZE
282 mcr p15, 0, ip, c7, c10, 4 @ drain WB
286 * dma_clean_range(start, end)
288 * Clean the specified virtual address range.
290 * - start - virtual start address
291 * - end - virtual end address
295 ENTRY(arm1020_dma_clean_range)
297 #ifndef CONFIG_CPU_DCACHE_DISABLE
298 bic r0, r0, #CACHE_DLINESIZE - 1
299 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
300 mcr p15, 0, ip, c7, c10, 4 @ drain WB
301 add r0, r0, #CACHE_DLINESIZE
305 mcr p15, 0, ip, c7, c10, 4 @ drain WB
309 * dma_flush_range(start, end)
311 * Clean and invalidate the specified virtual address range.
313 * - start - virtual start address
314 * - end - virtual end address
316 ENTRY(arm1020_dma_flush_range)
318 #ifndef CONFIG_CPU_DCACHE_DISABLE
319 bic r0, r0, #CACHE_DLINESIZE - 1
320 mcr p15, 0, ip, c7, c10, 4
321 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 mcr p15, 0, ip, c7, c10, 4 @ drain WB
323 add r0, r0, #CACHE_DLINESIZE
327 mcr p15, 0, ip, c7, c10, 4 @ drain WB
330 ENTRY(arm1020_cache_fns)
331 .long arm1020_flush_kern_cache_all
332 .long arm1020_flush_user_cache_all
333 .long arm1020_flush_user_cache_range
334 .long arm1020_coherent_kern_range
335 .long arm1020_coherent_user_range
336 .long arm1020_flush_kern_dcache_page
337 .long arm1020_dma_inv_range
338 .long arm1020_dma_clean_range
339 .long arm1020_dma_flush_range
342 ENTRY(cpu_arm1020_dcache_clean_area)
343 #ifndef CONFIG_CPU_DCACHE_DISABLE
345 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
346 mcr p15, 0, ip, c7, c10, 4 @ drain WB
347 add r0, r0, #CACHE_DLINESIZE
348 subs r1, r1, #CACHE_DLINESIZE
353 /* =============================== PageTable ============================== */
356 * cpu_arm1020_switch_mm(pgd)
358 * Set the translation base pointer to be as described by pgd.
360 * pgd: new page tables
363 ENTRY(cpu_arm1020_switch_mm)
365 #ifndef CONFIG_CPU_DCACHE_DISABLE
366 mcr p15, 0, r3, c7, c10, 4
367 mov r1, #0xF @ 16 segments
368 1: mov r3, #0x3F @ 64 entries
369 2: mov ip, r3, LSL #26 @ shift up entry
370 orr ip, ip, r1, LSL #5 @ shift in/up index
371 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
373 mcr p15, 0, ip, c7, c10, 4
376 bge 2b @ entries 3F to 0
379 bge 1b @ segments 15 to 0
383 #ifndef CONFIG_CPU_ICACHE_DISABLE
384 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
386 mcr p15, 0, r1, c7, c10, 4 @ drain WB
387 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
388 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
389 #endif /* CONFIG_MMU */
393 * cpu_arm1020_set_pte(ptep, pte)
395 * Set a PTE and flush it out
398 ENTRY(cpu_arm1020_set_pte)
400 str r1, [r0], #-2048 @ linux version
402 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
404 bic r2, r1, #PTE_SMALL_AP_MASK
405 bic r2, r2, #PTE_TYPE_MASK
406 orr r2, r2, #PTE_TYPE_SMALL
408 tst r1, #L_PTE_USER @ User?
409 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
411 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
412 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
414 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
417 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
418 eor r3, r1, #0x0a @ C & small page?
422 str r2, [r0] @ hardware version
424 #ifndef CONFIG_CPU_DCACHE_DISABLE
425 mcr p15, 0, r0, c7, c10, 4
426 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
428 mcr p15, 0, r0, c7, c10, 4 @ drain WB
429 #endif /* CONFIG_MMU */
434 .type __arm1020_setup, #function
437 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
438 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
443 adr r5, arm1020_crval
445 mrc p15, 0, r0, c1, c0 @ get control register v4
448 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
449 orr r0, r0, #0x4000 @ .R.. .... .... ....
452 .size __arm1020_setup, . - __arm1020_setup
456 * .RVI ZFRS BLDP WCAM
457 * .011 1001 ..11 0101
459 .type arm1020_crval, #object
461 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
466 * Purpose : Function pointers used to access above functions - all calls
469 .type arm1020_processor_functions, #object
470 arm1020_processor_functions:
471 .word v4t_early_abort
472 .word cpu_arm1020_proc_init
473 .word cpu_arm1020_proc_fin
474 .word cpu_arm1020_reset
475 .word cpu_arm1020_do_idle
476 .word cpu_arm1020_dcache_clean_area
477 .word cpu_arm1020_switch_mm
478 .word cpu_arm1020_set_pte
479 .size arm1020_processor_functions, . - arm1020_processor_functions
483 .type cpu_arch_name, #object
486 .size cpu_arch_name, . - cpu_arch_name
488 .type cpu_elf_name, #object
491 .size cpu_elf_name, . - cpu_elf_name
493 .type cpu_arm1020_name, #object
496 #ifndef CONFIG_CPU_ICACHE_DISABLE
499 #ifndef CONFIG_CPU_DCACHE_DISABLE
501 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
507 #ifndef CONFIG_CPU_BPREDICT_DISABLE
510 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
514 .size cpu_arm1020_name, . - cpu_arm1020_name
518 .section ".proc.info.init", #alloc, #execinstr
520 .type __arm1020_proc_info,#object
522 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
524 .long PMD_TYPE_SECT | \
525 PMD_SECT_AP_WRITE | \
527 .long PMD_TYPE_SECT | \
528 PMD_SECT_AP_WRITE | \
533 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
534 .long cpu_arm1020_name
535 .long arm1020_processor_functions
538 .long arm1020_cache_fns
539 .size __arm1020_proc_info, . - __arm1020_proc_info