1 /* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #define RTRAP_PSTATE (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18 #define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
19 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
21 /* Register %l6 keeps track of whether we are returning
22 * from a system call or not. It is cleared if we call
23 * do_notify_resume, and it must not be otherwise modified
24 * until we fully commit to returning to userspace.
32 ba,a,pt %xcc, __handle_softirq_continue
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 ba,pt %xcc, __handle_preemption_continue
38 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
40 __handle_user_windows:
41 call fault_in_user_windows
42 wrpr %g0, RTRAP_PSTATE, %pstate
43 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
44 /* Redo sched+sig checks */
45 ldx [%g6 + TI_FLAGS], %l0
46 andcc %l0, _TIF_NEED_RESCHED, %g0
51 wrpr %g0, RTRAP_PSTATE, %pstate
52 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
53 ldx [%g6 + TI_FLAGS], %l0
55 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
56 be,pt %xcc, __handle_user_windows_continue
60 add %sp, PTREGS_OFF, %o0
64 wrpr %g0, RTRAP_PSTATE, %pstate
65 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
67 /* Signal delivery can modify pt_regs tstate, so we must
70 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
71 sethi %hi(0xf << 20), %l4
73 ba,pt %xcc, __handle_user_windows_continue
78 wrpr %g0, RTRAP_PSTATE, %pstate
79 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
80 ldub [%g6 + TI_WSAVED], %o2
83 /* Redo userwin+sched+sig checks */
84 call fault_in_user_windows
86 wrpr %g0, RTRAP_PSTATE, %pstate
87 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
88 ldx [%g6 + TI_FLAGS], %l0
89 andcc %l0, _TIF_NEED_RESCHED, %g0
94 wrpr %g0, RTRAP_PSTATE, %pstate
95 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
96 ldx [%g6 + TI_FLAGS], %l0
97 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
99 be,pt %xcc, __handle_perfctrs_continue
100 sethi %hi(TSTATE_PEF), %o0
103 add %sp, PTREGS_OFF, %o0
105 call do_notify_resume
107 wrpr %g0, RTRAP_PSTATE, %pstate
108 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
110 /* Signal delivery can modify pt_regs tstate, so we must
113 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
114 sethi %hi(0xf << 20), %l4
117 ba,pt %xcc, __handle_perfctrs_continue
119 sethi %hi(TSTATE_PEF), %o0
122 andcc %l5, FPRS_FEF, %g0
123 sethi %hi(TSTATE_PEF), %o0
124 be,a,pn %icc, __handle_userfpu_continue
126 ba,a,pt %xcc, __handle_userfpu_continue
131 add %sp, PTREGS_OFF, %o0
133 call do_notify_resume
134 wrpr %g0, RTRAP_PSTATE, %pstate
135 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
138 /* Signal delivery can modify pt_regs tstate, so we must
141 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
142 sethi %hi(0xf << 20), %l4
144 ba,pt %xcc, __handle_signal_continue
148 .globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
150 rtrap_clr_l6: clr %l6
153 sethi %hi(per_cpu____cpu_data), %l0
154 lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
156 sethi %hi(per_cpu____cpu_data), %l0
157 or %l0, %lo(per_cpu____cpu_data), %l0
158 lduw [%l0 + %g5], %l1
162 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
163 bne,pn %icc, __handle_softirq
164 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
165 __handle_softirq_continue:
167 sethi %hi(0xf << 20), %l4
168 andcc %l1, TSTATE_PRIV, %l3
170 bne,pn %icc, to_kernel
173 /* We must hold IRQs off and atomically test schedule+signal
174 * state, then hold them off all the way back to userspace.
175 * If we are returning to kernel, none of this matters.
177 * If we do not do this, there is a window where we would do
178 * the tests, later the signal/resched event arrives but we do
179 * not process it since we are still in kernel mode. It would
180 * take until the next local IRQ before the signal/resched
181 * event would be handled.
183 * This also means that if we have to deal with performance
184 * counters or user windows, we have to redo all of these
185 * sched+signal checks with IRQs disabled.
187 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
189 __handle_preemption_continue:
190 ldx [%g6 + TI_FLAGS], %l0
191 sethi %hi(_TIF_USER_WORK_MASK), %o0
192 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
194 sethi %hi(TSTATE_PEF), %o0
195 be,pt %xcc, user_nowork
197 andcc %l0, _TIF_NEED_RESCHED, %g0
198 bne,pn %xcc, __handle_preemption
199 andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
200 bne,pn %xcc, __handle_signal
201 __handle_signal_continue:
202 ldub [%g6 + TI_WSAVED], %o2
203 brnz,pn %o2, __handle_user_windows
205 __handle_user_windows_continue:
206 ldx [%g6 + TI_FLAGS], %l5
207 andcc %l5, _TIF_PERFCTR, %g0
208 sethi %hi(TSTATE_PEF), %o0
209 bne,pn %xcc, __handle_perfctrs
210 __handle_perfctrs_continue:
213 /* This fpdepth clear is necessary for non-syscall rtraps only */
215 bne,pn %xcc, __handle_userfpu
216 stb %g0, [%g6 + TI_FPDEPTH]
217 __handle_userfpu_continue:
219 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
220 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
222 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
223 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
224 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
228 /* Must do this before thread reg is clobbered below. */
229 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
231 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
232 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
234 /* Normal globals are restored, go to trap globals. */
235 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
237 .section .sun4v_2insn_patch, "ax"
239 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
245 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
246 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
248 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
249 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
250 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
251 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
252 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
253 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
254 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
255 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
257 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
262 wrpr %l1, %g0, %tstate
266 brnz,pn %l3, kern_rtt
267 mov PRIMARY_CONTEXT, %l7
269 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
270 .section .sun4v_1insn_patch, "ax"
272 ldxa [%l7 + %l7] ASI_MMU, %l0
275 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
276 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
279 661: stxa %l0, [%l7] ASI_DMMU
280 .section .sun4v_1insn_patch, "ax"
282 stxa %l0, [%l7] ASI_MMU
285 sethi %hi(KERNBASE), %l7
291 wrpr %l2, %g0, %canrestore
292 wrpr %l1, %g0, %wstate
293 brnz,pt %l2, user_rtt_restore
294 wrpr %g0, %g0, %otherwin
296 ldx [%g6 + TI_FLAGS], %g3
297 wr %g0, ASI_AIUP, %asi
299 andcc %g3, _TIF_32BIT, %g0
301 bne,pt %xcc, user_rtt_fill_32bit
303 ba,a,pt %xcc, user_rtt_fill_64bit
312 wrpr %g2, 0x0, %wstate
314 /* We know %canrestore and %otherwin are both zero. */
316 sethi %hi(sparc64_kern_pri_context), %g2
317 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
318 mov PRIMARY_CONTEXT, %g1
320 661: stxa %g2, [%g1] ASI_DMMU
321 .section .sun4v_1insn_patch, "ax"
323 stxa %g2, [%g1] ASI_MMU
326 sethi %hi(KERNBASE), %g1
329 or %g4, FAULT_CODE_WINFIXUP, %g4
330 stb %g4, [%g6 + TI_FAULT_CODE]
331 stx %g5, [%g6 + TI_FAULT_ADDR]
337 .section .sun4v_1insn_patch, "ax"
342 wrpr %g0, RTRAP_PSTATE, %pstate
345 ldx [%g6 + TI_TASK], %g4
346 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
347 call do_sparc64_fault
348 add %sp, PTREGS_OFF, %o0
352 user_rtt_pre_restore:
358 rdpr %canrestore, %g1
359 wrpr %g1, 0x0, %cleanwin
363 kern_rtt: rdpr %canrestore, %g1
364 brz,pn %g1, kern_rtt_fill
371 #ifdef CONFIG_PREEMPT
372 ldsw [%g6 + TI_PRE_COUNT], %l5
373 brnz %l5, kern_fpucheck
374 ldx [%g6 + TI_FLAGS], %l5
375 andcc %l5, _TIF_NEED_RESCHED, %g0
376 be,pt %xcc, kern_fpucheck
379 bne,pn %xcc, kern_fpucheck
380 sethi %hi(PREEMPT_ACTIVE), %l6
381 stw %l6, [%g6 + TI_PRE_COUNT]
385 stw %g0, [%g6 + TI_PRE_COUNT]
387 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
388 brz,pt %l5, rt_continue
390 add %g6, TI_FPSAVED, %l6
391 ldub [%l6 + %o0], %l2
395 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
397 and %l2, FPRS_DL, %l6
398 andcc %l2, FPRS_FEF, %g0
403 wr %g1, FPRS_FEF, %fprs
405 add %g6, TI_XFSR, %o1
407 add %g6, TI_FPREGS, %o3
409 add %g6, TI_FPREGS+0x40, %o4
412 ldda [%o3 + %o2] ASI_BLK_P, %f0
413 ldda [%o4 + %o2] ASI_BLK_P, %f16
415 1: andcc %l2, FPRS_DU, %g0
420 ldda [%o3 + %o2] ASI_BLK_P, %f32
421 ldda [%o4 + %o2] ASI_BLK_P, %f48
423 ldx [%o1 + %o5], %fsr
424 2: stb %l5, [%g6 + TI_FPDEPTH]
425 ba,pt %xcc, rt_continue
427 5: wr %g0, FPRS_FEF, %fprs
430 add %g6, TI_FPREGS+0x80, %o3
431 add %g6, TI_FPREGS+0xc0, %o4
433 ldda [%o3 + %o2] ASI_BLK_P, %f32
434 ldda [%o4 + %o2] ASI_BLK_P, %f48
436 wr %g0, FPRS_DU, %fprs
437 ba,pt %xcc, rt_continue
438 stb %l5, [%g6 + TI_FPDEPTH]