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   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31
  32 #include <asm/system.h>
  33 #include <mach/hardware.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/hardware/arm_timer.h>
  38 #include <asm/hardware/icst307.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /* used by entry-macro.S and platsmp.c */
  54 void __iomem *gic_cpu_base_addr;
  55
  56 /*
  57  * This is the RealView sched_clock implementation.  This has
  58  * a resolution of 41.7ns, and a maximum value of about 179s.
  59  */
  60 unsigned long long sched_clock(void)
  61 {
  62         unsigned long long v;
  63
  64         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  65         do_div(v, 3);
  66
  67         return v;
  68 }
  69
  70
  71 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  72
  73 static int realview_flash_init(void)
  74 {
  75         u32 val;
  76
  77         val = __raw_readl(REALVIEW_FLASHCTRL);
  78         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  79         __raw_writel(val, REALVIEW_FLASHCTRL);
  80
  81         return 0;
  82 }
  83
  84 static void realview_flash_exit(void)
  85 {
  86         u32 val;
  87
  88         val = __raw_readl(REALVIEW_FLASHCTRL);
  89         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  90         __raw_writel(val, REALVIEW_FLASHCTRL);
  91 }
  92
  93 static void realview_flash_set_vpp(int on)
  94 {
  95         u32 val;
  96
  97         val = __raw_readl(REALVIEW_FLASHCTRL);
  98         if (on)
  99                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 100         else
 101                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 102         __raw_writel(val, REALVIEW_FLASHCTRL);
 103 }
 104
 105 static struct flash_platform_data realview_flash_data = {
 106         .map_name               = "cfi_probe",
 107         .width                  = 4,
 108         .init                   = realview_flash_init,
 109         .exit                   = realview_flash_exit,
 110         .set_vpp                = realview_flash_set_vpp,
 111 };
 112
 113 struct platform_device realview_flash_device = {
 114         .name                   = "armflash",
 115         .id                     = 0,
 116         .dev                    = {
 117                 .platform_data  = &realview_flash_data,
 118         },
 119 };
 120
 121 int realview_flash_register(struct resource *res, u32 num)
 122 {
 123         realview_flash_device.resource = res;
 124         realview_flash_device.num_resources = num;
 125         return platform_device_register(&realview_flash_device);
 126 }
 127
 128 static struct platform_device realview_eth_device = {
 129         .name           = "smc911x",
 130         .id             = 0,
 131         .num_resources  = 2,
 132 };
 133
 134 int realview_eth_register(const char *name, struct resource *res)
 135 {
 136         if (name)
 137                 realview_eth_device.name = name;
 138         realview_eth_device.resource = res;
 139
 140         return platform_device_register(&realview_eth_device);
 141 }
 142
 143 static struct resource realview_i2c_resource = {
 144         .start          = REALVIEW_I2C_BASE,
 145         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 146         .flags          = IORESOURCE_MEM,
 147 };
 148
 149 struct platform_device realview_i2c_device = {
 150         .name           = "versatile-i2c",
 151         .id             = -1,
 152         .num_resources  = 1,
 153         .resource       = &realview_i2c_resource,
 154 };
 155
 156 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 157
 158 static unsigned int realview_mmc_status(struct device *dev)
 159 {
 160         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 161         u32 mask;
 162
 163         if (adev->res.start == REALVIEW_MMCI0_BASE)
 164                 mask = 1;
 165         else
 166                 mask = 2;
 167
 168         return readl(REALVIEW_SYSMCI) & mask;
 169 }
 170
 171 struct mmc_platform_data realview_mmc0_plat_data = {
 172         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 173         .status         = realview_mmc_status,
 174 };
 175
 176 struct mmc_platform_data realview_mmc1_plat_data = {
 177         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 178         .status         = realview_mmc_status,
 179 };
 180
 181 /*
 182  * Clock handling
 183  */
 184 static const struct icst307_params realview_oscvco_params = {
 185         .ref            = 24000,
 186         .vco_max        = 200000,
 187         .vd_min         = 4 + 8,
 188         .vd_max         = 511 + 8,
 189         .rd_min         = 1 + 2,
 190         .rd_max         = 127 + 2,
 191 };
 192
 193 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 194 {
 195         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 196         void __iomem *sys_osc;
 197         u32 val;
 198
 199         if (machine_is_realview_pb1176())
 200                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 201         else
 202                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 203
 204         val = readl(sys_osc) & ~0x7ffff;
 205         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 206
 207         writel(0xa05f, sys_lock);
 208         writel(val, sys_osc);
 209         writel(0, sys_lock);
 210 }
 211
 212 struct clk realview_clcd_clk = {
 213         .name   = "CLCDCLK",
 214         .params = &realview_oscvco_params,
 215         .setvco = realview_oscvco_set,
 216 };
 217
 218 /*
 219  * CLCD support.
 220  */
 221 #define SYS_CLCD_NLCDIOON       (1 << 2)
 222 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 223 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 224 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 225 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 226 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 227 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 228 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 229 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 230
 231 static struct clcd_panel vga = {
 232         .mode           = {
 233                 .name           = "VGA",
 234                 .refresh        = 60,
 235                 .xres           = 640,
 236                 .yres           = 480,
 237                 .pixclock       = 39721,
 238                 .left_margin    = 40,
 239                 .right_margin   = 24,
 240                 .upper_margin   = 32,
 241                 .lower_margin   = 11,
 242                 .hsync_len      = 96,
 243                 .vsync_len      = 2,
 244                 .sync           = 0,
 245                 .vmode          = FB_VMODE_NONINTERLACED,
 246         },
 247         .width          = -1,
 248         .height         = -1,
 249         .tim2           = TIM2_BCD | TIM2_IPC,
 250         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 251         .bpp            = 16,
 252 };
 253
 254 static struct clcd_panel xvga = {
 255         .mode           = {
 256                 .name           = "XVGA",
 257                 .refresh        = 60,
 258                 .xres           = 1024,
 259                 .yres           = 768,
 260                 .pixclock       = 15748,
 261                 .left_margin    = 152,
 262                 .right_margin   = 48,
 263                 .upper_margin   = 23,
 264                 .lower_margin   = 3,
 265                 .hsync_len      = 104,
 266                 .vsync_len      = 4,
 267                 .sync           = 0,
 268                 .vmode          = FB_VMODE_NONINTERLACED,
 269         },
 270         .width          = -1,
 271         .height         = -1,
 272         .tim2           = TIM2_BCD | TIM2_IPC,
 273         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 274         .bpp            = 16,
 275 };
 276
 277 static struct clcd_panel sanyo_3_8_in = {
 278         .mode           = {
 279                 .name           = "Sanyo QVGA",
 280                 .refresh        = 116,
 281                 .xres           = 320,
 282                 .yres           = 240,
 283                 .pixclock       = 100000,
 284                 .left_margin    = 6,
 285                 .right_margin   = 6,
 286                 .upper_margin   = 5,
 287                 .lower_margin   = 5,
 288                 .hsync_len      = 6,
 289                 .vsync_len      = 6,
 290                 .sync           = 0,
 291                 .vmode          = FB_VMODE_NONINTERLACED,
 292         },
 293         .width          = -1,
 294         .height         = -1,
 295         .tim2           = TIM2_BCD,
 296         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 297         .bpp            = 16,
 298 };
 299
 300 static struct clcd_panel sanyo_2_5_in = {
 301         .mode           = {
 302                 .name           = "Sanyo QVGA Portrait",
 303                 .refresh        = 116,
 304                 .xres           = 240,
 305                 .yres           = 320,
 306                 .pixclock       = 100000,
 307                 .left_margin    = 20,
 308                 .right_margin   = 10,
 309                 .upper_margin   = 2,
 310                 .lower_margin   = 2,
 311                 .hsync_len      = 10,
 312                 .vsync_len      = 2,
 313                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 314                 .vmode          = FB_VMODE_NONINTERLACED,
 315         },
 316         .width          = -1,
 317         .height         = -1,
 318         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 319         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 320         .bpp            = 16,
 321 };
 322
 323 static struct clcd_panel epson_2_2_in = {
 324         .mode           = {
 325                 .name           = "Epson QCIF",
 326                 .refresh        = 390,
 327                 .xres           = 176,
 328                 .yres           = 220,
 329                 .pixclock       = 62500,
 330                 .left_margin    = 3,
 331                 .right_margin   = 2,
 332                 .upper_margin   = 1,
 333                 .lower_margin   = 0,
 334                 .hsync_len      = 3,
 335                 .vsync_len      = 2,
 336                 .sync           = 0,
 337                 .vmode          = FB_VMODE_NONINTERLACED,
 338         },
 339         .width          = -1,
 340         .height         = -1,
 341         .tim2           = TIM2_BCD | TIM2_IPC,
 342         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 343         .bpp            = 16,
 344 };
 345
 346 /*
 347  * Detect which LCD panel is connected, and return the appropriate
 348  * clcd_panel structure.  Note: we do not have any information on
 349  * the required timings for the 8.4in panel, so we presently assume
 350  * VGA timings.
 351  */
 352 static struct clcd_panel *realview_clcd_panel(void)
 353 {
 354         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 355         struct clcd_panel *vga_panel;
 356         struct clcd_panel *panel;
 357         u32 val;
 358
 359         if (machine_is_realview_eb())
 360                 vga_panel = &vga;
 361         else
 362                 vga_panel = &xvga;
 363
 364         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 365         if (val == SYS_CLCD_ID_SANYO_3_8)
 366                 panel = &sanyo_3_8_in;
 367         else if (val == SYS_CLCD_ID_SANYO_2_5)
 368                 panel = &sanyo_2_5_in;
 369         else if (val == SYS_CLCD_ID_EPSON_2_2)
 370                 panel = &epson_2_2_in;
 371         else if (val == SYS_CLCD_ID_VGA)
 372                 panel = vga_panel;
 373         else {
 374                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 375                         val);
 376                 panel = vga_panel;
 377         }
 378
 379         return panel;
 380 }
 381
 382 /*
 383  * Disable all display connectors on the interface module.
 384  */
 385 static void realview_clcd_disable(struct clcd_fb *fb)
 386 {
 387         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 388         u32 val;
 389
 390         val = readl(sys_clcd);
 391         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 392         writel(val, sys_clcd);
 393 }
 394
 395 /*
 396  * Enable the relevant connector on the interface module.
 397  */
 398 static void realview_clcd_enable(struct clcd_fb *fb)
 399 {
 400         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 401         u32 val;
 402
 403         /*
 404          * Enable the PSUs
 405          */
 406         val = readl(sys_clcd);
 407         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 408         writel(val, sys_clcd);
 409 }
 410
 411 static int realview_clcd_setup(struct clcd_fb *fb)
 412 {
 413         unsigned long framesize;
 414         dma_addr_t dma;
 415
 416         if (machine_is_realview_eb())
 417                 /* VGA, 16bpp */
 418                 framesize = 640 * 480 * 2;
 419         else
 420                 /* XVGA, 16bpp */
 421                 framesize = 1024 * 768 * 2;
 422
 423         fb->panel               = realview_clcd_panel();
 424
 425         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 426                                                     &dma, GFP_KERNEL);
 427         if (!fb->fb.screen_base) {
 428                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 429                 return -ENOMEM;
 430         }
 431
 432         fb->fb.fix.smem_start   = dma;
 433         fb->fb.fix.smem_len     = framesize;
 434
 435         return 0;
 436 }
 437
 438 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 439 {
 440         return dma_mmap_writecombine(&fb->dev->dev, vma,
 441                                      fb->fb.screen_base,
 442                                      fb->fb.fix.smem_start,
 443                                      fb->fb.fix.smem_len);
 444 }
 445
 446 static void realview_clcd_remove(struct clcd_fb *fb)
 447 {
 448         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 449                               fb->fb.screen_base, fb->fb.fix.smem_start);
 450 }
 451
 452 struct clcd_board clcd_plat_data = {
 453         .name           = "RealView",
 454         .check          = clcdfb_check,
 455         .decode         = clcdfb_decode,
 456         .disable        = realview_clcd_disable,
 457         .enable         = realview_clcd_enable,
 458         .setup          = realview_clcd_setup,
 459         .mmap           = realview_clcd_mmap,
 460         .remove         = realview_clcd_remove,
 461 };
 462
 463 #ifdef CONFIG_LEDS
 464 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 465
 466 void realview_leds_event(led_event_t ledevt)
 467 {
 468         unsigned long flags;
 469         u32 val;
 470
 471         local_irq_save(flags);
 472         val = readl(VA_LEDS_BASE);
 473
 474         switch (ledevt) {
 475         case led_idle_start:
 476                 val = val & ~REALVIEW_SYS_LED0;
 477                 break;
 478
 479         case led_idle_end:
 480                 val = val | REALVIEW_SYS_LED0;
 481                 break;
 482
 483         case led_timer:
 484                 val = val ^ REALVIEW_SYS_LED1;
 485                 break;
 486
 487         case led_halted:
 488                 val = 0;
 489                 break;
 490
 491         default:
 492                 break;
 493         }
 494
 495         writel(val, VA_LEDS_BASE);
 496         local_irq_restore(flags);
 497 }
 498 #endif  /* CONFIG_LEDS */
 499
 500 /*
 501  * Where is the timer (VA)?
 502  */
 503 void __iomem *timer0_va_base;
 504 void __iomem *timer1_va_base;
 505 void __iomem *timer2_va_base;
 506 void __iomem *timer3_va_base;
 507
 508 /*
 509  * How long is the timer interval?
 510  */
 511 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 512 #if TIMER_INTERVAL >= 0x100000
 513 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 514 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 515 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 516 #elif TIMER_INTERVAL >= 0x10000
 517 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 518 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 519 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 520 #else
 521 #define TIMER_RELOAD    (TIMER_INTERVAL)
 522 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 523 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 524 #endif
 525
 526 static void timer_set_mode(enum clock_event_mode mode,
 527                            struct clock_event_device *clk)
 528 {
 529         unsigned long ctrl;
 530
 531         switch(mode) {
 532         case CLOCK_EVT_MODE_PERIODIC:
 533                 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 534
 535                 ctrl = TIMER_CTRL_PERIODIC;
 536                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 537                 break;
 538         case CLOCK_EVT_MODE_ONESHOT:
 539                 /* period set, and timer enabled in 'next_event' hook */
 540                 ctrl = TIMER_CTRL_ONESHOT;
 541                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 542                 break;
 543         case CLOCK_EVT_MODE_UNUSED:
 544         case CLOCK_EVT_MODE_SHUTDOWN:
 545         default:
 546                 ctrl = 0;
 547         }
 548
 549         writel(ctrl, timer0_va_base + TIMER_CTRL);
 550 }
 551
 552 static int timer_set_next_event(unsigned long evt,
 553                                 struct clock_event_device *unused)
 554 {
 555         unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 556
 557         writel(evt, timer0_va_base + TIMER_LOAD);
 558         writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 559
 560         return 0;
 561 }
 562
 563 static struct clock_event_device timer0_clockevent =     {
 564         .name           = "timer0",
 565         .shift          = 32,
 566         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 567         .set_mode       = timer_set_mode,
 568         .set_next_event = timer_set_next_event,
 569         .rating         = 300,
 570         .cpumask        = CPU_MASK_ALL,
 571 };
 572
 573 static void __init realview_clockevents_init(unsigned int timer_irq)
 574 {
 575         timer0_clockevent.irq = timer_irq;
 576         timer0_clockevent.mult =
 577                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 578         timer0_clockevent.max_delta_ns =
 579                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 580         timer0_clockevent.min_delta_ns =
 581                 clockevent_delta2ns(0xf, &timer0_clockevent);
 582
 583         clockevents_register_device(&timer0_clockevent);
 584 }
 585
 586 /*
 587  * IRQ handler for the timer
 588  */
 589 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 590 {
 591         struct clock_event_device *evt = &timer0_clockevent;
 592
 593         /* clear the interrupt */
 594         writel(1, timer0_va_base + TIMER_INTCLR);
 595
 596         evt->event_handler(evt);
 597
 598         return IRQ_HANDLED;
 599 }
 600
 601 static struct irqaction realview_timer_irq = {
 602         .name           = "RealView Timer Tick",
 603         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 604         .handler        = realview_timer_interrupt,
 605 };
 606
 607 static cycle_t realview_get_cycles(void)
 608 {
 609         return ~readl(timer3_va_base + TIMER_VALUE);
 610 }
 611
 612 static struct clocksource clocksource_realview = {
 613         .name   = "timer3",
 614         .rating = 200,
 615         .read   = realview_get_cycles,
 616         .mask   = CLOCKSOURCE_MASK(32),
 617         .shift  = 20,
 618         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 619 };
 620
 621 static void __init realview_clocksource_init(void)
 622 {
 623         /* setup timer 0 as free-running clocksource */
 624         writel(0, timer3_va_base + TIMER_CTRL);
 625         writel(0xffffffff, timer3_va_base + TIMER_LOAD);
 626         writel(0xffffffff, timer3_va_base + TIMER_VALUE);
 627         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 628                 timer3_va_base + TIMER_CTRL);
 629
 630         clocksource_realview.mult =
 631                 clocksource_khz2mult(1000, clocksource_realview.shift);
 632         clocksource_register(&clocksource_realview);
 633 }
 634
 635 /*
 636  * Set up the clock source and clock events devices
 637  */
 638 void __init realview_timer_init(unsigned int timer_irq)
 639 {
 640         u32 val;
 641
 642 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 643         /*
 644          * The dummy clock device has to be registered before the main device
 645          * so that the latter will broadcast the clock events
 646          */
 647         local_timer_setup();
 648 #endif
 649
 650         /*
 651          * set clock frequency:
 652          *      REALVIEW_REFCLK is 32KHz
 653          *      REALVIEW_TIMCLK is 1MHz
 654          */
 655         val = readl(__io_address(REALVIEW_SCTL_BASE));
 656         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 657                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 658                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 659                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 660                __io_address(REALVIEW_SCTL_BASE));
 661
 662         /*
 663          * Initialise to a known state (all timers off)
 664          */
 665         writel(0, timer0_va_base + TIMER_CTRL);
 666         writel(0, timer1_va_base + TIMER_CTRL);
 667         writel(0, timer2_va_base + TIMER_CTRL);
 668         writel(0, timer3_va_base + TIMER_CTRL);
 669
 670         /*
 671          * Make irqs happen for the system timer
 672          */
 673         setup_irq(timer_irq, &realview_timer_irq);
 674
 675         realview_clocksource_init();
 676         realview_clockevents_init(timer_irq);
 677 }