git.oblomov.eu Git - linux-2.6/blob - drivers/dma/ioat_dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2007 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include "ioatdma.h"
  36 #include "ioatdma_registers.h"
  37 #include "ioatdma_hw.h"
  38
  39 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
  40 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  41 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  42 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
  43
  44 static int ioat_pending_level = 4;
  45 module_param(ioat_pending_level, int, 0644);
  46 MODULE_PARM_DESC(ioat_pending_level,
  47                  "high-water mark for pushing ioat descriptors (default: 4)");
  48
  49 /* internal functions */
  50 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
  51 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
  52
  53 static struct ioat_desc_sw *
  54 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
  55 static struct ioat_desc_sw *
  56 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
  57
  58 static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
  59                                                 struct ioatdma_device *device,
  60                                                 int index)
  61 {
  62         return device->idx[index];
  63 }
  64
  65 /**
  66  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  67  * @irq: interrupt id
  68  * @data: interrupt data
  69  */
  70 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  71 {
  72         struct ioatdma_device *instance = data;
  73         struct ioat_dma_chan *ioat_chan;
  74         unsigned long attnstatus;
  75         int bit;
  76         u8 intrctrl;
  77
  78         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  79
  80         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  81                 return IRQ_NONE;
  82
  83         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  84                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  85                 return IRQ_NONE;
  86         }
  87
  88         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  89         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
  90                 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
  91                 tasklet_schedule(&ioat_chan->cleanup_task);
  92         }
  93
  94         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  95         return IRQ_HANDLED;
  96 }
  97
  98 /**
  99  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
 100  * @irq: interrupt id
 101  * @data: interrupt data
 102  */
 103 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
 104 {
 105         struct ioat_dma_chan *ioat_chan = data;
 106
 107         tasklet_schedule(&ioat_chan->cleanup_task);
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static void ioat_dma_cleanup_tasklet(unsigned long data);
 113
 114 /**
 115  * ioat_dma_enumerate_channels - find and initialize the device's channels
 116  * @device: the device to be enumerated
 117  */
 118 static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
 119 {
 120         u8 xfercap_scale;
 121         u32 xfercap;
 122         int i;
 123         struct ioat_dma_chan *ioat_chan;
 124
 125         device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 126         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 127         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 128
 129         for (i = 0; i < device->common.chancnt; i++) {
 130                 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
 131                 if (!ioat_chan) {
 132                         device->common.chancnt = i;
 133                         break;
 134                 }
 135
 136                 ioat_chan->device = device;
 137                 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
 138                 ioat_chan->xfercap = xfercap;
 139                 ioat_chan->desccount = 0;
 140                 if (ioat_chan->device->version != IOAT_VER_1_2) {
 141                         writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
 142                                         | IOAT_DMA_DCA_ANY_CPU,
 143                                 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
 144                 }
 145                 spin_lock_init(&ioat_chan->cleanup_lock);
 146                 spin_lock_init(&ioat_chan->desc_lock);
 147                 INIT_LIST_HEAD(&ioat_chan->free_desc);
 148                 INIT_LIST_HEAD(&ioat_chan->used_desc);
 149                 /* This should be made common somewhere in dmaengine.c */
 150                 ioat_chan->common.device = &device->common;
 151                 list_add_tail(&ioat_chan->common.device_node,
 152                               &device->common.channels);
 153                 device->idx[i] = ioat_chan;
 154                 tasklet_init(&ioat_chan->cleanup_task,
 155                              ioat_dma_cleanup_tasklet,
 156                              (unsigned long) ioat_chan);
 157                 tasklet_disable(&ioat_chan->cleanup_task);
 158         }
 159         return device->common.chancnt;
 160 }
 161
 162 /**
 163  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 164  *                                 descriptors to hw
 165  * @chan: DMA channel handle
 166  */
 167 static inline void __ioat1_dma_memcpy_issue_pending(
 168                                                 struct ioat_dma_chan *ioat_chan)
 169 {
 170         ioat_chan->pending = 0;
 171         writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
 172 }
 173
 174 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 175 {
 176         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 177
 178         if (ioat_chan->pending != 0) {
 179                 spin_lock_bh(&ioat_chan->desc_lock);
 180                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
 181                 spin_unlock_bh(&ioat_chan->desc_lock);
 182         }
 183 }
 184
 185 static inline void __ioat2_dma_memcpy_issue_pending(
 186                                                 struct ioat_dma_chan *ioat_chan)
 187 {
 188         ioat_chan->pending = 0;
 189         writew(ioat_chan->dmacount,
 190                ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
 191 }
 192
 193 static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
 194 {
 195         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 196
 197         if (ioat_chan->pending != 0) {
 198                 spin_lock_bh(&ioat_chan->desc_lock);
 199                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
 200                 spin_unlock_bh(&ioat_chan->desc_lock);
 201         }
 202 }
 203
 204 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 205 {
 206         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
 207         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
 208         struct ioat_desc_sw *prev, *new;
 209         struct ioat_dma_descriptor *hw;
 210         dma_cookie_t cookie;
 211         LIST_HEAD(new_chain);
 212         u32 copy;
 213         size_t len;
 214         dma_addr_t src, dst;
 215         int orig_ack;
 216         unsigned int desc_count = 0;
 217
 218         /* src and dest and len are stored in the initial descriptor */
 219         len = first->len;
 220         src = first->src;
 221         dst = first->dst;
 222         orig_ack = first->async_tx.ack;
 223         new = first;
 224
 225         spin_lock_bh(&ioat_chan->desc_lock);
 226         prev = to_ioat_desc(ioat_chan->used_desc.prev);
 227         prefetch(prev->hw);
 228         do {
 229                 copy = min_t(size_t, len, ioat_chan->xfercap);
 230
 231                 new->async_tx.ack = 1;
 232
 233                 hw = new->hw;
 234                 hw->size = copy;
 235                 hw->ctl = 0;
 236                 hw->src_addr = src;
 237                 hw->dst_addr = dst;
 238                 hw->next = 0;
 239
 240                 /* chain together the physical address list for the HW */
 241                 wmb();
 242                 prev->hw->next = (u64) new->async_tx.phys;
 243
 244                 len -= copy;
 245                 dst += copy;
 246                 src += copy;
 247
 248                 list_add_tail(&new->node, &new_chain);
 249                 desc_count++;
 250                 prev = new;
 251         } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
 252
 253         hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
 254         if (new->async_tx.callback) {
 255                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
 256                 if (first != new) {
 257                         /* move callback into to last desc */
 258                         new->async_tx.callback = first->async_tx.callback;
 259                         new->async_tx.callback_param
 260                                         = first->async_tx.callback_param;
 261                         first->async_tx.callback = NULL;
 262                         first->async_tx.callback_param = NULL;
 263                 }
 264         }
 265
 266         new->tx_cnt = desc_count;
 267         new->async_tx.ack = orig_ack; /* client is in control of this ack */
 268
 269         /* store the original values for use in later cleanup */
 270         if (new != first) {
 271                 new->src = first->src;
 272                 new->dst = first->dst;
 273                 new->len = first->len;
 274         }
 275
 276         /* cookie incr and addition to used_list must be atomic */
 277         cookie = ioat_chan->common.cookie;
 278         cookie++;
 279         if (cookie < 0)
 280                 cookie = 1;
 281         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
 282
 283         /* write address into NextDescriptor field of last desc in chain */
 284         to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
 285                                                         first->async_tx.phys;
 286         __list_splice(&new_chain, ioat_chan->used_desc.prev);
 287
 288         ioat_chan->dmacount += desc_count;
 289         ioat_chan->pending += desc_count;
 290         if (ioat_chan->pending >= ioat_pending_level)
 291                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
 292         spin_unlock_bh(&ioat_chan->desc_lock);
 293
 294         return cookie;
 295 }
 296
 297 static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
 298 {
 299         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
 300         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
 301         struct ioat_desc_sw *new;
 302         struct ioat_dma_descriptor *hw;
 303         dma_cookie_t cookie;
 304         u32 copy;
 305         size_t len;
 306         dma_addr_t src, dst;
 307         int orig_ack;
 308         unsigned int desc_count = 0;
 309
 310         /* src and dest and len are stored in the initial descriptor */
 311         len = first->len;
 312         src = first->src;
 313         dst = first->dst;
 314         orig_ack = first->async_tx.ack;
 315         new = first;
 316
 317         /*
 318          * ioat_chan->desc_lock is still in force in version 2 path
 319          * it gets unlocked at end of this function
 320          */
 321         do {
 322                 copy = min_t(size_t, len, ioat_chan->xfercap);
 323
 324                 new->async_tx.ack = 1;
 325
 326                 hw = new->hw;
 327                 hw->size = copy;
 328                 hw->ctl = 0;
 329                 hw->src_addr = src;
 330                 hw->dst_addr = dst;
 331
 332                 len -= copy;
 333                 dst += copy;
 334                 src += copy;
 335                 desc_count++;
 336         } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
 337
 338         hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
 339         if (new->async_tx.callback) {
 340                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
 341                 if (first != new) {
 342                         /* move callback into to last desc */
 343                         new->async_tx.callback = first->async_tx.callback;
 344                         new->async_tx.callback_param
 345                                         = first->async_tx.callback_param;
 346                         first->async_tx.callback = NULL;
 347                         first->async_tx.callback_param = NULL;
 348                 }
 349         }
 350
 351         new->tx_cnt = desc_count;
 352         new->async_tx.ack = orig_ack; /* client is in control of this ack */
 353
 354         /* store the original values for use in later cleanup */
 355         if (new != first) {
 356                 new->src = first->src;
 357                 new->dst = first->dst;
 358                 new->len = first->len;
 359         }
 360
 361         /* cookie incr and addition to used_list must be atomic */
 362         cookie = ioat_chan->common.cookie;
 363         cookie++;
 364         if (cookie < 0)
 365                 cookie = 1;
 366         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
 367
 368         ioat_chan->dmacount += desc_count;
 369         ioat_chan->pending += desc_count;
 370         if (ioat_chan->pending >= ioat_pending_level)
 371                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
 372         spin_unlock_bh(&ioat_chan->desc_lock);
 373
 374         return cookie;
 375 }
 376
 377 /**
 378  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 379  * @ioat_chan: the channel supplying the memory pool for the descriptors
 380  * @flags: allocation flags
 381  */
 382 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
 383                                         struct ioat_dma_chan *ioat_chan,
 384                                         gfp_t flags)
 385 {
 386         struct ioat_dma_descriptor *desc;
 387         struct ioat_desc_sw *desc_sw;
 388         struct ioatdma_device *ioatdma_device;
 389         dma_addr_t phys;
 390
 391         ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
 392         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 393         if (unlikely(!desc))
 394                 return NULL;
 395
 396         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 397         if (unlikely(!desc_sw)) {
 398                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 399                 return NULL;
 400         }
 401
 402         memset(desc, 0, sizeof(*desc));
 403         dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
 404         switch (ioat_chan->device->version) {
 405         case IOAT_VER_1_2:
 406                 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
 407                 break;
 408         case IOAT_VER_2_0:
 409                 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
 410                 break;
 411         }
 412         INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
 413
 414         desc_sw->hw = desc;
 415         desc_sw->async_tx.phys = phys;
 416
 417         return desc_sw;
 418 }
 419
 420 static int ioat_initial_desc_count = 256;
 421 module_param(ioat_initial_desc_count, int, 0644);
 422 MODULE_PARM_DESC(ioat_initial_desc_count,
 423                  "initial descriptors per channel (default: 256)");
 424
 425 /**
 426  * ioat2_dma_massage_chan_desc - link the descriptors into a circle
 427  * @ioat_chan: the channel to be massaged
 428  */
 429 static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
 430 {
 431         struct ioat_desc_sw *desc, *_desc;
 432
 433         /* setup used_desc */
 434         ioat_chan->used_desc.next = ioat_chan->free_desc.next;
 435         ioat_chan->used_desc.prev = NULL;
 436
 437         /* pull free_desc out of the circle so that every node is a hw
 438          * descriptor, but leave it pointing to the list
 439          */
 440         ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
 441         ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
 442
 443         /* circle link the hw descriptors */
 444         desc = to_ioat_desc(ioat_chan->free_desc.next);
 445         desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
 446         list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
 447                 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
 448         }
 449 }
 450
 451 /**
 452  * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
 453  * @chan: the channel to be filled out
 454  */
 455 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
 456 {
 457         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 458         struct ioat_desc_sw *desc;
 459         u16 chanctrl;
 460         u32 chanerr;
 461         int i;
 462         LIST_HEAD(tmp_list);
 463
 464         /* have we already been set up? */
 465         if (!list_empty(&ioat_chan->free_desc))
 466                 return ioat_chan->desccount;
 467
 468         /* Setup register to interrupt and write completion status on error */
 469         chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
 470                 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
 471                 IOAT_CHANCTRL_ERR_COMPLETION_EN;
 472         writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
 473
 474         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 475         if (chanerr) {
 476                 dev_err(&ioat_chan->device->pdev->dev,
 477                         "CHANERR = %x, clearing\n", chanerr);
 478                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
 479         }
 480
 481         /* Allocate descriptors */
 482         for (i = 0; i < ioat_initial_desc_count; i++) {
 483                 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
 484                 if (!desc) {
 485                         dev_err(&ioat_chan->device->pdev->dev,
 486                                 "Only %d initial descriptors\n", i);
 487                         break;
 488                 }
 489                 list_add_tail(&desc->node, &tmp_list);
 490         }
 491         spin_lock_bh(&ioat_chan->desc_lock);
 492         ioat_chan->desccount = i;
 493         list_splice(&tmp_list, &ioat_chan->free_desc);
 494         if (ioat_chan->device->version != IOAT_VER_1_2)
 495                 ioat2_dma_massage_chan_desc(ioat_chan);
 496         spin_unlock_bh(&ioat_chan->desc_lock);
 497
 498         /* allocate a completion writeback area */
 499         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 500         ioat_chan->completion_virt =
 501                 pci_pool_alloc(ioat_chan->device->completion_pool,
 502                                GFP_KERNEL,
 503                                &ioat_chan->completion_addr);
 504         memset(ioat_chan->completion_virt, 0,
 505                sizeof(*ioat_chan->completion_virt));
 506         writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
 507                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 508         writel(((u64) ioat_chan->completion_addr) >> 32,
 509                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 510
 511         tasklet_enable(&ioat_chan->cleanup_task);
 512         ioat_dma_start_null_desc(ioat_chan);  /* give chain to dma device */
 513         return ioat_chan->desccount;
 514 }
 515
 516 /**
 517  * ioat_dma_free_chan_resources - release all the descriptors
 518  * @chan: the channel to be cleaned
 519  */
 520 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
 521 {
 522         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 523         struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
 524         struct ioat_desc_sw *desc, *_desc;
 525         int in_use_descs = 0;
 526
 527         tasklet_disable(&ioat_chan->cleanup_task);
 528         ioat_dma_memcpy_cleanup(ioat_chan);
 529
 530         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 531          * before removing DMA descriptor resources.
 532          */
 533         writeb(IOAT_CHANCMD_RESET,
 534                ioat_chan->reg_base
 535                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
 536         mdelay(100);
 537
 538         spin_lock_bh(&ioat_chan->desc_lock);
 539         switch (ioat_chan->device->version) {
 540         case IOAT_VER_1_2:
 541                 list_for_each_entry_safe(desc, _desc,
 542                                          &ioat_chan->used_desc, node) {
 543                         in_use_descs++;
 544                         list_del(&desc->node);
 545                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 546                                       desc->async_tx.phys);
 547                         kfree(desc);
 548                 }
 549                 list_for_each_entry_safe(desc, _desc,
 550                                          &ioat_chan->free_desc, node) {
 551                         list_del(&desc->node);
 552                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 553                                       desc->async_tx.phys);
 554                         kfree(desc);
 555                 }
 556                 break;
 557         case IOAT_VER_2_0:
 558                 list_for_each_entry_safe(desc, _desc,
 559                                          ioat_chan->free_desc.next, node) {
 560                         list_del(&desc->node);
 561                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 562                                       desc->async_tx.phys);
 563                         kfree(desc);
 564                 }
 565                 desc = to_ioat_desc(ioat_chan->free_desc.next);
 566                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 567                               desc->async_tx.phys);
 568                 kfree(desc);
 569                 INIT_LIST_HEAD(&ioat_chan->free_desc);
 570                 INIT_LIST_HEAD(&ioat_chan->used_desc);
 571                 break;
 572         }
 573         spin_unlock_bh(&ioat_chan->desc_lock);
 574
 575         pci_pool_free(ioatdma_device->completion_pool,
 576                       ioat_chan->completion_virt,
 577                       ioat_chan->completion_addr);
 578
 579         /* one is ok since we left it on there on purpose */
 580         if (in_use_descs > 1)
 581                 dev_err(&ioat_chan->device->pdev->dev,
 582                         "Freeing %d in use descriptors!\n",
 583                         in_use_descs - 1);
 584
 585         ioat_chan->last_completion = ioat_chan->completion_addr = 0;
 586         ioat_chan->pending = 0;
 587         ioat_chan->dmacount = 0;
 588 }
 589
 590 /**
 591  * ioat_dma_get_next_descriptor - return the next available descriptor
 592  * @ioat_chan: IOAT DMA channel handle
 593  *
 594  * Gets the next descriptor from the chain, and must be called with the
 595  * channel's desc_lock held.  Allocates more descriptors if the channel
 596  * has run out.
 597  */
 598 static struct ioat_desc_sw *
 599 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
 600 {
 601         struct ioat_desc_sw *new;
 602
 603         if (!list_empty(&ioat_chan->free_desc)) {
 604                 new = to_ioat_desc(ioat_chan->free_desc.next);
 605                 list_del(&new->node);
 606         } else {
 607                 /* try to get another desc */
 608                 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
 609                 if (!new) {
 610                         dev_err(&ioat_chan->device->pdev->dev,
 611                                 "alloc failed\n");
 612                         return NULL;
 613                 }
 614         }
 615
 616         prefetch(new->hw);
 617         return new;
 618 }
 619
 620 static struct ioat_desc_sw *
 621 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
 622 {
 623         struct ioat_desc_sw *new;
 624
 625         /*
 626          * used.prev points to where to start processing
 627          * used.next points to next free descriptor
 628          * if used.prev == NULL, there are none waiting to be processed
 629          * if used.next == used.prev.prev, there is only one free descriptor,
 630          *      and we need to use it to as a noop descriptor before
 631          *      linking in a new set of descriptors, since the device
 632          *      has probably already read the pointer to it
 633          */
 634         if (ioat_chan->used_desc.prev &&
 635             ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
 636
 637                 struct ioat_desc_sw *desc;
 638                 struct ioat_desc_sw *noop_desc;
 639                 int i;
 640
 641                 /* set up the noop descriptor */
 642                 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
 643                 noop_desc->hw->size = 0;
 644                 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
 645                 noop_desc->hw->src_addr = 0;
 646                 noop_desc->hw->dst_addr = 0;
 647
 648                 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
 649                 ioat_chan->pending++;
 650                 ioat_chan->dmacount++;
 651
 652                 /* try to get a few more descriptors */
 653                 for (i = 16; i; i--) {
 654                         desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
 655                         if (!desc) {
 656                                 dev_err(&ioat_chan->device->pdev->dev,
 657                                         "alloc failed\n");
 658                                 break;
 659                         }
 660                         list_add_tail(&desc->node, ioat_chan->used_desc.next);
 661
 662                         desc->hw->next
 663                                 = to_ioat_desc(desc->node.next)->async_tx.phys;
 664                         to_ioat_desc(desc->node.prev)->hw->next
 665                                 = desc->async_tx.phys;
 666                         ioat_chan->desccount++;
 667                 }
 668
 669                 ioat_chan->used_desc.next = noop_desc->node.next;
 670         }
 671         new = to_ioat_desc(ioat_chan->used_desc.next);
 672         prefetch(new);
 673         ioat_chan->used_desc.next = new->node.next;
 674
 675         if (ioat_chan->used_desc.prev == NULL)
 676                 ioat_chan->used_desc.prev = &new->node;
 677
 678         prefetch(new->hw);
 679         return new;
 680 }
 681
 682 static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
 683                                                 struct ioat_dma_chan *ioat_chan)
 684 {
 685         if (!ioat_chan)
 686                 return NULL;
 687
 688         switch (ioat_chan->device->version) {
 689         case IOAT_VER_1_2:
 690                 return ioat1_dma_get_next_descriptor(ioat_chan);
 691                 break;
 692         case IOAT_VER_2_0:
 693                 return ioat2_dma_get_next_descriptor(ioat_chan);
 694                 break;
 695         }
 696         return NULL;
 697 }
 698
 699 static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
 700                                                 struct dma_chan *chan,
 701                                                 dma_addr_t dma_dest,
 702                                                 dma_addr_t dma_src,
 703                                                 size_t len,
 704                                                 unsigned long flags)
 705 {
 706         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 707         struct ioat_desc_sw *new;
 708
 709         spin_lock_bh(&ioat_chan->desc_lock);
 710         new = ioat_dma_get_next_descriptor(ioat_chan);
 711         spin_unlock_bh(&ioat_chan->desc_lock);
 712
 713         if (new) {
 714                 new->len = len;
 715                 new->dst = dma_dest;
 716                 new->src = dma_src;
 717                 return &new->async_tx;
 718         } else
 719                 return NULL;
 720 }
 721
 722 static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
 723                                                 struct dma_chan *chan,
 724                                                 dma_addr_t dma_dest,
 725                                                 dma_addr_t dma_src,
 726                                                 size_t len,
 727                                                 unsigned long flags)
 728 {
 729         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 730         struct ioat_desc_sw *new;
 731
 732         spin_lock_bh(&ioat_chan->desc_lock);
 733         new = ioat2_dma_get_next_descriptor(ioat_chan);
 734
 735         /*
 736          * leave ioat_chan->desc_lock set in ioat 2 path
 737          * it will get unlocked at end of tx_submit
 738          */
 739
 740         if (new) {
 741                 new->len = len;
 742                 new->dst = dma_dest;
 743                 new->src = dma_src;
 744                 return &new->async_tx;
 745         } else
 746                 return NULL;
 747 }
 748
 749 static void ioat_dma_cleanup_tasklet(unsigned long data)
 750 {
 751         struct ioat_dma_chan *chan = (void *)data;
 752         ioat_dma_memcpy_cleanup(chan);
 753         writew(IOAT_CHANCTRL_INT_DISABLE,
 754                chan->reg_base + IOAT_CHANCTRL_OFFSET);
 755 }
 756
 757 /**
 758  * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
 759  * @chan: ioat channel to be cleaned up
 760  */
 761 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
 762 {
 763         unsigned long phys_complete;
 764         struct ioat_desc_sw *desc, *_desc;
 765         dma_cookie_t cookie = 0;
 766         unsigned long desc_phys;
 767         struct ioat_desc_sw *latest_desc;
 768
 769         prefetch(ioat_chan->completion_virt);
 770
 771         if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
 772                 return;
 773
 774         /* The completion writeback can happen at any time,
 775            so reads by the driver need to be atomic operations
 776            The descriptor physical addresses are limited to 32-bits
 777            when the CPU can only do a 32-bit mov */
 778
 779 #if (BITS_PER_LONG == 64)
 780         phys_complete =
 781                 ioat_chan->completion_virt->full
 782                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 783 #else
 784         phys_complete =
 785                 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
 786 #endif
 787
 788         if ((ioat_chan->completion_virt->full
 789                 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
 790                                 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
 791                 dev_err(&ioat_chan->device->pdev->dev,
 792                         "Channel halted, chanerr = %x\n",
 793                         readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
 794
 795                 /* TODO do something to salvage the situation */
 796         }
 797
 798         if (phys_complete == ioat_chan->last_completion) {
 799                 spin_unlock_bh(&ioat_chan->cleanup_lock);
 800                 return;
 801         }
 802
 803         cookie = 0;
 804         spin_lock_bh(&ioat_chan->desc_lock);
 805         switch (ioat_chan->device->version) {
 806         case IOAT_VER_1_2:
 807                 list_for_each_entry_safe(desc, _desc,
 808                                          &ioat_chan->used_desc, node) {
 809
 810                         /*
 811                          * Incoming DMA requests may use multiple descriptors,
 812                          * due to exceeding xfercap, perhaps. If so, only the
 813                          * last one will have a cookie, and require unmapping.
 814                          */
 815                         if (desc->async_tx.cookie) {
 816                                 cookie = desc->async_tx.cookie;
 817
 818                                 /*
 819                                  * yes we are unmapping both _page and _single
 820                                  * alloc'd regions with unmap_page. Is this
 821                                  * *really* that bad?
 822                                  */
 823                                 pci_unmap_page(ioat_chan->device->pdev,
 824                                                 pci_unmap_addr(desc, dst),
 825                                                 pci_unmap_len(desc, len),
 826                                                 PCI_DMA_FROMDEVICE);
 827                                 pci_unmap_page(ioat_chan->device->pdev,
 828                                                 pci_unmap_addr(desc, src),
 829                                                 pci_unmap_len(desc, len),
 830                                                 PCI_DMA_TODEVICE);
 831
 832                                 if (desc->async_tx.callback) {
 833                                         desc->async_tx.callback(desc->async_tx.callback_param);
 834                                         desc->async_tx.callback = NULL;
 835                                 }
 836                         }
 837
 838                         if (desc->async_tx.phys != phys_complete) {
 839                                 /*
 840                                  * a completed entry, but not the last, so clean
 841                                  * up if the client is done with the descriptor
 842                                  */
 843                                 if (desc->async_tx.ack) {
 844                                         list_del(&desc->node);
 845                                         list_add_tail(&desc->node,
 846                                                       &ioat_chan->free_desc);
 847                                 } else
 848                                         desc->async_tx.cookie = 0;
 849                         } else {
 850                                 /*
 851                                  * last used desc. Do not remove, so we can
 852                                  * append from it, but don't look at it next
 853                                  * time, either
 854                                  */
 855                                 desc->async_tx.cookie = 0;
 856
 857                                 /* TODO check status bits? */
 858                                 break;
 859                         }
 860                 }
 861                 break;
 862         case IOAT_VER_2_0:
 863                 /* has some other thread has already cleaned up? */
 864                 if (ioat_chan->used_desc.prev == NULL)
 865                         break;
 866
 867                 /* work backwards to find latest finished desc */
 868                 desc = to_ioat_desc(ioat_chan->used_desc.next);
 869                 latest_desc = NULL;
 870                 do {
 871                         desc = to_ioat_desc(desc->node.prev);
 872                         desc_phys = (unsigned long)desc->async_tx.phys
 873                                        & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 874                         if (desc_phys == phys_complete) {
 875                                 latest_desc = desc;
 876                                 break;
 877                         }
 878                 } while (&desc->node != ioat_chan->used_desc.prev);
 879
 880                 if (latest_desc != NULL) {
 881
 882                         /* work forwards to clear finished descriptors */
 883                         for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
 884                              &desc->node != latest_desc->node.next &&
 885                              &desc->node != ioat_chan->used_desc.next;
 886                              desc = to_ioat_desc(desc->node.next)) {
 887                                 if (desc->async_tx.cookie) {
 888                                         cookie = desc->async_tx.cookie;
 889                                         desc->async_tx.cookie = 0;
 890
 891                                         pci_unmap_page(ioat_chan->device->pdev,
 892                                                       pci_unmap_addr(desc, dst),
 893                                                       pci_unmap_len(desc, len),
 894                                                       PCI_DMA_FROMDEVICE);
 895                                         pci_unmap_page(ioat_chan->device->pdev,
 896                                                       pci_unmap_addr(desc, src),
 897                                                       pci_unmap_len(desc, len),
 898                                                       PCI_DMA_TODEVICE);
 899
 900                                         if (desc->async_tx.callback) {
 901                                                 desc->async_tx.callback(desc->async_tx.callback_param);
 902                                                 desc->async_tx.callback = NULL;
 903                                         }
 904                                 }
 905                         }
 906
 907                         /* move used.prev up beyond those that are finished */
 908                         if (&desc->node == ioat_chan->used_desc.next)
 909                                 ioat_chan->used_desc.prev = NULL;
 910                         else
 911                                 ioat_chan->used_desc.prev = &desc->node;
 912                 }
 913                 break;
 914         }
 915
 916         spin_unlock_bh(&ioat_chan->desc_lock);
 917
 918         ioat_chan->last_completion = phys_complete;
 919         if (cookie != 0)
 920                 ioat_chan->completed_cookie = cookie;
 921
 922         spin_unlock_bh(&ioat_chan->cleanup_lock);
 923 }
 924
 925 static void ioat_dma_dependency_added(struct dma_chan *chan)
 926 {
 927         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 928         spin_lock_bh(&ioat_chan->desc_lock);
 929         if (ioat_chan->pending == 0) {
 930                 spin_unlock_bh(&ioat_chan->desc_lock);
 931                 ioat_dma_memcpy_cleanup(ioat_chan);
 932         } else
 933                 spin_unlock_bh(&ioat_chan->desc_lock);
 934 }
 935
 936 /**
 937  * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
 938  * @chan: IOAT DMA channel handle
 939  * @cookie: DMA transaction identifier
 940  * @done: if not %NULL, updated with last completed transaction
 941  * @used: if not %NULL, updated with last used transaction
 942  */
 943 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
 944                                             dma_cookie_t cookie,
 945                                             dma_cookie_t *done,
 946                                             dma_cookie_t *used)
 947 {
 948         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 949         dma_cookie_t last_used;
 950         dma_cookie_t last_complete;
 951         enum dma_status ret;
 952
 953         last_used = chan->cookie;
 954         last_complete = ioat_chan->completed_cookie;
 955
 956         if (done)
 957                 *done = last_complete;
 958         if (used)
 959                 *used = last_used;
 960
 961         ret = dma_async_is_complete(cookie, last_complete, last_used);
 962         if (ret == DMA_SUCCESS)
 963                 return ret;
 964
 965         ioat_dma_memcpy_cleanup(ioat_chan);
 966
 967         last_used = chan->cookie;
 968         last_complete = ioat_chan->completed_cookie;
 969
 970         if (done)
 971                 *done = last_complete;
 972         if (used)
 973                 *used = last_used;
 974
 975         return dma_async_is_complete(cookie, last_complete, last_used);
 976 }
 977
 978 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
 979 {
 980         struct ioat_desc_sw *desc;
 981
 982         spin_lock_bh(&ioat_chan->desc_lock);
 983
 984         desc = ioat_dma_get_next_descriptor(ioat_chan);
 985         desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
 986                                 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
 987                                 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
 988         desc->hw->size = 0;
 989         desc->hw->src_addr = 0;
 990         desc->hw->dst_addr = 0;
 991         desc->async_tx.ack = 1;
 992         switch (ioat_chan->device->version) {
 993         case IOAT_VER_1_2:
 994                 desc->hw->next = 0;
 995                 list_add_tail(&desc->node, &ioat_chan->used_desc);
 996
 997                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
 998                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 999                 writel(((u64) desc->async_tx.phys) >> 32,
1000                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1001
1002                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1003                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1004                 break;
1005         case IOAT_VER_2_0:
1006                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1007                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1008                 writel(((u64) desc->async_tx.phys) >> 32,
1009                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1010
1011                 ioat_chan->dmacount++;
1012                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1013                 break;
1014         }
1015         spin_unlock_bh(&ioat_chan->desc_lock);
1016 }
1017
1018 /*
1019  * Perform a IOAT transaction to verify the HW works.
1020  */
1021 #define IOAT_TEST_SIZE 2000
1022
1023 static void ioat_dma_test_callback(void *dma_async_param)
1024 {
1025         printk(KERN_ERR "ioatdma: ioat_dma_test_callback(%p)\n",
1026                 dma_async_param);
1027 }
1028
1029 /**
1030  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1031  * @device: device to be tested
1032  */
1033 static int ioat_dma_self_test(struct ioatdma_device *device)
1034 {
1035         int i;
1036         u8 *src;
1037         u8 *dest;
1038         struct dma_chan *dma_chan;
1039         struct dma_async_tx_descriptor *tx;
1040         dma_addr_t dma_dest, dma_src;
1041         dma_cookie_t cookie;
1042         int err = 0;
1043
1044         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1045         if (!src)
1046                 return -ENOMEM;
1047         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1048         if (!dest) {
1049                 kfree(src);
1050                 return -ENOMEM;
1051         }
1052
1053         /* Fill in src buffer */
1054         for (i = 0; i < IOAT_TEST_SIZE; i++)
1055                 src[i] = (u8)i;
1056
1057         /* Start copy, using first DMA channel */
1058         dma_chan = container_of(device->common.channels.next,
1059                                 struct dma_chan,
1060                                 device_node);
1061         if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
1062                 dev_err(&device->pdev->dev,
1063                         "selftest cannot allocate chan resource\n");
1064                 err = -ENODEV;
1065                 goto out;
1066         }
1067
1068         dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1069                                  DMA_TO_DEVICE);
1070         dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1071                                   DMA_FROM_DEVICE);
1072         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1073                                                    IOAT_TEST_SIZE, 0);
1074         if (!tx) {
1075                 dev_err(&device->pdev->dev,
1076                         "Self-test prep failed, disabling\n");
1077                 err = -ENODEV;
1078                 goto free_resources;
1079         }
1080
1081         async_tx_ack(tx);
1082         tx->callback = ioat_dma_test_callback;
1083         tx->callback_param = (void *)0x8086;
1084         cookie = tx->tx_submit(tx);
1085         if (cookie < 0) {
1086                 dev_err(&device->pdev->dev,
1087                         "Self-test setup failed, disabling\n");
1088                 err = -ENODEV;
1089                 goto free_resources;
1090         }
1091         device->common.device_issue_pending(dma_chan);
1092         msleep(1);
1093
1094         if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
1095                                         != DMA_SUCCESS) {
1096                 dev_err(&device->pdev->dev,
1097                         "Self-test copy timed out, disabling\n");
1098                 err = -ENODEV;
1099                 goto free_resources;
1100         }
1101         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1102                 dev_err(&device->pdev->dev,
1103                         "Self-test copy failed compare, disabling\n");
1104                 err = -ENODEV;
1105                 goto free_resources;
1106         }
1107
1108 free_resources:
1109         device->common.device_free_chan_resources(dma_chan);
1110 out:
1111         kfree(src);
1112         kfree(dest);
1113         return err;
1114 }
1115
1116 static char ioat_interrupt_style[32] = "msix";
1117 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1118                     sizeof(ioat_interrupt_style), 0644);
1119 MODULE_PARM_DESC(ioat_interrupt_style,
1120                  "set ioat interrupt style: msix (default), "
1121                  "msix-single-vector, msi, intx)");
1122
1123 /**
1124  * ioat_dma_setup_interrupts - setup interrupt handler
1125  * @device: ioat device
1126  */
1127 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1128 {
1129         struct ioat_dma_chan *ioat_chan;
1130         int err, i, j, msixcnt;
1131         u8 intrctrl = 0;
1132
1133         if (!strcmp(ioat_interrupt_style, "msix"))
1134                 goto msix;
1135         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1136                 goto msix_single_vector;
1137         if (!strcmp(ioat_interrupt_style, "msi"))
1138                 goto msi;
1139         if (!strcmp(ioat_interrupt_style, "intx"))
1140                 goto intx;
1141         dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1142                 ioat_interrupt_style);
1143         goto err_no_irq;
1144
1145 msix:
1146         /* The number of MSI-X vectors should equal the number of channels */
1147         msixcnt = device->common.chancnt;
1148         for (i = 0; i < msixcnt; i++)
1149                 device->msix_entries[i].entry = i;
1150
1151         err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1152         if (err < 0)
1153                 goto msi;
1154         if (err > 0)
1155                 goto msix_single_vector;
1156
1157         for (i = 0; i < msixcnt; i++) {
1158                 ioat_chan = ioat_lookup_chan_by_index(device, i);
1159                 err = request_irq(device->msix_entries[i].vector,
1160                                   ioat_dma_do_interrupt_msix,
1161                                   0, "ioat-msix", ioat_chan);
1162                 if (err) {
1163                         for (j = 0; j < i; j++) {
1164                                 ioat_chan =
1165                                         ioat_lookup_chan_by_index(device, j);
1166                                 free_irq(device->msix_entries[j].vector,
1167                                          ioat_chan);
1168                         }
1169                         goto msix_single_vector;
1170                 }
1171         }
1172         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1173         device->irq_mode = msix_multi_vector;
1174         goto done;
1175
1176 msix_single_vector:
1177         device->msix_entries[0].entry = 0;
1178         err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1179         if (err)
1180                 goto msi;
1181
1182         err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1183                           0, "ioat-msix", device);
1184         if (err) {
1185                 pci_disable_msix(device->pdev);
1186                 goto msi;
1187         }
1188         device->irq_mode = msix_single_vector;
1189         goto done;
1190
1191 msi:
1192         err = pci_enable_msi(device->pdev);
1193         if (err)
1194                 goto intx;
1195
1196         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1197                           0, "ioat-msi", device);
1198         if (err) {
1199                 pci_disable_msi(device->pdev);
1200                 goto intx;
1201         }
1202         /*
1203          * CB 1.2 devices need a bit set in configuration space to enable MSI
1204          */
1205         if (device->version == IOAT_VER_1_2) {
1206                 u32 dmactrl;
1207                 pci_read_config_dword(device->pdev,
1208                                       IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1209                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1210                 pci_write_config_dword(device->pdev,
1211                                        IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1212         }
1213         device->irq_mode = msi;
1214         goto done;
1215
1216 intx:
1217         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1218                           IRQF_SHARED, "ioat-intx", device);
1219         if (err)
1220                 goto err_no_irq;
1221         device->irq_mode = intx;
1222
1223 done:
1224         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1225         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1226         return 0;
1227
1228 err_no_irq:
1229         /* Disable all interrupt generation */
1230         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1231         dev_err(&device->pdev->dev, "no usable interrupts\n");
1232         device->irq_mode = none;
1233         return -1;
1234 }
1235
1236 /**
1237  * ioat_dma_remove_interrupts - remove whatever interrupts were set
1238  * @device: ioat device
1239  */
1240 static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1241 {
1242         struct ioat_dma_chan *ioat_chan;
1243         int i;
1244
1245         /* Disable all interrupt generation */
1246         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1247
1248         switch (device->irq_mode) {
1249         case msix_multi_vector:
1250                 for (i = 0; i < device->common.chancnt; i++) {
1251                         ioat_chan = ioat_lookup_chan_by_index(device, i);
1252                         free_irq(device->msix_entries[i].vector, ioat_chan);
1253                 }
1254                 pci_disable_msix(device->pdev);
1255                 break;
1256         case msix_single_vector:
1257                 free_irq(device->msix_entries[0].vector, device);
1258                 pci_disable_msix(device->pdev);
1259                 break;
1260         case msi:
1261                 free_irq(device->pdev->irq, device);
1262                 pci_disable_msi(device->pdev);
1263                 break;
1264         case intx:
1265                 free_irq(device->pdev->irq, device);
1266                 break;
1267         case none:
1268                 dev_warn(&device->pdev->dev,
1269                          "call to %s without interrupts setup\n", __func__);
1270         }
1271         device->irq_mode = none;
1272 }
1273
1274 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1275                                       void __iomem *iobase)
1276 {
1277         int err;
1278         struct ioatdma_device *device;
1279
1280         device = kzalloc(sizeof(*device), GFP_KERNEL);
1281         if (!device) {
1282                 err = -ENOMEM;
1283                 goto err_kzalloc;
1284         }
1285         device->pdev = pdev;
1286         device->reg_base = iobase;
1287         device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1288
1289         /* DMA coherent memory pool for DMA descriptor allocations */
1290         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1291                                            sizeof(struct ioat_dma_descriptor),
1292                                            64, 0);
1293         if (!device->dma_pool) {
1294                 err = -ENOMEM;
1295                 goto err_dma_pool;
1296         }
1297
1298         device->completion_pool = pci_pool_create("completion_pool", pdev,
1299                                                   sizeof(u64), SMP_CACHE_BYTES,
1300                                                   SMP_CACHE_BYTES);
1301         if (!device->completion_pool) {
1302                 err = -ENOMEM;
1303                 goto err_completion_pool;
1304         }
1305
1306         INIT_LIST_HEAD(&device->common.channels);
1307         ioat_dma_enumerate_channels(device);
1308
1309         device->common.device_alloc_chan_resources =
1310                                                 ioat_dma_alloc_chan_resources;
1311         device->common.device_free_chan_resources =
1312                                                 ioat_dma_free_chan_resources;
1313         device->common.dev = &pdev->dev;
1314
1315         dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1316         device->common.device_is_tx_complete = ioat_dma_is_complete;
1317         device->common.device_dependency_added = ioat_dma_dependency_added;
1318         switch (device->version) {
1319         case IOAT_VER_1_2:
1320                 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1321                 device->common.device_issue_pending =
1322                                                 ioat1_dma_memcpy_issue_pending;
1323                 break;
1324         case IOAT_VER_2_0:
1325                 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1326                 device->common.device_issue_pending =
1327                                                 ioat2_dma_memcpy_issue_pending;
1328                 break;
1329         }
1330
1331         dev_err(&device->pdev->dev,
1332                 "Intel(R) I/OAT DMA Engine found,"
1333                 " %d channels, device version 0x%02x, driver version %s\n",
1334                 device->common.chancnt, device->version, IOAT_DMA_VERSION);
1335
1336         err = ioat_dma_setup_interrupts(device);
1337         if (err)
1338                 goto err_setup_interrupts;
1339
1340         err = ioat_dma_self_test(device);
1341         if (err)
1342                 goto err_self_test;
1343
1344         dma_async_device_register(&device->common);
1345
1346         return device;
1347
1348 err_self_test:
1349         ioat_dma_remove_interrupts(device);
1350 err_setup_interrupts:
1351         pci_pool_destroy(device->completion_pool);
1352 err_completion_pool:
1353         pci_pool_destroy(device->dma_pool);
1354 err_dma_pool:
1355         kfree(device);
1356 err_kzalloc:
1357         dev_err(&pdev->dev,
1358                 "Intel(R) I/OAT DMA Engine initialization failed\n");
1359         return NULL;
1360 }
1361
1362 void ioat_dma_remove(struct ioatdma_device *device)
1363 {
1364         struct dma_chan *chan, *_chan;
1365         struct ioat_dma_chan *ioat_chan;
1366
1367         ioat_dma_remove_interrupts(device);
1368
1369         dma_async_device_unregister(&device->common);
1370
1371         pci_pool_destroy(device->dma_pool);
1372         pci_pool_destroy(device->completion_pool);
1373
1374         iounmap(device->reg_base);
1375         pci_release_regions(device->pdev);
1376         pci_disable_device(device->pdev);
1377
1378         list_for_each_entry_safe(chan, _chan,
1379                                  &device->common.channels, device_node) {
1380                 ioat_chan = to_ioat_chan(chan);
1381                 list_del(&chan->device_node);
1382                 kfree(ioat_chan);
1383         }
1384         kfree(device);
1385 }
1386