2 * MPC8541 CDS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "MPC8541CDS", "MPC85xxCDS";
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
61 memory-controller@2000 {
62 compatible = "fsl,8541-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8541-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>;
81 compatible = "fsl-i2c";
84 interrupt-parent = <&mpic>;
91 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
93 ranges = <0x0 0x21100 0x200>;
96 compatible = "fsl,mpc8541-dma-channel",
97 "fsl,eloplus-dma-channel";
100 interrupt-parent = <&mpic>;
104 compatible = "fsl,mpc8541-dma-channel",
105 "fsl,eloplus-dma-channel";
108 interrupt-parent = <&mpic>;
112 compatible = "fsl,mpc8541-dma-channel",
113 "fsl,eloplus-dma-channel";
116 interrupt-parent = <&mpic>;
120 compatible = "fsl,mpc8541-dma-channel",
121 "fsl,eloplus-dma-channel";
124 interrupt-parent = <&mpic>;
130 #address-cells = <1>;
132 compatible = "fsl,gianfar-mdio";
133 reg = <0x24520 0x20>;
135 phy0: ethernet-phy@0 {
136 interrupt-parent = <&mpic>;
139 device_type = "ethernet-phy";
141 phy1: ethernet-phy@1 {
142 interrupt-parent = <&mpic>;
145 device_type = "ethernet-phy";
149 device_type = "tbi-phy";
154 #address-cells = <1>;
156 compatible = "fsl,gianfar-tbi";
157 reg = <0x25520 0x20>;
161 device_type = "tbi-phy";
165 enet0: ethernet@24000 {
167 device_type = "network";
169 compatible = "gianfar";
170 reg = <0x24000 0x1000>;
171 local-mac-address = [ 00 00 00 00 00 00 ];
172 interrupts = <29 2 30 2 34 2>;
173 interrupt-parent = <&mpic>;
174 tbi-handle = <&tbi0>;
175 phy-handle = <&phy0>;
178 enet1: ethernet@25000 {
180 device_type = "network";
182 compatible = "gianfar";
183 reg = <0x25000 0x1000>;
184 local-mac-address = [ 00 00 00 00 00 00 ];
185 interrupts = <35 2 36 2 40 2>;
186 interrupt-parent = <&mpic>;
187 tbi-handle = <&tbi1>;
188 phy-handle = <&phy1>;
191 serial0: serial@4500 {
193 device_type = "serial";
194 compatible = "ns16550";
195 reg = <0x4500 0x100>; // reg base, size
196 clock-frequency = <0>; // should we fill in in uboot?
198 interrupt-parent = <&mpic>;
201 serial1: serial@4600 {
203 device_type = "serial";
204 compatible = "ns16550";
205 reg = <0x4600 0x100>; // reg base, size
206 clock-frequency = <0>; // should we fill in in uboot?
208 interrupt-parent = <&mpic>;
212 compatible = "fsl,sec2.0";
213 reg = <0x30000 0x10000>;
215 interrupt-parent = <&mpic>;
216 fsl,num-channels = <4>;
217 fsl,channel-fifo-len = <24>;
218 fsl,exec-units-mask = <0x7e>;
219 fsl,descriptor-types-mask = <0x01010ebf>;
223 interrupt-controller;
224 #address-cells = <0>;
225 #interrupt-cells = <2>;
226 reg = <0x40000 0x40000>;
227 compatible = "chrp,open-pic";
228 device_type = "open-pic";
232 #address-cells = <1>;
234 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
235 reg = <0x919c0 0x30>;
239 #address-cells = <1>;
241 ranges = <0x0 0x80000 0x10000>;
244 compatible = "fsl,cpm-muram-data";
245 reg = <0x0 0x2000 0x9000 0x1000>;
250 compatible = "fsl,mpc8541-brg",
253 reg = <0x919f0 0x10 0x915f0 0x10>;
257 interrupt-controller;
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
261 interrupt-parent = <&mpic>;
262 reg = <0x90c00 0x80>;
263 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
270 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
274 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
280 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
281 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
282 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
283 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
285 /* IDSEL 0x12 (Slot 1) */
286 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
287 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
288 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
289 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
291 /* IDSEL 0x13 (Slot 2) */
292 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
293 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
294 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
295 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
297 /* IDSEL 0x14 (Slot 3) */
298 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
299 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
300 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
301 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
303 /* IDSEL 0x15 (Slot 4) */
304 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
305 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
306 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
307 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
309 /* Bus 1 (Tundra Bridge) */
310 /* IDSEL 0x12 (ISA bridge) */
311 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
312 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
313 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
314 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
315 interrupt-parent = <&mpic>;
318 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
319 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
320 clock-frequency = <66666666>;
321 #interrupt-cells = <1>;
323 #address-cells = <3>;
324 reg = <0xe0008000 0x1000>;
325 compatible = "fsl,mpc8540-pci";
329 interrupt-controller;
330 device_type = "interrupt-controller";
331 reg = <0x19000 0x0 0x0 0x0 0x1>;
332 #address-cells = <0>;
333 #interrupt-cells = <2>;
334 compatible = "chrp,iic";
336 interrupt-parent = <&pci0>;
342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
346 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
347 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
348 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
349 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
350 interrupt-parent = <&mpic>;
353 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
354 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
355 clock-frequency = <66666666>;
356 #interrupt-cells = <1>;
358 #address-cells = <3>;
359 reg = <0xe0009000 0x1000>;
360 compatible = "fsl,mpc8540-pci";