git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/i2c-id.h>
  28 #include <linux/init.h>
  29 #include <linux/time.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/delay.h>
  32 #include <linux/errno.h>
  33 #include <linux/err.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40
  41 #include <plat/regs-iic.h>
  42 #include <plat/iic.h>
  43
  44 /* i2c controller state */
  45
  46 enum s3c24xx_i2c_state {
  47         STATE_IDLE,
  48         STATE_START,
  49         STATE_READ,
  50         STATE_WRITE,
  51         STATE_STOP
  52 };
  53
  54 struct s3c24xx_i2c {
  55         spinlock_t              lock;
  56         wait_queue_head_t       wait;
  57         unsigned int            suspended:1;
  58
  59         struct i2c_msg          *msg;
  60         unsigned int            msg_num;
  61         unsigned int            msg_idx;
  62         unsigned int            msg_ptr;
  63
  64         unsigned int            tx_setup;
  65         unsigned int            irq;
  66
  67         enum s3c24xx_i2c_state  state;
  68         unsigned long           clkrate;
  69
  70         void __iomem            *regs;
  71         struct clk              *clk;
  72         struct device           *dev;
  73         struct resource         *ioarea;
  74         struct i2c_adapter      adap;
  75
  76 #ifdef CONFIG_CPU_FREQ
  77         struct notifier_block   freq_transition;
  78 #endif
  79 };
  80
  81 /* default platform data removed, dev should always carry data. */
  82
  83 /* s3c24xx_i2c_is2440()
  84  *
  85  * return true is this is an s3c2440
  86 */
  87
  88 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  89 {
  90         struct platform_device *pdev = to_platform_device(i2c->dev);
  91
  92         return !strcmp(pdev->name, "s3c2440-i2c");
  93 }
  94
  95 /* s3c24xx_i2c_master_complete
  96  *
  97  * complete the message and wake up the caller, using the given return code,
  98  * or zero to mean ok.
  99 */
 100
 101 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 102 {
 103         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 104
 105         i2c->msg_ptr = 0;
 106         i2c->msg = NULL;
 107         i2c->msg_idx++;
 108         i2c->msg_num = 0;
 109         if (ret)
 110                 i2c->msg_idx = ret;
 111
 112         wake_up(&i2c->wait);
 113 }
 114
 115 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 116 {
 117         unsigned long tmp;
 118
 119         tmp = readl(i2c->regs + S3C2410_IICCON);
 120         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 121 }
 122
 123 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 124 {
 125         unsigned long tmp;
 126
 127         tmp = readl(i2c->regs + S3C2410_IICCON);
 128         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 129 }
 130
 131 /* irq enable/disable functions */
 132
 133 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 134 {
 135         unsigned long tmp;
 136
 137         tmp = readl(i2c->regs + S3C2410_IICCON);
 138         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 139 }
 140
 141 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 142 {
 143         unsigned long tmp;
 144
 145         tmp = readl(i2c->regs + S3C2410_IICCON);
 146         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 147 }
 148
 149
 150 /* s3c24xx_i2c_message_start
 151  *
 152  * put the start of a message onto the bus
 153 */
 154
 155 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 156                                       struct i2c_msg *msg)
 157 {
 158         unsigned int addr = (msg->addr & 0x7f) << 1;
 159         unsigned long stat;
 160         unsigned long iiccon;
 161
 162         stat = 0;
 163         stat |=  S3C2410_IICSTAT_TXRXEN;
 164
 165         if (msg->flags & I2C_M_RD) {
 166                 stat |= S3C2410_IICSTAT_MASTER_RX;
 167                 addr |= 1;
 168         } else
 169                 stat |= S3C2410_IICSTAT_MASTER_TX;
 170
 171         if (msg->flags & I2C_M_REV_DIR_ADDR)
 172                 addr ^= 1;
 173
 174         /* todo - check for wether ack wanted or not */
 175         s3c24xx_i2c_enable_ack(i2c);
 176
 177         iiccon = readl(i2c->regs + S3C2410_IICCON);
 178         writel(stat, i2c->regs + S3C2410_IICSTAT);
 179
 180         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 181         writeb(addr, i2c->regs + S3C2410_IICDS);
 182
 183         /* delay here to ensure the data byte has gotten onto the bus
 184          * before the transaction is started */
 185
 186         ndelay(i2c->tx_setup);
 187
 188         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 189         writel(iiccon, i2c->regs + S3C2410_IICCON);
 190
 191         stat |= S3C2410_IICSTAT_START;
 192         writel(stat, i2c->regs + S3C2410_IICSTAT);
 193 }
 194
 195 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 196 {
 197         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 198
 199         dev_dbg(i2c->dev, "STOP\n");
 200
 201         /* stop the transfer */
 202         iicstat &= ~S3C2410_IICSTAT_START;
 203         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 204
 205         i2c->state = STATE_STOP;
 206
 207         s3c24xx_i2c_master_complete(i2c, ret);
 208         s3c24xx_i2c_disable_irq(i2c);
 209 }
 210
 211 /* helper functions to determine the current state in the set of
 212  * messages we are sending */
 213
 214 /* is_lastmsg()
 215  *
 216  * returns TRUE if the current message is the last in the set
 217 */
 218
 219 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 220 {
 221         return i2c->msg_idx >= (i2c->msg_num - 1);
 222 }
 223
 224 /* is_msglast
 225  *
 226  * returns TRUE if we this is the last byte in the current message
 227 */
 228
 229 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 230 {
 231         return i2c->msg_ptr == i2c->msg->len-1;
 232 }
 233
 234 /* is_msgend
 235  *
 236  * returns TRUE if we reached the end of the current message
 237 */
 238
 239 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 240 {
 241         return i2c->msg_ptr >= i2c->msg->len;
 242 }
 243
 244 /* i2s_s3c_irq_nextbyte
 245  *
 246  * process an interrupt and work out what to do
 247  */
 248
 249 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 250 {
 251         unsigned long tmp;
 252         unsigned char byte;
 253         int ret = 0;
 254
 255         switch (i2c->state) {
 256
 257         case STATE_IDLE:
 258                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 259                 goto out;
 260                 break;
 261
 262         case STATE_STOP:
 263                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 264                 s3c24xx_i2c_disable_irq(i2c);
 265                 goto out_ack;
 266
 267         case STATE_START:
 268                 /* last thing we did was send a start condition on the
 269                  * bus, or started a new i2c message
 270                  */
 271
 272                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 273                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 274                         /* ack was not received... */
 275
 276                         dev_dbg(i2c->dev, "ack was not received\n");
 277                         s3c24xx_i2c_stop(i2c, -ENXIO);
 278                         goto out_ack;
 279                 }
 280
 281                 if (i2c->msg->flags & I2C_M_RD)
 282                         i2c->state = STATE_READ;
 283                 else
 284                         i2c->state = STATE_WRITE;
 285
 286                 /* terminate the transfer if there is nothing to do
 287                  * as this is used by the i2c probe to find devices. */
 288
 289                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 290                         s3c24xx_i2c_stop(i2c, 0);
 291                         goto out_ack;
 292                 }
 293
 294                 if (i2c->state == STATE_READ)
 295                         goto prepare_read;
 296
 297                 /* fall through to the write state, as we will need to
 298                  * send a byte as well */
 299
 300         case STATE_WRITE:
 301                 /* we are writing data to the device... check for the
 302                  * end of the message, and if so, work out what to do
 303                  */
 304
 305                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 306                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 307                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 308
 309                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 310                                 goto out_ack;
 311                         }
 312                 }
 313
 314  retry_write:
 315
 316                 if (!is_msgend(i2c)) {
 317                         byte = i2c->msg->buf[i2c->msg_ptr++];
 318                         writeb(byte, i2c->regs + S3C2410_IICDS);
 319
 320                         /* delay after writing the byte to allow the
 321                          * data setup time on the bus, as writing the
 322                          * data to the register causes the first bit
 323                          * to appear on SDA, and SCL will change as
 324                          * soon as the interrupt is acknowledged */
 325
 326                         ndelay(i2c->tx_setup);
 327
 328                 } else if (!is_lastmsg(i2c)) {
 329                         /* we need to go to the next i2c message */
 330
 331                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 332
 333                         i2c->msg_ptr = 0;
 334                         i2c->msg_idx++;
 335                         i2c->msg++;
 336
 337                         /* check to see if we need to do another message */
 338                         if (i2c->msg->flags & I2C_M_NOSTART) {
 339
 340                                 if (i2c->msg->flags & I2C_M_RD) {
 341                                         /* cannot do this, the controller
 342                                          * forces us to send a new START
 343                                          * when we change direction */
 344
 345                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 346                                 }
 347
 348                                 goto retry_write;
 349                         } else {
 350                                 /* send the new start */
 351                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 352                                 i2c->state = STATE_START;
 353                         }
 354
 355                 } else {
 356                         /* send stop */
 357
 358                         s3c24xx_i2c_stop(i2c, 0);
 359                 }
 360                 break;
 361
 362         case STATE_READ:
 363                 /* we have a byte of data in the data register, do
 364                  * something with it, and then work out wether we are
 365                  * going to do any more read/write
 366                  */
 367
 368                 byte = readb(i2c->regs + S3C2410_IICDS);
 369                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 370
 371  prepare_read:
 372                 if (is_msglast(i2c)) {
 373                         /* last byte of buffer */
 374
 375                         if (is_lastmsg(i2c))
 376                                 s3c24xx_i2c_disable_ack(i2c);
 377
 378                 } else if (is_msgend(i2c)) {
 379                         /* ok, we've read the entire buffer, see if there
 380                          * is anything else we need to do */
 381
 382                         if (is_lastmsg(i2c)) {
 383                                 /* last message, send stop and complete */
 384                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 385
 386                                 s3c24xx_i2c_stop(i2c, 0);
 387                         } else {
 388                                 /* go to the next transfer */
 389                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 390
 391                                 i2c->msg_ptr = 0;
 392                                 i2c->msg_idx++;
 393                                 i2c->msg++;
 394                         }
 395                 }
 396
 397                 break;
 398         }
 399
 400         /* acknowlegde the IRQ and get back on with the work */
 401
 402  out_ack:
 403         tmp = readl(i2c->regs + S3C2410_IICCON);
 404         tmp &= ~S3C2410_IICCON_IRQPEND;
 405         writel(tmp, i2c->regs + S3C2410_IICCON);
 406  out:
 407         return ret;
 408 }
 409
 410 /* s3c24xx_i2c_irq
 411  *
 412  * top level IRQ servicing routine
 413 */
 414
 415 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 416 {
 417         struct s3c24xx_i2c *i2c = dev_id;
 418         unsigned long status;
 419         unsigned long tmp;
 420
 421         status = readl(i2c->regs + S3C2410_IICSTAT);
 422
 423         if (status & S3C2410_IICSTAT_ARBITR) {
 424                 /* deal with arbitration loss */
 425                 dev_err(i2c->dev, "deal with arbitration loss\n");
 426         }
 427
 428         if (i2c->state == STATE_IDLE) {
 429                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 430
 431                 tmp = readl(i2c->regs + S3C2410_IICCON);
 432                 tmp &= ~S3C2410_IICCON_IRQPEND;
 433                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 434                 goto out;
 435         }
 436
 437         /* pretty much this leaves us with the fact that we've
 438          * transmitted or received whatever byte we last sent */
 439
 440         i2s_s3c_irq_nextbyte(i2c, status);
 441
 442  out:
 443         return IRQ_HANDLED;
 444 }
 445
 446
 447 /* s3c24xx_i2c_set_master
 448  *
 449  * get the i2c bus for a master transaction
 450 */
 451
 452 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 453 {
 454         unsigned long iicstat;
 455         int timeout = 400;
 456
 457         while (timeout-- > 0) {
 458                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 459
 460                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 461                         return 0;
 462
 463                 msleep(1);
 464         }
 465
 466         return -ETIMEDOUT;
 467 }
 468
 469 /* s3c24xx_i2c_doxfer
 470  *
 471  * this starts an i2c transfer
 472 */
 473
 474 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 475                               struct i2c_msg *msgs, int num)
 476 {
 477         unsigned long timeout;
 478         int ret;
 479
 480         if (i2c->suspended)
 481                 return -EIO;
 482
 483         ret = s3c24xx_i2c_set_master(i2c);
 484         if (ret != 0) {
 485                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 486                 ret = -EAGAIN;
 487                 goto out;
 488         }
 489
 490         spin_lock_irq(&i2c->lock);
 491
 492         i2c->msg     = msgs;
 493         i2c->msg_num = num;
 494         i2c->msg_ptr = 0;
 495         i2c->msg_idx = 0;
 496         i2c->state   = STATE_START;
 497
 498         s3c24xx_i2c_enable_irq(i2c);
 499         s3c24xx_i2c_message_start(i2c, msgs);
 500         spin_unlock_irq(&i2c->lock);
 501
 502         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 503
 504         ret = i2c->msg_idx;
 505
 506         /* having these next two as dev_err() makes life very
 507          * noisy when doing an i2cdetect */
 508
 509         if (timeout == 0)
 510                 dev_dbg(i2c->dev, "timeout\n");
 511         else if (ret != num)
 512                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 513
 514         /* ensure the stop has been through the bus */
 515
 516         msleep(1);
 517
 518  out:
 519         return ret;
 520 }
 521
 522 /* s3c24xx_i2c_xfer
 523  *
 524  * first port of call from the i2c bus code when an message needs
 525  * transferring across the i2c bus.
 526 */
 527
 528 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 529                         struct i2c_msg *msgs, int num)
 530 {
 531         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 532         int retry;
 533         int ret;
 534
 535         for (retry = 0; retry < adap->retries; retry++) {
 536
 537                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 538
 539                 if (ret != -EAGAIN)
 540                         return ret;
 541
 542                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 543
 544                 udelay(100);
 545         }
 546
 547         return -EREMOTEIO;
 548 }
 549
 550 /* declare our i2c functionality */
 551 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 552 {
 553         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 554 }
 555
 556 /* i2c bus registration info */
 557
 558 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 559         .master_xfer            = s3c24xx_i2c_xfer,
 560         .functionality          = s3c24xx_i2c_func,
 561 };
 562
 563 /* s3c24xx_i2c_calcdivisor
 564  *
 565  * return the divisor settings for a given frequency
 566 */
 567
 568 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 569                                    unsigned int *div1, unsigned int *divs)
 570 {
 571         unsigned int calc_divs = clkin / wanted;
 572         unsigned int calc_div1;
 573
 574         if (calc_divs > (16*16))
 575                 calc_div1 = 512;
 576         else
 577                 calc_div1 = 16;
 578
 579         calc_divs += calc_div1-1;
 580         calc_divs /= calc_div1;
 581
 582         if (calc_divs == 0)
 583                 calc_divs = 1;
 584         if (calc_divs > 17)
 585                 calc_divs = 17;
 586
 587         *divs = calc_divs;
 588         *div1 = calc_div1;
 589
 590         return clkin / (calc_divs * calc_div1);
 591 }
 592
 593 /* freq_acceptable
 594  *
 595  * test wether a frequency is within the acceptable range of error
 596 */
 597
 598 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 599 {
 600         int diff = freq - wanted;
 601
 602         return diff >= -2 && diff <= 2;
 603 }
 604
 605 /* s3c24xx_i2c_clockrate
 606  *
 607  * work out a divisor for the user requested frequency setting,
 608  * either by the requested frequency, or scanning the acceptable
 609  * range of frequencies until something is found
 610 */
 611
 612 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 613 {
 614         struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
 615         unsigned long clkin = clk_get_rate(i2c->clk);
 616         unsigned int divs, div1;
 617         u32 iiccon;
 618         int freq;
 619         int start, end;
 620
 621         i2c->clkrate = clkin;
 622         clkin /= 1000;          /* clkin now in KHz */
 623
 624         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
 625                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
 626
 627         if (pdata->bus_freq != 0) {
 628                 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
 629                                                &div1, &divs);
 630                 if (freq_acceptable(freq, pdata->bus_freq/1000))
 631                         goto found;
 632         }
 633
 634         /* ok, we may have to search for something suitable... */
 635
 636         start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
 637         end = pdata->min_freq;
 638
 639         start /= 1000;
 640         end /= 1000;
 641
 642         /* search loop... */
 643
 644         for (; start > end; start--) {
 645                 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
 646                 if (freq_acceptable(freq, start))
 647                         goto found;
 648         }
 649
 650         /* cannot find frequency spec */
 651
 652         return -EINVAL;
 653
 654  found:
 655         *got = freq;
 656
 657         iiccon = readl(i2c->regs + S3C2410_IICCON);
 658         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 659         iiccon |= (divs-1);
 660
 661         if (div1 == 512)
 662                 iiccon |= S3C2410_IICCON_TXDIV_512;
 663
 664         writel(iiccon, i2c->regs + S3C2410_IICCON);
 665
 666         return 0;
 667 }
 668
 669 #ifdef CONFIG_CPU_FREQ
 670
 671 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 672
 673 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 674                                           unsigned long val, void *data)
 675 {
 676         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 677         unsigned long flags;
 678         unsigned int got;
 679         int delta_f;
 680         int ret;
 681
 682         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 683
 684         /* if we're post-change and the input clock has slowed down
 685          * or at pre-change and the clock is about to speed up, then
 686          * adjust our clock rate. <0 is slow, >0 speedup.
 687          */
 688
 689         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 690             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 691                 spin_lock_irqsave(&i2c->lock, flags);
 692                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 693                 spin_unlock_irqrestore(&i2c->lock, flags);
 694
 695                 if (ret < 0)
 696                         dev_err(i2c->dev, "cannot find frequency\n");
 697                 else
 698                         dev_info(i2c->dev, "setting freq %d\n", got);
 699         }
 700
 701         return 0;
 702 }
 703
 704 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 705 {
 706         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 707
 708         return cpufreq_register_notifier(&i2c->freq_transition,
 709                                          CPUFREQ_TRANSITION_NOTIFIER);
 710 }
 711
 712 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 713 {
 714         cpufreq_unregister_notifier(&i2c->freq_transition,
 715                                     CPUFREQ_TRANSITION_NOTIFIER);
 716 }
 717
 718 #else
 719 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 720 {
 721         return 0;
 722 }
 723
 724 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 725 {
 726 }
 727 #endif
 728
 729 /* s3c24xx_i2c_init
 730  *
 731  * initialise the controller, set the IO lines and frequency
 732 */
 733
 734 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 735 {
 736         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 737         struct s3c2410_platform_i2c *pdata;
 738         unsigned int freq;
 739
 740         /* get the plafrom data */
 741
 742         pdata = i2c->dev->platform_data;
 743
 744         /* inititalise the gpio */
 745
 746         if (pdata->cfg_gpio)
 747                 pdata->cfg_gpio(to_platform_device(i2c->dev));
 748
 749         /* write slave address */
 750
 751         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 752
 753         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 754
 755         writel(iicon, i2c->regs + S3C2410_IICCON);
 756
 757         /* we need to work out the divisors for the clock... */
 758
 759         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 760                 writel(0, i2c->regs + S3C2410_IICCON);
 761                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 762                 return -EINVAL;
 763         }
 764
 765         /* todo - check that the i2c lines aren't being dragged anywhere */
 766
 767         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 768         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 769
 770         /* check for s3c2440 i2c controller  */
 771
 772         if (s3c24xx_i2c_is2440(i2c)) {
 773                 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
 774
 775                 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
 776         }
 777
 778         return 0;
 779 }
 780
 781 /* s3c24xx_i2c_probe
 782  *
 783  * called by the bus driver when a suitable device is found
 784 */
 785
 786 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 787 {
 788         struct s3c24xx_i2c *i2c;
 789         struct s3c2410_platform_i2c *pdata;
 790         struct resource *res;
 791         int ret;
 792
 793         pdata = pdev->dev.platform_data;
 794         if (!pdata) {
 795                 dev_err(&pdev->dev, "no platform data\n");
 796                 return -EINVAL;
 797         }
 798
 799         i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
 800         if (!i2c) {
 801                 dev_err(&pdev->dev, "no memory for state\n");
 802                 return -ENOMEM;
 803         }
 804
 805         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
 806         i2c->adap.owner   = THIS_MODULE;
 807         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
 808         i2c->adap.retries = 2;
 809         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 810         i2c->tx_setup     = 50;
 811
 812         spin_lock_init(&i2c->lock);
 813         init_waitqueue_head(&i2c->wait);
 814
 815         /* find the clock and enable it */
 816
 817         i2c->dev = &pdev->dev;
 818         i2c->clk = clk_get(&pdev->dev, "i2c");
 819         if (IS_ERR(i2c->clk)) {
 820                 dev_err(&pdev->dev, "cannot get clock\n");
 821                 ret = -ENOENT;
 822                 goto err_noclk;
 823         }
 824
 825         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
 826
 827         clk_enable(i2c->clk);
 828
 829         /* map the registers */
 830
 831         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 832         if (res == NULL) {
 833                 dev_err(&pdev->dev, "cannot find IO resource\n");
 834                 ret = -ENOENT;
 835                 goto err_clk;
 836         }
 837
 838         i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
 839                                          pdev->name);
 840
 841         if (i2c->ioarea == NULL) {
 842                 dev_err(&pdev->dev, "cannot request IO\n");
 843                 ret = -ENXIO;
 844                 goto err_clk;
 845         }
 846
 847         i2c->regs = ioremap(res->start, (res->end-res->start)+1);
 848
 849         if (i2c->regs == NULL) {
 850                 dev_err(&pdev->dev, "cannot map IO\n");
 851                 ret = -ENXIO;
 852                 goto err_ioarea;
 853         }
 854
 855         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
 856                 i2c->regs, i2c->ioarea, res);
 857
 858         /* setup info block for the i2c core */
 859
 860         i2c->adap.algo_data = i2c;
 861         i2c->adap.dev.parent = &pdev->dev;
 862
 863         /* initialise the i2c controller */
 864
 865         ret = s3c24xx_i2c_init(i2c);
 866         if (ret != 0)
 867                 goto err_iomap;
 868
 869         /* find the IRQ for this unit (note, this relies on the init call to
 870          * ensure no current IRQs pending
 871          */
 872
 873         i2c->irq = ret = platform_get_irq(pdev, 0);
 874         if (ret <= 0) {
 875                 dev_err(&pdev->dev, "cannot find IRQ\n");
 876                 goto err_iomap;
 877         }
 878
 879         ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
 880                           dev_name(&pdev->dev), i2c);
 881
 882         if (ret != 0) {
 883                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
 884                 goto err_iomap;
 885         }
 886
 887         ret = s3c24xx_i2c_register_cpufreq(i2c);
 888         if (ret < 0) {
 889                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
 890                 goto err_irq;
 891         }
 892
 893         /* Note, previous versions of the driver used i2c_add_adapter()
 894          * to add the bus at any number. We now pass the bus number via
 895          * the platform data, so if unset it will now default to always
 896          * being bus 0.
 897          */
 898
 899         i2c->adap.nr = pdata->bus_num;
 900
 901         ret = i2c_add_numbered_adapter(&i2c->adap);
 902         if (ret < 0) {
 903                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 904                 goto err_cpufreq;
 905         }
 906
 907         platform_set_drvdata(pdev, i2c);
 908
 909         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
 910         return 0;
 911
 912  err_cpufreq:
 913         s3c24xx_i2c_deregister_cpufreq(i2c);
 914
 915  err_irq:
 916         free_irq(i2c->irq, i2c);
 917
 918  err_iomap:
 919         iounmap(i2c->regs);
 920
 921  err_ioarea:
 922         release_resource(i2c->ioarea);
 923         kfree(i2c->ioarea);
 924
 925  err_clk:
 926         clk_disable(i2c->clk);
 927         clk_put(i2c->clk);
 928
 929  err_noclk:
 930         kfree(i2c);
 931         return ret;
 932 }
 933
 934 /* s3c24xx_i2c_remove
 935  *
 936  * called when device is removed from the bus
 937 */
 938
 939 static int s3c24xx_i2c_remove(struct platform_device *pdev)
 940 {
 941         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
 942
 943         s3c24xx_i2c_deregister_cpufreq(i2c);
 944
 945         i2c_del_adapter(&i2c->adap);
 946         free_irq(i2c->irq, i2c);
 947
 948         clk_disable(i2c->clk);
 949         clk_put(i2c->clk);
 950
 951         iounmap(i2c->regs);
 952
 953         release_resource(i2c->ioarea);
 954         kfree(i2c->ioarea);
 955         kfree(i2c);
 956
 957         return 0;
 958 }
 959
 960 #ifdef CONFIG_PM
 961 static int s3c24xx_i2c_suspend_late(struct platform_device *dev,
 962                                     pm_message_t msg)
 963 {
 964         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
 965         i2c->suspended = 1;
 966         return 0;
 967 }
 968
 969 static int s3c24xx_i2c_resume(struct platform_device *dev)
 970 {
 971         struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
 972
 973         i2c->suspended = 0;
 974         s3c24xx_i2c_init(i2c);
 975
 976         return 0;
 977 }
 978
 979 #else
 980 #define s3c24xx_i2c_suspend_late NULL
 981 #define s3c24xx_i2c_resume NULL
 982 #endif
 983
 984 /* device driver for platform bus bits */
 985
 986 static struct platform_driver s3c2410_i2c_driver = {
 987         .probe          = s3c24xx_i2c_probe,
 988         .remove         = s3c24xx_i2c_remove,
 989         .suspend_late   = s3c24xx_i2c_suspend_late,
 990         .resume         = s3c24xx_i2c_resume,
 991         .driver         = {
 992                 .owner  = THIS_MODULE,
 993                 .name   = "s3c2410-i2c",
 994         },
 995 };
 996
 997 static struct platform_driver s3c2440_i2c_driver = {
 998         .probe          = s3c24xx_i2c_probe,
 999         .remove         = s3c24xx_i2c_remove,
1000         .suspend_late   = s3c24xx_i2c_suspend_late,
1001         .resume         = s3c24xx_i2c_resume,
1002         .driver         = {
1003                 .owner  = THIS_MODULE,
1004                 .name   = "s3c2440-i2c",
1005         },
1006 };
1007
1008 static int __init i2c_adap_s3c_init(void)
1009 {
1010         int ret;
1011
1012         ret = platform_driver_register(&s3c2410_i2c_driver);
1013         if (ret == 0) {
1014                 ret = platform_driver_register(&s3c2440_i2c_driver);
1015                 if (ret)
1016                         platform_driver_unregister(&s3c2410_i2c_driver);
1017         }
1018
1019         return ret;
1020 }
1021
1022 static void __exit i2c_adap_s3c_exit(void)
1023 {
1024         platform_driver_unregister(&s3c2410_i2c_driver);
1025         platform_driver_unregister(&s3c2440_i2c_driver);
1026 }
1027
1028 module_init(i2c_adap_s3c_init);
1029 module_exit(i2c_adap_s3c_exit);
1030
1031 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1032 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1033 MODULE_LICENSE("GPL");
1034 MODULE_ALIAS("platform:s3c2410-i2c");
1035 MODULE_ALIAS("platform:s3c2440-i2c");