git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <asm/io.h>
  23 #include <linux/fsl_devices.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27
  28 #define MPC_I2C_ADDR  0x00
  29 #define MPC_I2C_FDR     0x04
  30 #define MPC_I2C_CR      0x08
  31 #define MPC_I2C_SR      0x0c
  32 #define MPC_I2C_DR      0x10
  33 #define MPC_I2C_DFSRR 0x14
  34 #define MPC_I2C_REGION 0x20
  35
  36 #define CCR_MEN  0x80
  37 #define CCR_MIEN 0x40
  38 #define CCR_MSTA 0x20
  39 #define CCR_MTX  0x10
  40 #define CCR_TXAK 0x08
  41 #define CCR_RSTA 0x04
  42
  43 #define CSR_MCF  0x80
  44 #define CSR_MAAS 0x40
  45 #define CSR_MBB  0x20
  46 #define CSR_MAL  0x10
  47 #define CSR_SRW  0x04
  48 #define CSR_MIF  0x02
  49 #define CSR_RXAK 0x01
  50
  51 struct mpc_i2c {
  52         void __iomem *base;
  53         u32 interrupt;
  54         wait_queue_head_t queue;
  55         struct i2c_adapter adap;
  56         int irq;
  57         u32 flags;
  58 };
  59
  60 static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
  61 {
  62         writeb(x, i2c->base + MPC_I2C_CR);
  63 }
  64
  65 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  66 {
  67         struct mpc_i2c *i2c = dev_id;
  68         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  69                 /* Read again to allow register to stabilise */
  70                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  71                 writeb(0, i2c->base + MPC_I2C_SR);
  72                 wake_up_interruptible(&i2c->queue);
  73         }
  74         return IRQ_HANDLED;
  75 }
  76
  77 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  78  * the bus, because it wants to send ACK.
  79  * Following sequence of enabling/disabling and sending start/stop generates
  80  * the pulse, so it's all OK.
  81  */
  82 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
  83 {
  84         writeccr(i2c, 0);
  85         udelay(30);
  86         writeccr(i2c, CCR_MEN);
  87         udelay(30);
  88         writeccr(i2c, CCR_MSTA | CCR_MTX);
  89         udelay(30);
  90         writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
  91         udelay(30);
  92         writeccr(i2c, CCR_MEN);
  93         udelay(30);
  94 }
  95
  96 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
  97 {
  98         unsigned long orig_jiffies = jiffies;
  99         u32 x;
 100         int result = 0;
 101
 102         if (i2c->irq == 0)
 103         {
 104                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 105                         schedule();
 106                         if (time_after(jiffies, orig_jiffies + timeout)) {
 107                                 pr_debug("I2C: timeout\n");
 108                                 result = -EIO;
 109                                 break;
 110                         }
 111                 }
 112                 x = readb(i2c->base + MPC_I2C_SR);
 113                 writeb(0, i2c->base + MPC_I2C_SR);
 114         } else {
 115                 /* Interrupt mode */
 116                 result = wait_event_interruptible_timeout(i2c->queue,
 117                         (i2c->interrupt & CSR_MIF), timeout * HZ);
 118
 119                 if (unlikely(result < 0))
 120                         pr_debug("I2C: wait interrupted\n");
 121                 else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 122                         pr_debug("I2C: wait timeout\n");
 123                         result = -ETIMEDOUT;
 124                 }
 125
 126                 x = i2c->interrupt;
 127                 i2c->interrupt = 0;
 128         }
 129
 130         if (result < 0)
 131                 return result;
 132
 133         if (!(x & CSR_MCF)) {
 134                 pr_debug("I2C: unfinished\n");
 135                 return -EIO;
 136         }
 137
 138         if (x & CSR_MAL) {
 139                 pr_debug("I2C: MAL\n");
 140                 return -EIO;
 141         }
 142
 143         if (writing && (x & CSR_RXAK)) {
 144                 pr_debug("I2C: No RXAK\n");
 145                 /* generate stop */
 146                 writeccr(i2c, CCR_MEN);
 147                 return -EIO;
 148         }
 149         return 0;
 150 }
 151
 152 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
 153 {
 154         /* Set clock and filters */
 155         if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
 156                 writeb(0x31, i2c->base + MPC_I2C_FDR);
 157                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
 158         } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
 159                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
 160         else
 161                 writel(0x1031, i2c->base + MPC_I2C_FDR);
 162 }
 163
 164 static void mpc_i2c_start(struct mpc_i2c *i2c)
 165 {
 166         /* Clear arbitration */
 167         writeb(0, i2c->base + MPC_I2C_SR);
 168         /* Start with MEN */
 169         writeccr(i2c, CCR_MEN);
 170 }
 171
 172 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 173 {
 174         writeccr(i2c, CCR_MEN);
 175         writeccr(i2c, 0);
 176 }
 177
 178 static int mpc_write(struct mpc_i2c *i2c, int target,
 179                      const u8 * data, int length, int restart)
 180 {
 181         int i;
 182         unsigned timeout = i2c->adap.timeout;
 183         u32 flags = restart ? CCR_RSTA : 0;
 184
 185         /* Start with MEN */
 186         if (!restart)
 187                 writeccr(i2c, CCR_MEN);
 188         /* Start as master */
 189         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 190         /* Write target byte */
 191         writeb((target << 1), i2c->base + MPC_I2C_DR);
 192
 193         if (i2c_wait(i2c, timeout, 1) < 0)
 194                 return -1;
 195
 196         for (i = 0; i < length; i++) {
 197                 /* Write data byte */
 198                 writeb(data[i], i2c->base + MPC_I2C_DR);
 199
 200                 if (i2c_wait(i2c, timeout, 1) < 0)
 201                         return -1;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static int mpc_read(struct mpc_i2c *i2c, int target,
 208                     u8 * data, int length, int restart)
 209 {
 210         unsigned timeout = i2c->adap.timeout;
 211         int i;
 212         u32 flags = restart ? CCR_RSTA : 0;
 213
 214         /* Start with MEN */
 215         if (!restart)
 216                 writeccr(i2c, CCR_MEN);
 217         /* Switch to read - restart */
 218         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 219         /* Write target address byte - this time with the read flag set */
 220         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 221
 222         if (i2c_wait(i2c, timeout, 1) < 0)
 223                 return -1;
 224
 225         if (length) {
 226                 if (length == 1)
 227                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 228                 else
 229                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 230                 /* Dummy read */
 231                 readb(i2c->base + MPC_I2C_DR);
 232         }
 233
 234         for (i = 0; i < length; i++) {
 235                 if (i2c_wait(i2c, timeout, 0) < 0)
 236                         return -1;
 237
 238                 /* Generate txack on next to last byte */
 239                 if (i == length - 2)
 240                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 241                 /* Generate stop on last byte */
 242                 if (i == length - 1)
 243                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
 244                 data[i] = readb(i2c->base + MPC_I2C_DR);
 245         }
 246
 247         return length;
 248 }
 249
 250 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 251 {
 252         struct i2c_msg *pmsg;
 253         int i;
 254         int ret = 0;
 255         unsigned long orig_jiffies = jiffies;
 256         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 257
 258         mpc_i2c_start(i2c);
 259
 260         /* Allow bus up to 1s to become not busy */
 261         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 262                 if (signal_pending(current)) {
 263                         pr_debug("I2C: Interrupted\n");
 264                         return -EINTR;
 265                 }
 266                 if (time_after(jiffies, orig_jiffies + HZ)) {
 267                         pr_debug("I2C: timeout\n");
 268                         if (readb(i2c->base + MPC_I2C_SR) ==
 269                             (CSR_MCF | CSR_MBB | CSR_RXAK))
 270                                 mpc_i2c_fixup(i2c);
 271                         return -EIO;
 272                 }
 273                 schedule();
 274         }
 275
 276         for (i = 0; ret >= 0 && i < num; i++) {
 277                 pmsg = &msgs[i];
 278                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 279                          pmsg->flags & I2C_M_RD ? "read" : "write",
 280                          pmsg->len, pmsg->addr, i + 1, num);
 281                 if (pmsg->flags & I2C_M_RD)
 282                         ret =
 283                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 284                 else
 285                         ret =
 286                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 287         }
 288         mpc_i2c_stop(i2c);
 289         return (ret < 0) ? ret : num;
 290 }
 291
 292 static u32 mpc_functionality(struct i2c_adapter *adap)
 293 {
 294         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 295 }
 296
 297 static const struct i2c_algorithm mpc_algo = {
 298         .master_xfer = mpc_xfer,
 299         .functionality = mpc_functionality,
 300 };
 301
 302 static struct i2c_adapter mpc_ops = {
 303         .owner = THIS_MODULE,
 304         .name = "MPC adapter",
 305         .id = I2C_HW_MPC107,
 306         .algo = &mpc_algo,
 307         .class = I2C_CLASS_HWMON,
 308         .timeout = 1,
 309         .retries = 1
 310 };
 311
 312 static int fsl_i2c_probe(struct platform_device *pdev)
 313 {
 314         int result = 0;
 315         struct mpc_i2c *i2c;
 316         struct fsl_i2c_platform_data *pdata;
 317         struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 318
 319         pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
 320
 321         if (!(i2c = kzalloc(sizeof(*i2c), GFP_KERNEL))) {
 322                 return -ENOMEM;
 323         }
 324
 325         i2c->irq = platform_get_irq(pdev, 0);
 326         if (i2c->irq < 0) {
 327                 result = -ENXIO;
 328                 goto fail_get_irq;
 329         }
 330         i2c->flags = pdata->device_flags;
 331         init_waitqueue_head(&i2c->queue);
 332
 333         i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
 334
 335         if (!i2c->base) {
 336                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
 337                 result = -ENOMEM;
 338                 goto fail_map;
 339         }
 340
 341         if (i2c->irq != 0)
 342                 if ((result = request_irq(i2c->irq, mpc_i2c_isr,
 343                                           IRQF_SHARED, "i2c-mpc", i2c)) < 0) {
 344                         printk(KERN_ERR
 345                                "i2c-mpc - failed to attach interrupt\n");
 346                         goto fail_irq;
 347                 }
 348
 349         mpc_i2c_setclock(i2c);
 350         platform_set_drvdata(pdev, i2c);
 351
 352         i2c->adap = mpc_ops;
 353         i2c->adap.nr = pdev->id;
 354         i2c_set_adapdata(&i2c->adap, i2c);
 355         i2c->adap.dev.parent = &pdev->dev;
 356         if ((result = i2c_add_numbered_adapter(&i2c->adap)) < 0) {
 357                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
 358                 goto fail_add;
 359         }
 360
 361         return result;
 362
 363       fail_add:
 364         if (i2c->irq != 0)
 365                 free_irq(i2c->irq, NULL);
 366       fail_irq:
 367         iounmap(i2c->base);
 368       fail_map:
 369       fail_get_irq:
 370         kfree(i2c);
 371         return result;
 372 };
 373
 374 static int fsl_i2c_remove(struct platform_device *pdev)
 375 {
 376         struct mpc_i2c *i2c = platform_get_drvdata(pdev);
 377
 378         i2c_del_adapter(&i2c->adap);
 379         platform_set_drvdata(pdev, NULL);
 380
 381         if (i2c->irq != 0)
 382                 free_irq(i2c->irq, i2c);
 383
 384         iounmap(i2c->base);
 385         kfree(i2c);
 386         return 0;
 387 };
 388
 389 /* Structure for a device driver */
 390 static struct platform_driver fsl_i2c_driver = {
 391         .probe = fsl_i2c_probe,
 392         .remove = fsl_i2c_remove,
 393         .driver = {
 394                 .owner = THIS_MODULE,
 395                 .name = "fsl-i2c",
 396         },
 397 };
 398
 399 static int __init fsl_i2c_init(void)
 400 {
 401         return platform_driver_register(&fsl_i2c_driver);
 402 }
 403
 404 static void __exit fsl_i2c_exit(void)
 405 {
 406         platform_driver_unregister(&fsl_i2c_driver);
 407 }
 408
 409 module_init(fsl_i2c_init);
 410 module_exit(fsl_i2c_exit);
 411
 412 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 413 MODULE_DESCRIPTION
 414     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
 415 MODULE_LICENSE("GPL");