2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #define SECONDARY_PROCESSORS
28 #include <linux/config.h>
29 #include <linux/threads.h>
30 #include <asm/processor.h>
33 #include <asm/systemcfg.h>
34 #include <asm/ppc_asm.h>
35 #include <asm/offsets.h>
37 #include <asm/cputable.h>
38 #include <asm/setup.h>
39 #include <asm/hvcall.h>
40 #include <asm/iSeries/LparMap.h>
42 #ifdef CONFIG_PPC_ISERIES
43 #define DO_SOFT_DISABLE
47 * hcall interface to pSeries LPAR
49 #define H_SET_ASR 0x30
52 * We layout physical memory as follows:
53 * 0x0000 - 0x00ff : Secondary processor spin code
54 * 0x0100 - 0x2fff : pSeries Interrupt prologs
55 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
56 * 0x6000 - 0x6fff : Initial (CPU0) segment table
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - : Early init and support code
66 * SPRG0 reserved for hypervisor
67 * SPRG1 temp - used to save gpr
68 * SPRG2 temp - used to save gpr
69 * SPRG3 virt addr of paca
73 * Entering into this code we make the following assumptions:
75 * 1. The MMU is off & open firmware is running in real mode.
76 * 2. The kernel is entered at __start
79 * 1. The MMU is on (as it always is for iSeries)
80 * 2. The kernel is entered at system_reset_iSeries
86 #ifdef CONFIG_PPC_MULTIPLATFORM
88 /* NOP this out unconditionally */
90 b .__start_initialization_multiplatform
92 #endif /* CONFIG_PPC_MULTIPLATFORM */
94 /* Catch branch to 0 in real mode */
96 #ifdef CONFIG_PPC_ISERIES
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
102 .llong hvReleaseData-KERNELBASE
105 * At offset 0x28 and 0x30 are offsets to the msChunks
106 * array (used by the iSeries LPAR debugger to do translation
107 * between physical addresses and absolute addresses) and
108 * to the pidhash table (also used by the debugger)
110 .llong msChunks-KERNELBASE
111 .llong 0 /* pidhash-KERNELBASE SFRXXX */
113 /* Offset 0x38 - Pointer to start of embedded System.map */
114 .globl embedded_sysmap_start
115 embedded_sysmap_start:
117 /* Offset 0x40 - Pointer to end of embedded System.map */
118 .globl embedded_sysmap_end
122 #else /* CONFIG_PPC_ISERIES */
124 /* Secondary processors spin on this value until it goes to 1. */
125 .globl __secondary_hold_spinloop
126 __secondary_hold_spinloop:
129 /* Secondary processors write this value with their cpu # */
130 /* after they enter the spin loop immediately below. */
131 .globl __secondary_hold_acknowledge
132 __secondary_hold_acknowledge:
137 * The following code is used on pSeries to hold secondary processors
138 * in a spin loop after they have been freed from OpenFirmware, but
139 * before the bulk of the kernel has been relocated. This code
140 * is relocated to physical address 0x60 before prom_init is run.
141 * All of it must fit below the first exception vector at 0x100.
143 _GLOBAL(__secondary_hold)
146 mtmsrd r24 /* RI on */
148 /* Grab our linux cpu number */
151 /* Tell the master cpu we're here */
152 /* Relocation is off & we are located at an address less */
153 /* than 0x100, so only need to grab low order offset. */
154 std r24,__secondary_hold_acknowledge@l(0)
157 /* All secondary cpu's wait here until told to start. */
158 100: ld r4,__secondary_hold_spinloop@l(0)
167 b .pSeries_secondary_smp_init
174 /* This value is used to mark exception frames on the stack. */
177 .tc ID_72656773_68657265[TC],0x7265677368657265
181 * The following macros define the code that appears as
182 * the prologue to each of the exception handlers. They
183 * are split into two parts to allow a single kernel binary
184 * to be used for pSeries and iSeries.
185 * LOL. One day... - paulus
189 * We make as much of the exception code common between native
190 * exception handlers (including pSeries LPAR) and iSeries LPAR
191 * implementations as possible.
195 * This is the start of the interrupt handlers for pSeries
196 * This code runs with relocation off.
204 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
206 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
210 #define EXCEPTION_PROLOG_PSERIES(area, label) \
211 mfspr r13,SPRG3; /* get paca address into r13 */ \
212 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
213 std r10,area+EX_R10(r13); \
214 std r11,area+EX_R11(r13); \
215 std r12,area+EX_R12(r13); \
217 std r9,area+EX_R13(r13); \
219 clrrdi r12,r13,32; /* get high part of &label */ \
221 mfspr r11,SRR0; /* save SRR0 */ \
222 ori r12,r12,(label)@l; /* virt addr of handler */ \
223 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
225 mfspr r12,SRR1; /* and SRR1 */ \
228 b . /* prevent speculative execution */
231 * This is the start of the interrupt handlers for iSeries
232 * This code runs with relocation on.
234 #define EXCEPTION_PROLOG_ISERIES_1(area) \
235 mfspr r13,SPRG3; /* get paca address into r13 */ \
236 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
237 std r10,area+EX_R10(r13); \
238 std r11,area+EX_R11(r13); \
239 std r12,area+EX_R12(r13); \
241 std r9,area+EX_R13(r13); \
244 #define EXCEPTION_PROLOG_ISERIES_2 \
246 ld r11,PACALPPACA+LPPACASRR0(r13); \
247 ld r12,PACALPPACA+LPPACASRR1(r13); \
248 ori r10,r10,MSR_RI; \
252 * The common exception prolog is used for all except a few exceptions
253 * such as a segment miss on a kernel address. We have to be prepared
254 * to take another exception from the point where we first touch the
255 * kernel stack onwards.
257 * On entry r13 points to the paca, r9-r13 are saved in the paca,
258 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
259 * SRR1, and relocation is on.
261 #define EXCEPTION_PROLOG_COMMON(n, area) \
262 andi. r10,r12,MSR_PR; /* See if coming from user */ \
263 mr r10,r1; /* Save r1 */ \
264 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
266 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
267 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
268 bge- cr1,bad_stack; /* abort if it is */ \
269 std r9,_CCR(r1); /* save CR in stackframe */ \
270 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
271 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
272 std r10,0(r1); /* make stack chain pointer */ \
273 std r0,GPR0(r1); /* save r0 in stackframe */ \
274 std r10,GPR1(r1); /* save r1 in stackframe */ \
275 std r2,GPR2(r1); /* save r2 in stackframe */ \
276 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
277 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
278 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
279 ld r10,area+EX_R10(r13); \
282 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
283 ld r10,area+EX_R12(r13); \
284 ld r11,area+EX_R13(r13); \
288 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
289 mflr r9; /* save LR in stackframe */ \
291 mfctr r10; /* save CTR in stackframe */ \
293 mfspr r11,XER; /* save XER in stackframe */ \
296 std r9,_TRAP(r1); /* set trap number */ \
298 ld r11,exception_marker@toc(r2); \
299 std r10,RESULT(r1); /* clear regs->result */ \
300 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
305 #define STD_EXCEPTION_PSERIES(n, label) \
307 .globl label##_pSeries; \
310 mtspr SPRG1,r13; /* save r13 */ \
312 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
314 #define STD_EXCEPTION_ISERIES(n, label, area) \
315 .globl label##_iSeries; \
318 mtspr SPRG1,r13; /* save r13 */ \
320 EXCEPTION_PROLOG_ISERIES_1(area); \
321 EXCEPTION_PROLOG_ISERIES_2; \
324 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
325 .globl label##_iSeries; \
328 mtspr SPRG1,r13; /* save r13 */ \
330 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
331 lbz r10,PACAPROCENABLED(r13); \
333 beq- label##_iSeries_masked; \
334 EXCEPTION_PROLOG_ISERIES_2; \
337 #ifdef DO_SOFT_DISABLE
338 #define DISABLE_INTS \
339 lbz r10,PACAPROCENABLED(r13); \
343 stb r11,PACAPROCENABLED(r13); \
344 ori r10,r10,MSR_EE; \
347 #define ENABLE_INTS \
348 lbz r10,PACAPROCENABLED(r13); \
351 ori r11,r11,MSR_EE; \
354 #else /* hard enable/disable interrupts */
357 #define ENABLE_INTS \
360 rlwimi r11,r12,0,MSR_EE; \
365 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
367 .globl label##_common; \
369 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
372 addi r3,r1,STACK_FRAME_OVERHEAD; \
376 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
378 .globl label##_common; \
380 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
382 addi r3,r1,STACK_FRAME_OVERHEAD; \
384 b .ret_from_except_lite
387 * Start of pSeries system interrupt routines
390 .globl __start_interrupts
393 STD_EXCEPTION_PSERIES(0x100, system_reset)
396 _machine_check_pSeries:
398 mtspr SPRG1,r13 /* save r13 */
400 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
403 .globl data_access_pSeries
412 rlwimi r13,r12,16,0x20
415 beq .do_stab_bolted_pSeries
418 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
419 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
422 .globl data_access_slb_pSeries
423 data_access_slb_pSeries:
427 mfspr r13,SPRG3 /* get paca address into r13 */
428 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
429 std r10,PACA_EXSLB+EX_R10(r13)
430 std r11,PACA_EXSLB+EX_R11(r13)
431 std r12,PACA_EXSLB+EX_R12(r13)
432 std r3,PACA_EXSLB+EX_R3(r13)
434 std r9,PACA_EXSLB+EX_R13(r13)
436 mfspr r12,SRR1 /* and SRR1 */
438 b .do_slb_miss /* Rel. branch works in real mode */
440 STD_EXCEPTION_PSERIES(0x400, instruction_access)
443 .globl instruction_access_slb_pSeries
444 instruction_access_slb_pSeries:
448 mfspr r13,SPRG3 /* get paca address into r13 */
449 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
450 std r10,PACA_EXSLB+EX_R10(r13)
451 std r11,PACA_EXSLB+EX_R11(r13)
452 std r12,PACA_EXSLB+EX_R12(r13)
453 std r3,PACA_EXSLB+EX_R3(r13)
455 std r9,PACA_EXSLB+EX_R13(r13)
457 mfspr r12,SRR1 /* and SRR1 */
458 mfspr r3,SRR0 /* SRR0 is faulting address */
459 b .do_slb_miss /* Rel. branch works in real mode */
461 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
462 STD_EXCEPTION_PSERIES(0x600, alignment)
463 STD_EXCEPTION_PSERIES(0x700, program_check)
464 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
465 STD_EXCEPTION_PSERIES(0x900, decrementer)
466 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
467 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
470 .globl system_call_pSeries
479 oris r12,r12,system_call_common@h
480 ori r12,r12,system_call_common@l
482 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
486 b . /* prevent speculative execution */
488 STD_EXCEPTION_PSERIES(0xd00, single_step)
489 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
491 /* We need to deal with the Altivec unavailable exception
492 * here which is at 0xf20, thus in the middle of the
493 * prolog code of the PerformanceMonitor one. A little
494 * trickery is thus necessary
497 b performance_monitor_pSeries
499 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
501 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
502 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
506 /*** pSeries interrupt support ***/
508 /* moved from 0xf00 */
509 STD_EXCEPTION_PSERIES(., performance_monitor)
512 _GLOBAL(do_stab_bolted_pSeries)
515 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
518 * Vectors for the FWNMI option. Share common code.
520 .globl system_reset_fwnmi
523 mtspr SPRG1,r13 /* save r13 */
525 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
527 .globl machine_check_fwnmi
530 mtspr SPRG1,r13 /* save r13 */
532 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
534 #ifdef CONFIG_PPC_ISERIES
535 /*** ISeries-LPAR interrupt handlers ***/
537 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
539 .globl data_access_iSeries
547 rlwimi r13,r12,16,0x20
550 beq .do_stab_bolted_iSeries
553 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
554 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
555 EXCEPTION_PROLOG_ISERIES_2
558 .do_stab_bolted_iSeries:
561 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
562 EXCEPTION_PROLOG_ISERIES_2
565 .globl data_access_slb_iSeries
566 data_access_slb_iSeries:
567 mtspr SPRG1,r13 /* save r13 */
568 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
569 std r3,PACA_EXSLB+EX_R3(r13)
570 ld r12,PACALPPACA+LPPACASRR1(r13)
574 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
576 .globl instruction_access_slb_iSeries
577 instruction_access_slb_iSeries:
578 mtspr SPRG1,r13 /* save r13 */
579 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
580 std r3,PACA_EXSLB+EX_R3(r13)
581 ld r12,PACALPPACA+LPPACASRR1(r13)
582 ld r3,PACALPPACA+LPPACASRR0(r13)
585 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
586 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
587 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
588 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
589 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
590 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
591 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
593 .globl system_call_iSeries
597 EXCEPTION_PROLOG_ISERIES_2
600 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
601 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
602 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
604 .globl system_reset_iSeries
605 system_reset_iSeries:
606 mfspr r13,SPRG3 /* Get paca address */
609 mtmsrd r24 /* RI on */
610 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
611 cmpwi 0,r24,0 /* Are we processor 0? */
612 beq .__start_initialization_iSeries /* Start up the first processor */
614 li r5,CTRL_RUNLATCH /* Turn off the run light */
621 lbz r23,PACAPROCSTART(r13) /* Test if this processor
624 LOADADDR(r3,current_set)
625 sldi r28,r24,3 /* get current_set[cpu#] */
627 addi r1,r3,THREAD_SIZE
628 subi r1,r1,STACK_FRAME_OVERHEAD
631 beq iSeries_secondary_smp_loop /* Loop until told to go */
632 #ifdef SECONDARY_PROCESSORS
633 bne .__secondary_start /* Loop until told to go */
635 iSeries_secondary_smp_loop:
636 /* Let the Hypervisor know we are alive */
637 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
639 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
640 #else /* CONFIG_SMP */
641 /* Yield the processor. This is required for non-SMP kernels
642 which are running on multi-threaded machines. */
644 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
645 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
646 li r4,0 /* "yield timed" */
647 li r5,-1 /* "yield forever" */
648 #endif /* CONFIG_SMP */
649 li r0,-1 /* r0=-1 indicates a Hypervisor call */
650 sc /* Invoke the hypervisor via a system call */
651 mfspr r13,SPRG3 /* Put r13 back ???? */
652 b 1b /* If SMP not configured, secondaries
655 .globl decrementer_iSeries_masked
656 decrementer_iSeries_masked:
658 stb r11,PACALPPACA+LPPACADECRINT(r13)
659 lwz r12,PACADEFAULTDECR(r13)
663 .globl hardware_interrupt_iSeries_masked
664 hardware_interrupt_iSeries_masked:
665 mtcrf 0x80,r9 /* Restore regs */
666 ld r11,PACALPPACA+LPPACASRR0(r13)
667 ld r12,PACALPPACA+LPPACASRR1(r13)
670 ld r9,PACA_EXGEN+EX_R9(r13)
671 ld r10,PACA_EXGEN+EX_R10(r13)
672 ld r11,PACA_EXGEN+EX_R11(r13)
673 ld r12,PACA_EXGEN+EX_R12(r13)
674 ld r13,PACA_EXGEN+EX_R13(r13)
676 b . /* prevent speculative execution */
677 #endif /* CONFIG_PPC_ISERIES */
679 /*** Common interrupt handlers ***/
681 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
684 * Machine check is different because we use a different
685 * save area: PACA_EXMC instead of PACA_EXGEN.
688 .globl machine_check_common
689 machine_check_common:
690 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
693 addi r3,r1,STACK_FRAME_OVERHEAD
694 bl .machine_check_exception
697 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
698 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
699 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
700 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
701 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
702 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
703 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
704 #ifdef CONFIG_ALTIVEC
705 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
707 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
711 * Here we have detected that the kernel stack pointer is bad.
712 * R9 contains the saved CR, r13 points to the paca,
713 * r10 contains the (bad) kernel stack pointer,
714 * r11 and r12 contain the saved SRR0 and SRR1.
715 * We switch to using the paca guard page as an emergency stack,
716 * save the registers there, and call kernel_bad_stack(), which panics.
719 ld r1,PACAEMERGSP(r13)
720 subi r1,r1,64+INT_FRAME_SIZE
741 addi r11,r1,INT_FRAME_SIZE
746 1: addi r3,r1,STACK_FRAME_OVERHEAD
751 * Return from an exception with minimal checks.
752 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
753 * If interrupts have been enabled, or anything has been
754 * done that might have changed the scheduling status of
755 * any task or sent any task a signal, you should use
756 * ret_from_except or ret_from_except_lite instead of this.
758 fast_exception_return:
761 andi. r3,r12,MSR_RI /* check if RI is set */
775 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
783 b . /* prevent speculative execution */
787 1: addi r3,r1,STACK_FRAME_OVERHEAD
788 bl .unrecoverable_exception
792 * Here r13 points to the paca, r9 contains the saved CR,
793 * SRR0 and SRR1 are saved in r11 and r12,
794 * r9 - r13 are saved in paca->exgen.
797 .globl data_access_common
799 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
801 std r10,PACA_EXGEN+EX_DAR(r13)
803 stw r10,PACA_EXGEN+EX_DSISR(r13)
804 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
805 ld r3,PACA_EXGEN+EX_DAR(r13)
806 lwz r4,PACA_EXGEN+EX_DSISR(r13)
808 b .do_hash_page /* Try to handle as hpte fault */
811 .globl instruction_access_common
812 instruction_access_common:
813 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
817 b .do_hash_page /* Try to handle as hpte fault */
820 .globl hardware_interrupt_common
821 .globl hardware_interrupt_entry
822 hardware_interrupt_common:
823 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
824 hardware_interrupt_entry:
826 addi r3,r1,STACK_FRAME_OVERHEAD
828 b .ret_from_except_lite
831 .globl alignment_common
834 std r10,PACA_EXGEN+EX_DAR(r13)
836 stw r10,PACA_EXGEN+EX_DSISR(r13)
837 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
838 ld r3,PACA_EXGEN+EX_DAR(r13)
839 lwz r4,PACA_EXGEN+EX_DSISR(r13)
843 addi r3,r1,STACK_FRAME_OVERHEAD
845 bl .alignment_exception
849 .globl program_check_common
850 program_check_common:
851 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
853 addi r3,r1,STACK_FRAME_OVERHEAD
855 bl .program_check_exception
859 .globl fp_unavailable_common
860 fp_unavailable_common:
861 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
862 bne .load_up_fpu /* if from user, just load it up */
864 addi r3,r1,STACK_FRAME_OVERHEAD
866 bl .kernel_fp_unavailable_exception
870 * load_up_fpu(unused, unused, tsk)
871 * Disable FP for the task which had the FPU previously,
872 * and save its floating-point registers in its thread_struct.
873 * Enables the FPU for use in the kernel on return.
874 * On SMP we know the fpu is free, since we give it up every
875 * switch (ie, no lazy save of the FP registers).
876 * On entry: r13 == 'current' && last_task_used_math != 'current'
879 mfmsr r5 /* grab the current MSR */
881 mtmsrd r5 /* enable use of fpu now */
884 * For SMP, we don't do lazy FPU switching because it just gets too
885 * horrendously complex, especially when a task switches from one CPU
886 * to another. Instead we call giveup_fpu in switch_to.
890 ld r3,last_task_used_math@got(r2)
894 /* Save FP state to last_task_used_math's THREAD struct */
898 stfd fr0,THREAD_FPSCR(r4)
899 /* Disable FP for last_task_used_math */
901 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
902 li r6,MSR_FP|MSR_FE0|MSR_FE1
904 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
906 #endif /* CONFIG_SMP */
907 /* enable use of FP after return */
908 ld r4,PACACURRENT(r13)
909 addi r5,r4,THREAD /* Get THREAD */
910 ld r4,THREAD_FPEXC_MODE(r5)
914 lfd fr0,THREAD_FPSCR(r5)
918 /* Update last_task_used_math to 'current' */
919 subi r4,r5,THREAD /* Back to 'current' */
921 #endif /* CONFIG_SMP */
922 /* restore registers and return */
923 b fast_exception_return
926 .globl altivec_unavailable_common
927 altivec_unavailable_common:
928 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
929 #ifdef CONFIG_ALTIVEC
931 bne .load_up_altivec /* if from user, just load it up */
932 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
935 addi r3,r1,STACK_FRAME_OVERHEAD
937 bl .altivec_unavailable_exception
940 #ifdef CONFIG_ALTIVEC
942 * load_up_altivec(unused, unused, tsk)
943 * Disable VMX for the task which had it previously,
944 * and save its vector registers in its thread_struct.
945 * Enables the VMX for use in the kernel on return.
946 * On SMP we know the VMX is free, since we give it up every
947 * switch (ie, no lazy save of the vector registers).
948 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
950 _STATIC(load_up_altivec)
951 mfmsr r5 /* grab the current MSR */
953 mtmsrd r5 /* enable use of VMX now */
957 * For SMP, we don't do lazy VMX switching because it just gets too
958 * horrendously complex, especially when a task switches from one CPU
959 * to another. Instead we call giveup_altvec in switch_to.
960 * VRSAVE isn't dealt with here, that is done in the normal context
961 * switch code. Note that we could rely on vrsave value to eventually
962 * avoid saving all of the VREGs here...
965 ld r3,last_task_used_altivec@got(r2)
969 /* Save VMX state to last_task_used_altivec's THREAD struct */
975 /* Disable VMX for last_task_used_altivec */
977 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
980 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
982 #endif /* CONFIG_SMP */
983 /* Hack: if we get an altivec unavailable trap with VRSAVE
984 * set to all zeros, we assume this is a broken application
985 * that fails to set it properly, and thus we switch it to
994 /* enable use of VMX after return */
995 ld r4,PACACURRENT(r13)
996 addi r5,r4,THREAD /* Get THREAD */
997 oris r12,r12,MSR_VEC@h
1001 stw r4,THREAD_USED_VR(r5)
1006 /* Update last_task_used_math to 'current' */
1007 subi r4,r5,THREAD /* Back to 'current' */
1009 #endif /* CONFIG_SMP */
1010 /* restore registers and return */
1011 b fast_exception_return
1012 #endif /* CONFIG_ALTIVEC */
1018 _GLOBAL(do_hash_page)
1022 andis. r0,r4,0xa450 /* weird error? */
1023 bne- .handle_page_fault /* if not, try to insert a HPTE */
1025 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1026 bne- .do_ste_alloc /* If so handle it */
1027 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1030 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1031 * accessing a userspace segment (even from the kernel). We assume
1032 * kernel addresses always have the high bit set.
1034 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1035 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1036 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1037 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1038 ori r4,r4,1 /* add _PAGE_PRESENT */
1039 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1042 * On iSeries, we soft-disable interrupts here, then
1043 * hard-enable interrupts so that the hash_page code can spin on
1044 * the hash_table_lock without problems on a shared processor.
1049 * r3 contains the faulting address
1050 * r4 contains the required access permissions
1051 * r5 contains the trap number
1053 * at return r3 = 0 for success
1055 bl .hash_page /* build HPTE if possible */
1056 cmpdi r3,0 /* see if hash_page succeeded */
1058 #ifdef DO_SOFT_DISABLE
1060 * If we had interrupts soft-enabled at the point where the
1061 * DSI/ISI occurred, and an interrupt came in during hash_page,
1063 * We jump to ret_from_except_lite rather than fast_exception_return
1064 * because ret_from_except_lite will check for and handle pending
1065 * interrupts if necessary.
1067 beq .ret_from_except_lite
1068 /* For a hash failure, we don't bother re-enabling interrupts */
1072 * hash_page couldn't handle it, set soft interrupt enable back
1073 * to what it was before the trap. Note that .local_irq_restore
1074 * handles any interrupts pending at this point.
1077 bl .local_irq_restore
1080 beq fast_exception_return /* Return from exception on success */
1081 ble- 12f /* Failure return from hash_page */
1086 /* Here we have a page fault that hash_page can't handle. */
1087 _GLOBAL(handle_page_fault)
1091 addi r3,r1,STACK_FRAME_OVERHEAD
1094 beq+ .ret_from_except_lite
1097 addi r3,r1,STACK_FRAME_OVERHEAD
1102 /* We have a page fault that hash_page could handle but HV refused
1106 addi r3,r1,STACK_FRAME_OVERHEAD
1111 /* here we have a segment miss */
1112 _GLOBAL(do_ste_alloc)
1113 bl .ste_allocate /* try to insert stab entry */
1115 beq+ fast_exception_return
1116 b .handle_page_fault
1119 * r13 points to the PACA, r9 contains the saved CR,
1120 * r11 and r12 contain the saved SRR0 and SRR1.
1121 * r9 - r13 are saved in paca->exslb.
1122 * We assume we aren't going to take any exceptions during this procedure.
1123 * We assume (DAR >> 60) == 0xc.
1126 _GLOBAL(do_stab_bolted)
1127 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1128 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1130 /* Hash to the primary group */
1131 ld r10,PACASTABVIRT(r13)
1134 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1136 /* Calculate VSID */
1137 /* This is a kernel address, so protovsid = ESID */
1138 ASM_VSID_SCRAMBLE(r11, r9)
1139 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1141 /* Search the primary group for a free entry */
1142 1: ld r11,0(r10) /* Test valid bit of the current ste */
1149 /* Stick for only searching the primary group for now. */
1150 /* At least for now, we use a very simple random castout scheme */
1151 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1153 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1156 /* r10 currently points to an ste one past the group of interest */
1157 /* make it point to the randomly selected entry */
1159 or r10,r10,r11 /* r10 is the entry to invalidate */
1161 isync /* mark the entry invalid */
1163 rldicl r11,r11,56,1 /* clear the valid bit */
1168 clrrdi r11,r11,28 /* Get the esid part of the ste */
1171 2: std r9,8(r10) /* Store the vsid part of the ste */
1174 mfspr r11,DAR /* Get the new esid */
1175 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1176 ori r11,r11,0x90 /* Turn on valid and kp */
1177 std r11,0(r10) /* Put new entry back into the stab */
1181 /* All done -- return from exception. */
1182 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1183 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1185 andi. r10,r12,MSR_RI
1188 mtcrf 0x80,r9 /* restore CR */
1196 ld r9,PACA_EXSLB+EX_R9(r13)
1197 ld r10,PACA_EXSLB+EX_R10(r13)
1198 ld r11,PACA_EXSLB+EX_R11(r13)
1199 ld r12,PACA_EXSLB+EX_R12(r13)
1200 ld r13,PACA_EXSLB+EX_R13(r13)
1202 b . /* prevent speculative execution */
1205 * r13 points to the PACA, r9 contains the saved CR,
1206 * r11 and r12 contain the saved SRR0 and SRR1.
1207 * r3 has the faulting address
1208 * r9 - r13 are saved in paca->exslb.
1209 * r3 is saved in paca->slb_r3
1210 * We assume we aren't going to take any exceptions during this procedure.
1212 _GLOBAL(do_slb_miss)
1215 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1216 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1218 bl .slb_allocate /* handle it */
1220 /* All done -- return from exception. */
1222 ld r10,PACA_EXSLB+EX_LR(r13)
1223 ld r3,PACA_EXSLB+EX_R3(r13)
1224 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1225 #ifdef CONFIG_PPC_ISERIES
1226 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1227 #endif /* CONFIG_PPC_ISERIES */
1231 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1237 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1240 #ifdef CONFIG_PPC_ISERIES
1243 #endif /* CONFIG_PPC_ISERIES */
1244 ld r9,PACA_EXSLB+EX_R9(r13)
1245 ld r10,PACA_EXSLB+EX_R10(r13)
1246 ld r11,PACA_EXSLB+EX_R11(r13)
1247 ld r12,PACA_EXSLB+EX_R12(r13)
1248 ld r13,PACA_EXSLB+EX_R13(r13)
1250 b . /* prevent speculative execution */
1253 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1256 1: addi r3,r1,STACK_FRAME_OVERHEAD
1257 bl .unrecoverable_exception
1261 * Space for CPU0's segment table.
1263 * On iSeries, the hypervisor must fill in at least one entry before
1264 * we get control (with relocate on). The address is give to the hv
1265 * as a page number (see xLparMap in LparData.c), so this must be at a
1266 * fixed address (the linker can't compute (u64)&initial_stab >>
1269 . = STAB0_PHYS_ADDR /* 0x6000 */
1275 * Data area reserved for FWNMI option.
1276 * This address (0x7000) is fixed by the RPA.
1279 .globl fwnmi_data_area
1284 * On pSeries, secondary processors spin in the following code.
1285 * At entry, r3 = this processor's number (physical cpu id)
1287 _GLOBAL(pSeries_secondary_smp_init)
1290 /* turn on 64-bit mode */
1294 /* Copy some CPU settings from CPU 0 */
1295 bl .__restore_cpu_setup
1297 /* Set up a paca value for this processor. Since we have the
1298 * physical cpu id in r24, we need to search the pacas to find
1299 * which logical id maps to our physical one.
1301 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1302 li r5,0 /* logical cpu id */
1303 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1304 cmpw r6,r24 /* Compare to our id */
1306 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1311 mr r3,r24 /* not found, copy phys to r3 */
1312 b .kexec_wait /* next kernel might do better */
1314 2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1315 /* From now on, r24 is expected to be logica cpuid */
1318 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1322 /* Create a temp kernel stack for use before relocation is on. */
1323 ld r1,PACAEMERGSP(r13)
1324 subi r1,r1,STACK_FRAME_OVERHEAD
1328 #ifdef SECONDARY_PROCESSORS
1329 bne .__secondary_start
1332 b 3b /* Loop until told to go */
1334 #ifdef CONFIG_PPC_ISERIES
1335 _STATIC(__start_initialization_iSeries)
1336 /* Clear out the BSS */
1337 LOADADDR(r11,__bss_stop)
1338 LOADADDR(r8,__bss_start)
1339 sub r11,r11,r8 /* bss size */
1340 addi r11,r11,7 /* round up to an even double word */
1341 rldicl. r11,r11,61,3 /* shift right by 3 */
1345 mtctr r11 /* zero this many doublewords */
1349 LOADADDR(r1,init_thread_union)
1350 addi r1,r1,THREAD_SIZE
1352 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1354 LOADADDR(r3,cpu_specs)
1355 LOADADDR(r4,cur_cpu_spec)
1359 LOADADDR(r2,__toc_start)
1363 bl .iSeries_early_setup
1365 /* relocation is on at this point */
1367 b .start_here_common
1368 #endif /* CONFIG_PPC_ISERIES */
1370 #ifdef CONFIG_PPC_MULTIPLATFORM
1374 andi. r0,r3,MSR_IR|MSR_DR
1381 b . /* prevent speculative execution */
1385 * Here is our main kernel entry point. We support currently 2 kind of entries
1386 * depending on the value of r5.
1388 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1391 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1392 * DT block, r4 is a physical pointer to the kernel itself
1395 _GLOBAL(__start_initialization_multiplatform)
1397 * Are we booted from a PROM Of-type client-interface ?
1400 bne .__boot_from_prom /* yes -> prom */
1402 /* Save parameters */
1406 /* Make sure we are running in 64 bits mode */
1409 /* Setup some critical 970 SPRs before switching MMU off */
1410 bl .__970_cpu_preinit
1415 /* Switch off MMU if not already */
1416 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1419 b .__after_prom_start
1421 _STATIC(__boot_from_prom)
1422 /* Save parameters */
1429 /* Make sure we are running in 64 bits mode */
1432 /* put a relocation offset into r3 */
1435 LOADADDR(r2,__toc_start)
1439 /* Relocate the TOC from a virt addr to a real addr */
1442 /* Restore parameters */
1449 /* Do all of the interaction with OF client interface */
1451 /* We never return */
1455 * At this point, r3 contains the physical address we are running at,
1456 * returned by prom_init()
1458 _STATIC(__after_prom_start)
1461 * We need to run with __start at physical address 0.
1462 * This will leave some code in the first 256B of
1463 * real memory, which are reserved for software use.
1464 * The remainder of the first page is loaded with the fixed
1465 * interrupt vectors. The next two pages are filled with
1466 * unknown exception placeholders.
1468 * Note: This process overwrites the OF exception vectors.
1469 * r26 == relocation offset
1474 SET_REG_TO_CONST(r27,KERNELBASE)
1476 li r3,0 /* target addr */
1478 // XXX FIXME: Use phys returned by OF (r30)
1479 sub r4,r27,r26 /* source addr */
1480 /* current address of _start */
1481 /* i.e. where we are running */
1482 /* the source addr */
1484 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1487 li r6,0x100 /* Start offset, the first 0x100 */
1488 /* bytes were copied earlier. */
1490 bl .copy_and_flush /* copy the first n bytes */
1491 /* this includes the code being */
1492 /* executed here. */
1494 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1495 mtctr r0 /* that we just made/relocated */
1498 4: LOADADDR(r5,klimit)
1500 ld r5,0(r5) /* get the value of klimit */
1502 bl .copy_and_flush /* copy the rest */
1503 b .start_here_multiplatform
1505 #endif /* CONFIG_PPC_MULTIPLATFORM */
1508 * Copy routine used to copy the kernel to start at physical address 0
1509 * and flush and invalidate the caches as needed.
1510 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1511 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1513 * Note: this routine *only* clobbers r0, r6 and lr
1515 _GLOBAL(copy_and_flush)
1518 4: li r0,16 /* Use the least common */
1519 /* denominator cache line */
1520 /* size. This results in */
1521 /* extra cache line flushes */
1522 /* but operation is correct. */
1523 /* Can't get cache line size */
1524 /* from NACA as it is being */
1527 mtctr r0 /* put # words/line in ctr */
1528 3: addi r6,r6,8 /* copy a cache line */
1532 dcbst r6,r3 /* write it to memory */
1534 icbi r6,r3 /* flush the icache line */
1546 #ifdef CONFIG_PPC_PMAC
1548 * On PowerMac, secondary processors starts from the reset vector, which
1549 * is temporarily turned into a call to one of the functions below.
1554 .globl pmac_secondary_start_1
1555 pmac_secondary_start_1:
1557 b .pmac_secondary_start
1559 .globl pmac_secondary_start_2
1560 pmac_secondary_start_2:
1562 b .pmac_secondary_start
1564 .globl pmac_secondary_start_3
1565 pmac_secondary_start_3:
1567 b .pmac_secondary_start
1569 _GLOBAL(pmac_secondary_start)
1570 /* turn on 64-bit mode */
1574 /* Copy some CPU settings from CPU 0 */
1575 bl .__restore_cpu_setup
1577 /* pSeries do that early though I don't think we really need it */
1580 mtmsrd r3 /* RI on */
1582 /* Set up a paca value for this processor. */
1583 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1584 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1585 add r13,r13,r4 /* for this processor. */
1586 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1588 /* Create a temp kernel stack for use before relocation is on. */
1589 ld r1,PACAEMERGSP(r13)
1590 subi r1,r1,STACK_FRAME_OVERHEAD
1592 b .__secondary_start
1594 #endif /* CONFIG_PPC_PMAC */
1597 * This function is called after the master CPU has released the
1598 * secondary processors. The execution environment is relocation off.
1599 * The paca for this processor has the following fields initialized at
1601 * 1. Processor number
1602 * 2. Segment table pointer (virtual address)
1603 * On entry the following are set:
1604 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1605 * r24 = cpu# (in Linux terms)
1606 * r13 = paca virtual address
1607 * SPRG3 = paca virtual address
1609 _GLOBAL(__secondary_start)
1611 HMT_MEDIUM /* Set thread priority to MEDIUM */
1615 stb r6,PACAPROCENABLED(r13)
1617 #ifndef CONFIG_PPC_ISERIES
1618 /* Initialize the page table pointer register. */
1620 ld r6,0(r6) /* get the value of _SDR1 */
1621 mtspr SDR1,r6 /* set the htab location */
1623 /* Initialize the first segment table (or SLB) entry */
1624 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1627 /* Initialize the kernel stack. Just a repeat for iSeries. */
1628 LOADADDR(r3,current_set)
1629 sldi r28,r24,3 /* get current_set[cpu#] */
1631 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1632 std r1,PACAKSAVE(r13)
1634 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1635 ori r4,r3,1 /* turn on valid bit */
1637 #ifdef CONFIG_PPC_ISERIES
1638 li r0,-1 /* hypervisor call */
1640 sldi r3,r3,63 /* 0x8000000000000000 */
1641 ori r3,r3,4 /* 0x8000000000000004 */
1642 sc /* HvCall_setASR */
1645 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1646 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1647 cmpldi r3,PLATFORM_PSERIES_LPAR
1651 cmpwi r3,0x37 /* SStar */
1653 cmpwi r3,0x36 /* IStar */
1655 cmpwi r3,0x34 /* Pulsar */
1657 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1658 HVSC /* Invoking hcall */
1660 98: /* !(rpa hypervisor) || !(star) */
1661 mtasr r4 /* set the stab location */
1667 /* enable MMU and jump to start_secondary */
1668 LOADADDR(r3,.start_secondary_prolog)
1669 SET_REG_TO_CONST(r4, MSR_KERNEL)
1670 #ifdef DO_SOFT_DISABLE
1676 b . /* prevent speculative execution */
1679 * Running with relocation on at this point. All we want to do is
1680 * zero the stack back-chain pointer before going into C code.
1682 _GLOBAL(start_secondary_prolog)
1684 std r3,0(r1) /* Zero the stack frame pointer */
1689 * This subroutine clobbers r11 and r12
1691 _GLOBAL(enable_64b_mode)
1692 mfmsr r11 /* grab the current MSR */
1694 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1697 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1703 #ifdef CONFIG_PPC_MULTIPLATFORM
1705 * This is where the main kernel code starts.
1707 _STATIC(start_here_multiplatform)
1708 /* get a new offset, now that the kernel has moved. */
1712 /* Clear out the BSS. It may have been done in prom_init,
1713 * already but that's irrelevant since prom_init will soon
1714 * be detached from the kernel completely. Besides, we need
1715 * to clear it now for kexec-style entry.
1717 LOADADDR(r11,__bss_stop)
1718 LOADADDR(r8,__bss_start)
1719 sub r11,r11,r8 /* bss size */
1720 addi r11,r11,7 /* round up to an even double word */
1721 rldicl. r11,r11,61,3 /* shift right by 3 */
1725 mtctr r11 /* zero this many doublewords */
1732 mtmsrd r6 /* RI on */
1735 /* Start up the second thread on cpu 0 */
1738 cmpwi r3,0x34 /* Pulsar */
1740 cmpwi r3,0x36 /* Icestar */
1742 cmpwi r3,0x37 /* SStar */
1744 b 91f /* HMT not supported */
1746 bl .hmt_start_secondary
1750 /* The following gets the stack and TOC set up with the regs */
1751 /* pointing to the real addr of the kernel stack. This is */
1752 /* all done to support the C function call below which sets */
1753 /* up the htab. This is done because we have relocated the */
1754 /* kernel but are still running in real mode. */
1756 LOADADDR(r3,init_thread_union)
1759 /* set up a stack pointer (physical address) */
1760 addi r1,r3,THREAD_SIZE
1762 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1764 /* set up the TOC (physical address) */
1765 LOADADDR(r2,__toc_start)
1770 LOADADDR(r3,cpu_specs)
1772 LOADADDR(r4,cur_cpu_spec)
1777 /* Save some low level config HIDs of CPU0 to be copied to
1778 * other CPUs later on, or used for suspend/resume
1780 bl .__save_cpu_setup
1783 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1784 * note that boot_cpuid can always be 0 nowadays since there is
1785 * nowhere it can be initialized differently before we reach this
1788 LOADADDR(r27, boot_cpuid)
1792 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1793 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1794 add r13,r13,r24 /* for this processor. */
1795 sub r13,r13,r26 /* convert to physical addr */
1796 mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
1798 /* Do very early kernel initializations, including initial hash table,
1799 * stab and slb setup before we turn on relocation. */
1801 /* Restore parameters passed from prom_init/kexec */
1806 ld r3,PACASTABREAL(r13)
1807 ori r4,r3,1 /* turn on valid bit */
1808 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1809 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1810 cmpldi r3,PLATFORM_PSERIES_LPAR
1814 cmpwi r3,0x37 /* SStar */
1816 cmpwi r3,0x36 /* IStar */
1818 cmpwi r3,0x34 /* Pulsar */
1820 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1821 HVSC /* Invoking hcall */
1823 98: /* !(rpa hypervisor) || !(star) */
1824 mtasr r4 /* set the stab location */
1826 /* Set SDR1 (hash table pointer) */
1827 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1828 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1829 /* Test if bit 0 is set (LPAR bit) */
1832 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1834 ld r6,0(r6) /* get the value of _SDR1 */
1835 mtspr SDR1,r6 /* set the htab location */
1837 LOADADDR(r3,.start_here_common)
1838 SET_REG_TO_CONST(r4, MSR_KERNEL)
1842 b . /* prevent speculative execution */
1843 #endif /* CONFIG_PPC_MULTIPLATFORM */
1845 /* This is where all platforms converge execution */
1846 _STATIC(start_here_common)
1847 /* relocation is on at this point */
1849 /* The following code sets up the SP and TOC now that we are */
1850 /* running with translation enabled. */
1852 LOADADDR(r3,init_thread_union)
1854 /* set up the stack */
1855 addi r1,r3,THREAD_SIZE
1857 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1859 /* Apply the CPUs-specific fixups (nop out sections not relevant
1863 bl .do_cpu_ftr_fixups
1865 LOADADDR(r26, boot_cpuid)
1868 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1869 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1870 add r13,r13,r24 /* for this processor. */
1873 /* ptr to current */
1874 LOADADDR(r4,init_task)
1875 std r4,PACACURRENT(r13)
1879 std r1,PACAKSAVE(r13)
1883 /* Load up the kernel context */
1885 #ifdef DO_SOFT_DISABLE
1887 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1889 ori r5,r5,MSR_EE /* Hard Enabled */
1897 LOADADDR(r5, hmt_thread_data)
1900 cmpwi r7,0x34 /* Pulsar */
1902 cmpwi r7,0x36 /* Icestar */
1904 cmpwi r7,0x37 /* SStar */
1914 bl .hmt_start_secondary
1917 __hmt_secondary_hold:
1918 LOADADDR(r5, hmt_thread_data)
1928 93: andi. r6,r6,0x3f
1942 b .pSeries_secondary_smp_init
1945 _GLOBAL(hmt_start_secondary)
1946 LOADADDR(r4,__hmt_secondary_hold)
1961 mfspr r4, SPRN_CTRLF
1963 mtspr SPRN_CTRLT, r4
1967 #if defined(CONFIG_KEXEC) || (defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES))
1968 _GLOBAL(smp_release_cpus)
1969 /* All secondary cpus are spinning on a common
1970 * spinloop, release them all now so they can start
1971 * to spin on their individual paca spinloops.
1972 * For non SMP kernels, the secondary cpus never
1973 * get out of the common spinloop.
1976 LOADADDR(r5,__secondary_hold_spinloop)
1980 #endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */
1984 * We put a few things here that have to be page-aligned.
1985 * This stuff goes at the beginning of the data segment,
1986 * which is page-aligned.
1992 .globl empty_zero_page
1996 .globl swapper_pg_dir
2001 * This space gets a copy of optional info passed to us by the bootstrap
2002 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2006 .space COMMAND_LINE_SIZE