git.oblomov.eu Git - linux-2.6/blob - drivers/char/drm/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
  35                        dev->pci_device == 0x2982 || \
  36                        dev->pci_device == 0x2992 || \
  37                        dev->pci_device == 0x29A2 || \
  38                        dev->pci_device == 0x2A02 || \
  39                        dev->pci_device == 0x2A12)
  40
  41 #define IS_G33(dev) (dev->pci_device == 0x29b2 || \
  42                      dev->pci_device == 0x29c2 || \
  43                      dev->pci_device == 0x29d2)
  44
  45 /* Really want an OS-independent resettable timer.  Would like to have
  46  * this loop run for (eg) 3 sec, but have the timer reset every time
  47  * the head pointer changes, so that EBUSY only happens if the ring
  48  * actually stalls for (eg) 3 seconds.
  49  */
  50 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  54         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  55         int i;
  56
  57         for (i = 0; i < 10000; i++) {
  58                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  59                 ring->space = ring->head - (ring->tail + 8);
  60                 if (ring->space < 0)
  61                         ring->space += ring->Size;
  62                 if (ring->space >= n)
  63                         return 0;
  64
  65                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  66
  67                 if (ring->head != last_head)
  68                         i = 0;
  69
  70                 last_head = ring->head;
  71         }
  72
  73         return DRM_ERR(EBUSY);
  74 }
  75
  76 void i915_kernel_lost_context(struct drm_device * dev)
  77 {
  78         drm_i915_private_t *dev_priv = dev->dev_private;
  79         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  80
  81         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  82         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  83         ring->space = ring->head - (ring->tail + 8);
  84         if (ring->space < 0)
  85                 ring->space += ring->Size;
  86
  87         if (ring->head == ring->tail)
  88                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  89 }
  90
  91 static int i915_dma_cleanup(struct drm_device * dev)
  92 {
  93         /* Make sure interrupts are disabled here because the uninstall ioctl
  94          * may not have been called from userspace and after dev_private
  95          * is freed, it's too late.
  96          */
  97         if (dev->irq)
  98                 drm_irq_uninstall(dev);
  99
 100         if (dev->dev_private) {
 101                 drm_i915_private_t *dev_priv =
 102                     (drm_i915_private_t *) dev->dev_private;
 103
 104                 if (dev_priv->ring.virtual_start) {
 105                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 106                 }
 107
 108                 if (dev_priv->status_page_dmah) {
 109                         drm_pci_free(dev, dev_priv->status_page_dmah);
 110                         /* Need to rewrite hardware status page */
 111                         I915_WRITE(0x02080, 0x1ffff000);
 112                 }
 113
 114                 if (dev_priv->status_gfx_addr) {
 115                         dev_priv->status_gfx_addr = 0;
 116                         drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117                         I915_WRITE(0x2080, 0x1ffff000);
 118                 }
 119
 120                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 121                          DRM_MEM_DRIVER);
 122
 123                 dev->dev_private = NULL;
 124         }
 125
 126         return 0;
 127 }
 128
 129 static int i915_initialize(struct drm_device * dev,
 130                            drm_i915_private_t * dev_priv,
 131                            drm_i915_init_t * init)
 132 {
 133         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 134
 135         dev_priv->sarea = drm_getsarea(dev);
 136         if (!dev_priv->sarea) {
 137                 DRM_ERROR("can not find sarea!\n");
 138                 dev->dev_private = (void *)dev_priv;
 139                 i915_dma_cleanup(dev);
 140                 return DRM_ERR(EINVAL);
 141         }
 142
 143         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 144         if (!dev_priv->mmio_map) {
 145                 dev->dev_private = (void *)dev_priv;
 146                 i915_dma_cleanup(dev);
 147                 DRM_ERROR("can not find mmio map!\n");
 148                 return DRM_ERR(EINVAL);
 149         }
 150
 151         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 152             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 153
 154         dev_priv->ring.Start = init->ring_start;
 155         dev_priv->ring.End = init->ring_end;
 156         dev_priv->ring.Size = init->ring_size;
 157         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 158
 159         dev_priv->ring.map.offset = init->ring_start;
 160         dev_priv->ring.map.size = init->ring_size;
 161         dev_priv->ring.map.type = 0;
 162         dev_priv->ring.map.flags = 0;
 163         dev_priv->ring.map.mtrr = 0;
 164
 165         drm_core_ioremap(&dev_priv->ring.map, dev);
 166
 167         if (dev_priv->ring.map.handle == NULL) {
 168                 dev->dev_private = (void *)dev_priv;
 169                 i915_dma_cleanup(dev);
 170                 DRM_ERROR("can not ioremap virtual address for"
 171                           " ring buffer\n");
 172                 return DRM_ERR(ENOMEM);
 173         }
 174
 175         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 176
 177         dev_priv->cpp = init->cpp;
 178         dev_priv->back_offset = init->back_offset;
 179         dev_priv->front_offset = init->front_offset;
 180         dev_priv->current_page = 0;
 181         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 182
 183         /* We are using separate values as placeholders for mechanisms for
 184          * private backbuffer/depthbuffer usage.
 185          */
 186         dev_priv->use_mi_batchbuffer_start = 0;
 187         if (IS_I965G(dev)) /* 965 doesn't support older method */
 188                 dev_priv->use_mi_batchbuffer_start = 1;
 189
 190         /* Allow hardware batchbuffers unless told otherwise.
 191          */
 192         dev_priv->allow_batchbuffer = 1;
 193
 194         /* Program Hardware Status Page */
 195         if (!IS_G33(dev)) {
 196                 dev_priv->status_page_dmah =
 197                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 198
 199                 if (!dev_priv->status_page_dmah) {
 200                         dev->dev_private = (void *)dev_priv;
 201                         i915_dma_cleanup(dev);
 202                         DRM_ERROR("Can not allocate hardware status page\n");
 203                         return DRM_ERR(ENOMEM);
 204                 }
 205                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 206                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 207
 208                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 209                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 210         }
 211         DRM_DEBUG("Enabled hardware status page\n");
 212         dev->dev_private = (void *)dev_priv;
 213         return 0;
 214 }
 215
 216 static int i915_dma_resume(struct drm_device * dev)
 217 {
 218         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 219
 220         DRM_DEBUG("%s\n", __FUNCTION__);
 221
 222         if (!dev_priv->sarea) {
 223                 DRM_ERROR("can not find sarea!\n");
 224                 return DRM_ERR(EINVAL);
 225         }
 226
 227         if (!dev_priv->mmio_map) {
 228                 DRM_ERROR("can not find mmio map!\n");
 229                 return DRM_ERR(EINVAL);
 230         }
 231
 232         if (dev_priv->ring.map.handle == NULL) {
 233                 DRM_ERROR("can not ioremap virtual address for"
 234                           " ring buffer\n");
 235                 return DRM_ERR(ENOMEM);
 236         }
 237
 238         /* Program Hardware Status Page */
 239         if (!dev_priv->hw_status_page) {
 240                 DRM_ERROR("Can not find hardware status page\n");
 241                 return DRM_ERR(EINVAL);
 242         }
 243         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 244
 245         if (dev_priv->status_gfx_addr != 0)
 246                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 247         else
 248                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 249         DRM_DEBUG("Enabled hardware status page\n");
 250
 251         return 0;
 252 }
 253
 254 static int i915_dma_init(DRM_IOCTL_ARGS)
 255 {
 256         DRM_DEVICE;
 257         drm_i915_private_t *dev_priv;
 258         drm_i915_init_t init;
 259         int retcode = 0;
 260
 261         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 262                                  sizeof(init));
 263
 264         switch (init.func) {
 265         case I915_INIT_DMA:
 266                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 267                                      DRM_MEM_DRIVER);
 268                 if (dev_priv == NULL)
 269                         return DRM_ERR(ENOMEM);
 270                 retcode = i915_initialize(dev, dev_priv, &init);
 271                 break;
 272         case I915_CLEANUP_DMA:
 273                 retcode = i915_dma_cleanup(dev);
 274                 break;
 275         case I915_RESUME_DMA:
 276                 retcode = i915_dma_resume(dev);
 277                 break;
 278         default:
 279                 retcode = DRM_ERR(EINVAL);
 280                 break;
 281         }
 282
 283         return retcode;
 284 }
 285
 286 /* Implement basically the same security restrictions as hardware does
 287  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 288  *
 289  * Most of the calculations below involve calculating the size of a
 290  * particular instruction.  It's important to get the size right as
 291  * that tells us where the next instruction to check is.  Any illegal
 292  * instruction detected will be given a size of zero, which is a
 293  * signal to abort the rest of the buffer.
 294  */
 295 static int do_validate_cmd(int cmd)
 296 {
 297         switch (((cmd >> 29) & 0x7)) {
 298         case 0x0:
 299                 switch ((cmd >> 23) & 0x3f) {
 300                 case 0x0:
 301                         return 1;       /* MI_NOOP */
 302                 case 0x4:
 303                         return 1;       /* MI_FLUSH */
 304                 default:
 305                         return 0;       /* disallow everything else */
 306                 }
 307                 break;
 308         case 0x1:
 309                 return 0;       /* reserved */
 310         case 0x2:
 311                 return (cmd & 0xff) + 2;        /* 2d commands */
 312         case 0x3:
 313                 if (((cmd >> 24) & 0x1f) <= 0x18)
 314                         return 1;
 315
 316                 switch ((cmd >> 24) & 0x1f) {
 317                 case 0x1c:
 318                         return 1;
 319                 case 0x1d:
 320                         switch ((cmd >> 16) & 0xff) {
 321                         case 0x3:
 322                                 return (cmd & 0x1f) + 2;
 323                         case 0x4:
 324                                 return (cmd & 0xf) + 2;
 325                         default:
 326                                 return (cmd & 0xffff) + 2;
 327                         }
 328                 case 0x1e:
 329                         if (cmd & (1 << 23))
 330                                 return (cmd & 0xffff) + 1;
 331                         else
 332                                 return 1;
 333                 case 0x1f:
 334                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 335                                 return (cmd & 0x1ffff) + 2;
 336                         else if (cmd & (1 << 17))       /* indirect random */
 337                                 if ((cmd & 0xffff) == 0)
 338                                         return 0;       /* unknown length, too hard */
 339                                 else
 340                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 341                         else
 342                                 return 2;       /* indirect sequential */
 343                 default:
 344                         return 0;
 345                 }
 346         default:
 347                 return 0;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int validate_cmd(int cmd)
 354 {
 355         int ret = do_validate_cmd(cmd);
 356
 357 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 358
 359         return ret;
 360 }
 361
 362 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 363 {
 364         drm_i915_private_t *dev_priv = dev->dev_private;
 365         int i;
 366         RING_LOCALS;
 367
 368         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 369                 return DRM_ERR(EINVAL);
 370
 371         BEGIN_LP_RING((dwords+1)&~1);
 372
 373         for (i = 0; i < dwords;) {
 374                 int cmd, sz;
 375
 376                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 377                         return DRM_ERR(EINVAL);
 378
 379                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 380                         return DRM_ERR(EINVAL);
 381
 382                 OUT_RING(cmd);
 383
 384                 while (++i, --sz) {
 385                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 386                                                          sizeof(cmd))) {
 387                                 return DRM_ERR(EINVAL);
 388                         }
 389                         OUT_RING(cmd);
 390                 }
 391         }
 392
 393         if (dwords & 1)
 394                 OUT_RING(0);
 395
 396         ADVANCE_LP_RING();
 397
 398         return 0;
 399 }
 400
 401 static int i915_emit_box(struct drm_device * dev,
 402                          struct drm_clip_rect __user * boxes,
 403                          int i, int DR1, int DR4)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         struct drm_clip_rect box;
 407         RING_LOCALS;
 408
 409         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 410                 return DRM_ERR(EFAULT);
 411         }
 412
 413         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 414                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 415                           box.x1, box.y1, box.x2, box.y2);
 416                 return DRM_ERR(EINVAL);
 417         }
 418
 419         if (IS_I965G(dev)) {
 420                 BEGIN_LP_RING(4);
 421                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 422                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 423                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 424                 OUT_RING(DR4);
 425                 ADVANCE_LP_RING();
 426         } else {
 427                 BEGIN_LP_RING(6);
 428                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 429                 OUT_RING(DR1);
 430                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 431                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 432                 OUT_RING(DR4);
 433                 OUT_RING(0);
 434                 ADVANCE_LP_RING();
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* XXX: Emitting the counter should really be moved to part of the IRQ
 441  * emit. For now, do it in both places:
 442  */
 443
 444 static void i915_emit_breadcrumb(struct drm_device *dev)
 445 {
 446         drm_i915_private_t *dev_priv = dev->dev_private;
 447         RING_LOCALS;
 448
 449         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 450
 451         if (dev_priv->counter > 0x7FFFFFFFUL)
 452                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 453
 454         BEGIN_LP_RING(4);
 455         OUT_RING(CMD_STORE_DWORD_IDX);
 456         OUT_RING(20);
 457         OUT_RING(dev_priv->counter);
 458         OUT_RING(0);
 459         ADVANCE_LP_RING();
 460 }
 461
 462 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 463                                    drm_i915_cmdbuffer_t * cmd)
 464 {
 465         int nbox = cmd->num_cliprects;
 466         int i = 0, count, ret;
 467
 468         if (cmd->sz & 0x3) {
 469                 DRM_ERROR("alignment");
 470                 return DRM_ERR(EINVAL);
 471         }
 472
 473         i915_kernel_lost_context(dev);
 474
 475         count = nbox ? nbox : 1;
 476
 477         for (i = 0; i < count; i++) {
 478                 if (i < nbox) {
 479                         ret = i915_emit_box(dev, cmd->cliprects, i,
 480                                             cmd->DR1, cmd->DR4);
 481                         if (ret)
 482                                 return ret;
 483                 }
 484
 485                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         i915_emit_breadcrumb(dev);
 491         return 0;
 492 }
 493
 494 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 495                                      drm_i915_batchbuffer_t * batch)
 496 {
 497         drm_i915_private_t *dev_priv = dev->dev_private;
 498         struct drm_clip_rect __user *boxes = batch->cliprects;
 499         int nbox = batch->num_cliprects;
 500         int i = 0, count;
 501         RING_LOCALS;
 502
 503         if ((batch->start | batch->used) & 0x7) {
 504                 DRM_ERROR("alignment");
 505                 return DRM_ERR(EINVAL);
 506         }
 507
 508         i915_kernel_lost_context(dev);
 509
 510         count = nbox ? nbox : 1;
 511
 512         for (i = 0; i < count; i++) {
 513                 if (i < nbox) {
 514                         int ret = i915_emit_box(dev, boxes, i,
 515                                                 batch->DR1, batch->DR4);
 516                         if (ret)
 517                                 return ret;
 518                 }
 519
 520                 if (dev_priv->use_mi_batchbuffer_start) {
 521                         BEGIN_LP_RING(2);
 522                         if (IS_I965G(dev)) {
 523                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 524                                 OUT_RING(batch->start);
 525                         } else {
 526                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 527                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 528                         }
 529                         ADVANCE_LP_RING();
 530                 } else {
 531                         BEGIN_LP_RING(4);
 532                         OUT_RING(MI_BATCH_BUFFER);
 533                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 534                         OUT_RING(batch->start + batch->used - 4);
 535                         OUT_RING(0);
 536                         ADVANCE_LP_RING();
 537                 }
 538         }
 539
 540         i915_emit_breadcrumb(dev);
 541
 542         return 0;
 543 }
 544
 545 static int i915_dispatch_flip(struct drm_device * dev)
 546 {
 547         drm_i915_private_t *dev_priv = dev->dev_private;
 548         RING_LOCALS;
 549
 550         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 551                   __FUNCTION__,
 552                   dev_priv->current_page,
 553                   dev_priv->sarea_priv->pf_current_page);
 554
 555         i915_kernel_lost_context(dev);
 556
 557         BEGIN_LP_RING(2);
 558         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 559         OUT_RING(0);
 560         ADVANCE_LP_RING();
 561
 562         BEGIN_LP_RING(6);
 563         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 564         OUT_RING(0);
 565         if (dev_priv->current_page == 0) {
 566                 OUT_RING(dev_priv->back_offset);
 567                 dev_priv->current_page = 1;
 568         } else {
 569                 OUT_RING(dev_priv->front_offset);
 570                 dev_priv->current_page = 0;
 571         }
 572         OUT_RING(0);
 573         ADVANCE_LP_RING();
 574
 575         BEGIN_LP_RING(2);
 576         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 577         OUT_RING(0);
 578         ADVANCE_LP_RING();
 579
 580         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 581
 582         BEGIN_LP_RING(4);
 583         OUT_RING(CMD_STORE_DWORD_IDX);
 584         OUT_RING(20);
 585         OUT_RING(dev_priv->counter);
 586         OUT_RING(0);
 587         ADVANCE_LP_RING();
 588
 589         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 590         return 0;
 591 }
 592
 593 static int i915_quiescent(struct drm_device * dev)
 594 {
 595         drm_i915_private_t *dev_priv = dev->dev_private;
 596
 597         i915_kernel_lost_context(dev);
 598         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 599 }
 600
 601 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 602 {
 603         DRM_DEVICE;
 604
 605         LOCK_TEST_WITH_RETURN(dev, filp);
 606
 607         return i915_quiescent(dev);
 608 }
 609
 610 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 611 {
 612         DRM_DEVICE;
 613         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 614         u32 *hw_status = dev_priv->hw_status_page;
 615         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 616             dev_priv->sarea_priv;
 617         drm_i915_batchbuffer_t batch;
 618         int ret;
 619
 620         if (!dev_priv->allow_batchbuffer) {
 621                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 622                 return DRM_ERR(EINVAL);
 623         }
 624
 625         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 626                                  sizeof(batch));
 627
 628         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 629                   batch.start, batch.used, batch.num_cliprects);
 630
 631         LOCK_TEST_WITH_RETURN(dev, filp);
 632
 633         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 634                                                        batch.num_cliprects *
 635                                                        sizeof(struct drm_clip_rect)))
 636                 return DRM_ERR(EFAULT);
 637
 638         ret = i915_dispatch_batchbuffer(dev, &batch);
 639
 640         sarea_priv->last_dispatch = (int)hw_status[5];
 641         return ret;
 642 }
 643
 644 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 645 {
 646         DRM_DEVICE;
 647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 648         u32 *hw_status = dev_priv->hw_status_page;
 649         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 650             dev_priv->sarea_priv;
 651         drm_i915_cmdbuffer_t cmdbuf;
 652         int ret;
 653
 654         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 655                                  sizeof(cmdbuf));
 656
 657         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 658                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 659
 660         LOCK_TEST_WITH_RETURN(dev, filp);
 661
 662         if (cmdbuf.num_cliprects &&
 663             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 664                                 cmdbuf.num_cliprects *
 665                                 sizeof(struct drm_clip_rect))) {
 666                 DRM_ERROR("Fault accessing cliprects\n");
 667                 return DRM_ERR(EFAULT);
 668         }
 669
 670         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 671         if (ret) {
 672                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 673                 return ret;
 674         }
 675
 676         sarea_priv->last_dispatch = (int)hw_status[5];
 677         return 0;
 678 }
 679
 680 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 681 {
 682         DRM_DEVICE;
 683
 684         DRM_DEBUG("%s\n", __FUNCTION__);
 685
 686         LOCK_TEST_WITH_RETURN(dev, filp);
 687
 688         return i915_dispatch_flip(dev);
 689 }
 690
 691 static int i915_getparam(DRM_IOCTL_ARGS)
 692 {
 693         DRM_DEVICE;
 694         drm_i915_private_t *dev_priv = dev->dev_private;
 695         drm_i915_getparam_t param;
 696         int value;
 697
 698         if (!dev_priv) {
 699                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 700                 return DRM_ERR(EINVAL);
 701         }
 702
 703         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 704                                  sizeof(param));
 705
 706         switch (param.param) {
 707         case I915_PARAM_IRQ_ACTIVE:
 708                 value = dev->irq ? 1 : 0;
 709                 break;
 710         case I915_PARAM_ALLOW_BATCHBUFFER:
 711                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 712                 break;
 713         case I915_PARAM_LAST_DISPATCH:
 714                 value = READ_BREADCRUMB(dev_priv);
 715                 break;
 716         default:
 717                 DRM_ERROR("Unknown parameter %d\n", param.param);
 718                 return DRM_ERR(EINVAL);
 719         }
 720
 721         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 722                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 723                 return DRM_ERR(EFAULT);
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int i915_setparam(DRM_IOCTL_ARGS)
 730 {
 731         DRM_DEVICE;
 732         drm_i915_private_t *dev_priv = dev->dev_private;
 733         drm_i915_setparam_t param;
 734
 735         if (!dev_priv) {
 736                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 737                 return DRM_ERR(EINVAL);
 738         }
 739
 740         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 741                                  sizeof(param));
 742
 743         switch (param.param) {
 744         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 745                 if (!IS_I965G(dev))
 746                         dev_priv->use_mi_batchbuffer_start = param.value;
 747                 break;
 748         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 749                 dev_priv->tex_lru_log_granularity = param.value;
 750                 break;
 751         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 752                 dev_priv->allow_batchbuffer = param.value;
 753                 break;
 754         default:
 755                 DRM_ERROR("unknown parameter %d\n", param.param);
 756                 return DRM_ERR(EINVAL);
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int i915_set_status_page(DRM_IOCTL_ARGS)
 763 {
 764         DRM_DEVICE;
 765         drm_i915_private_t *dev_priv = dev->dev_private;
 766         drm_i915_hws_addr_t hws;
 767
 768         if (!dev_priv) {
 769                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 770                 return DRM_ERR(EINVAL);
 771         }
 772         DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data,
 773                         sizeof(hws));
 774         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws.addr);
 775
 776         dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
 777
 778         dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr;
 779         dev_priv->hws_map.size = 4*1024;
 780         dev_priv->hws_map.type = 0;
 781         dev_priv->hws_map.flags = 0;
 782         dev_priv->hws_map.mtrr = 0;
 783
 784         drm_core_ioremap(&dev_priv->hws_map, dev);
 785         if (dev_priv->hws_map.handle == NULL) {
 786                 dev->dev_private = (void *)dev_priv;
 787                 i915_dma_cleanup(dev);
 788                 dev_priv->status_gfx_addr = 0;
 789                 DRM_ERROR("can not ioremap virtual address for"
 790                                 " G33 hw status page\n");
 791                 return DRM_ERR(ENOMEM);
 792         }
 793         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 794
 795         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 796         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 797         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
 798                         dev_priv->status_gfx_addr);
 799         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 800         return 0;
 801 }
 802
 803 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 804 {
 805         /* i915 has 4 more counters */
 806         dev->counters += 4;
 807         dev->types[6] = _DRM_STAT_IRQ;
 808         dev->types[7] = _DRM_STAT_PRIMARY;
 809         dev->types[8] = _DRM_STAT_SECONDARY;
 810         dev->types[9] = _DRM_STAT_DMA;
 811
 812         return 0;
 813 }
 814
 815 void i915_driver_lastclose(struct drm_device * dev)
 816 {
 817         if (dev->dev_private) {
 818                 drm_i915_private_t *dev_priv = dev->dev_private;
 819                 i915_mem_takedown(&(dev_priv->agp_heap));
 820         }
 821         i915_dma_cleanup(dev);
 822 }
 823
 824 void i915_driver_preclose(struct drm_device * dev, DRMFILE filp)
 825 {
 826         if (dev->dev_private) {
 827                 drm_i915_private_t *dev_priv = dev->dev_private;
 828                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 829         }
 830 }
 831
 832 drm_ioctl_desc_t i915_ioctls[] = {
 833         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 834         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 835         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 836         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 837         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 838         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 839         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 840         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 841         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 842         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 843         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 844         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 845         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 846         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 847         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 848         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 849         [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH},
 850 };
 851
 852 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 853
 854 /**
 855  * Determine if the device really is AGP or not.
 856  *
 857  * All Intel graphics chipsets are treated as AGP, even if they are really
 858  * PCI-e.
 859  *
 860  * \param dev   The device to be tested.
 861  *
 862  * \returns
 863  * A value of 1 is always retured to indictate every i9x5 is AGP.
 864  */
 865 int i915_driver_device_is_agp(struct drm_device * dev)
 866 {
 867         return 1;
 868 }