2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <dev/aic7xxx/aic7xxx_osm.h>
49 #include <dev/aic7xxx/aic7xxx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
71 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
74 * Hardware error codes.
76 struct ahc_hard_error_entry {
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referrenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" },
85 { SQPARERR, "Sequencer Parity Error" },
86 { DPARERR, "Data-path Parity Error" },
87 { MPARERR, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT, "PCI Error detected" },
89 { CIOPARERR, "CIOBUS Parity Error" },
91 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
93 static struct ahc_phase_table_entry ahc_phase_table[] =
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
99 { P_COMMAND, MSG_NOOP, "in Command phase" },
100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
103 { P_BUSFREE, MSG_NOOP, "while idle" },
104 { 0, MSG_NOOP, "in unknown phase" }
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
111 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
118 static struct ahc_syncrate ahc_syncrates[] =
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL }
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc *ahc,
143 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145 ahc_alloc_tstate(struct ahc_softc *ahc,
146 u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force);
151 static struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *,
157 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
159 struct ahc_devinfo *devinfo);
160 static void ahc_scb_devinfo(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
163 static void ahc_assert_atn(struct ahc_softc *ahc);
164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
167 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo);
169 static void ahc_construct_sdtr(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 u_int period, u_int offset);
172 static void ahc_construct_wdtr(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo,
175 static void ahc_construct_ppr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset,
178 u_int bus_width, u_int ppr_options);
179 static void ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void ahc_handle_message_phase(struct ahc_softc *ahc);
187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188 u_int msgval, int full);
189 static int ahc_parse_msg(struct ahc_softc *ahc,
190 struct ahc_devinfo *devinfo);
191 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
192 struct ahc_devinfo *devinfo);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void ahc_handle_devreset(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo,
198 cam_status status, char *message,
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
206 static bus_dmamap_callback_t ahc_dmamap_cb;
207 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int ahc_init_scbdata(struct ahc_softc *ahc);
209 static void ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb,
213 static int ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215 u_int prev, u_int scbptr);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
218 u_int scbpos, u_int prev);
219 static void ahc_reset_current_bus(struct ahc_softc *ahc);
221 static void ahc_dumpseq(struct ahc_softc *ahc);
223 static int ahc_loadseq(struct ahc_softc *ahc);
224 static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr);
227 static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts);
229 #ifdef AHC_TARGET_MODE
230 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
231 struct ahc_tmode_lstate *lstate,
235 static void ahc_update_scsiid(struct ahc_softc *ahc,
237 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
238 struct target_cmd *cmd);
240 /************************* Sequencer Execution Control ************************/
242 * Restart the sequencer program from address zero
245 ahc_restart(struct ahc_softc *ahc)
250 /* No more pending messages. */
251 ahc_clear_msg_state(ahc);
253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
256 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
257 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
258 ahc_outb(ahc, SAVED_LUN, 0xFF);
261 * Ensure that the sequencer's idea of TQINPOS
262 * matches our own. The sequencer increments TQINPOS
263 * only after it sees a DMA complete and a reset could
264 * occur before the increment leaving the kernel to believe
265 * the command arrived but the sequencer to not.
267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
269 /* Always allow reselection */
270 ahc_outb(ahc, SCSISEQ,
271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
272 if ((ahc->features & AHC_CMD_CHAN) != 0) {
273 /* Ensure that no DMA operations are in progress */
274 ahc_outb(ahc, CCSCBCNT, 0);
275 ahc_outb(ahc, CCSGCTL, 0);
276 ahc_outb(ahc, CCSCBCTL, 0);
279 * If we were in the process of DMA'ing SCB data into
280 * an SCB, replace that SCB on the free list. This prevents
283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
284 ahc_add_curscb_to_free_list(ahc);
285 ahc_outb(ahc, SEQ_FLAGS2,
286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
290 * Clear any pending sequencer interrupt. It is no
291 * longer relevant since we're resetting the Program
294 ahc_outb(ahc, CLRINT, CLRSEQINT);
296 ahc_outb(ahc, MWI_RESIDUAL, 0);
297 ahc_outb(ahc, SEQCTL, ahc->seqctl);
298 ahc_outb(ahc, SEQADDR0, 0);
299 ahc_outb(ahc, SEQADDR1, 0);
304 /************************* Input/Output Queues ********************************/
306 ahc_run_qoutfifo(struct ahc_softc *ahc)
311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
314 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
315 if ((ahc->qoutfifonext & 0x03) == 0x03) {
319 * Clear 32bits of QOUTFIFO at a time
320 * so that we don't clobber an incoming
321 * byte DMA to the array on architectures
322 * that only support 32bit load and store
325 modnext = ahc->qoutfifonext & ~0x3;
326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
328 ahc->shared_data_dmamap,
329 /*offset*/modnext, /*len*/4,
330 BUS_DMASYNC_PREREAD);
334 scb = ahc_lookup_scb(ahc, scb_index);
336 printf("%s: WARNING no command for scb %d "
337 "(cmdcmplt)\nQOUTPOS = %d\n",
338 ahc_name(ahc), scb_index,
339 (ahc->qoutfifonext - 1) & 0xFF);
344 * Save off the residual
347 ahc_update_residual(ahc, scb);
353 ahc_run_untagged_queues(struct ahc_softc *ahc)
357 for (i = 0; i < 16; i++)
358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
366 if (ahc->untagged_queue_lock != 0)
369 if ((scb = TAILQ_FIRST(queue)) != NULL
370 && (scb->flags & SCB_ACTIVE) == 0) {
371 scb->flags |= SCB_ACTIVE;
372 ahc_queue_scb(ahc, scb);
376 /************************* Interrupt Handling *********************************/
378 ahc_handle_brkadrint(struct ahc_softc *ahc)
381 * We upset the sequencer :-(
382 * Lookup the error message
387 error = ahc_inb(ahc, ERROR);
388 for (i = 0; error != 1 && i < num_errors; i++)
390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
391 ahc_name(ahc), ahc_hard_errors[i].errmesg,
392 ahc_inb(ahc, SEQADDR0) |
393 (ahc_inb(ahc, SEQADDR1) << 8));
395 ahc_dump_card_state(ahc);
397 /* Tell everyone that this HBA is no longer available */
398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
402 /* Disable all interrupt sources by resetting the controller */
407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
410 struct ahc_devinfo devinfo;
412 ahc_fetch_devinfo(ahc, &devinfo);
415 * Clear the upper byte that holds SEQINT status
416 * codes and clear the SEQINT bit. We will unpause
417 * the sequencer, if appropriate, after servicing
420 ahc_outb(ahc, CLRINT, CLRSEQINT);
421 switch (intstat & SEQINT_MASK) {
425 struct hardware_scb *hscb;
428 * Set the default return value to 0 (don't
429 * send sense). The sense code will change
432 ahc_outb(ahc, RETURN_1, 0);
435 * The sequencer will notify us when a command
436 * has an error that would be of interest to
437 * the kernel. This allows us to leave the sequencer
438 * running in the common case of command completes
439 * without error. The sequencer will already have
440 * dma'd the SCB back up to us, so we can reference
441 * the in kernel copy directly.
443 scb_index = ahc_inb(ahc, SCB_TAG);
444 scb = ahc_lookup_scb(ahc, scb_index);
446 ahc_print_devinfo(ahc, &devinfo);
447 printf("ahc_intr - referenced scb "
448 "not valid during seqint 0x%x scb(%d)\n",
450 ahc_dump_card_state(ahc);
457 /* Don't want to clobber the original sense code */
458 if ((scb->flags & SCB_SENSE) != 0) {
460 * Clear the SCB_SENSE Flag and have
461 * the sequencer do a normal command
464 scb->flags &= ~SCB_SENSE;
465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
469 /* Freeze the queue until the client sees the error. */
470 ahc_freeze_devq(ahc, scb);
472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
473 switch (hscb->shared_data.status.scsi_status) {
475 printf("%s: Interrupted for staus of 0???\n",
478 case SCSI_STATUS_CMD_TERMINATED:
479 case SCSI_STATUS_CHECK_COND:
481 struct ahc_dma_seg *sg;
482 struct scsi_sense *sc;
483 struct ahc_initiator_tinfo *targ_info;
484 struct ahc_tmode_tstate *tstate;
485 struct ahc_transinfo *tinfo;
487 if (ahc_debug & AHC_SHOW_SENSE) {
488 ahc_print_path(ahc, scb);
489 printf("SCB %d: requests Check Status\n",
494 if (ahc_perform_autosense(scb) == 0)
497 targ_info = ahc_fetch_transinfo(ahc,
502 tinfo = &targ_info->curr;
504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
506 * Save off the residual if there is one.
508 ahc_update_residual(ahc, scb);
510 if (ahc_debug & AHC_SHOW_SENSE) {
511 ahc_print_path(ahc, scb);
512 printf("Sending Sense\n");
515 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
516 sg->len = ahc_get_sense_bufsize(ahc, scb);
517 sg->len |= AHC_DMA_LAST_SEG;
519 /* Fixup byte order */
520 sg->addr = ahc_htole32(sg->addr);
521 sg->len = ahc_htole32(sg->len);
523 sc->opcode = REQUEST_SENSE;
525 if (tinfo->protocol_version <= SCSI_REV_2
526 && SCB_GET_LUN(scb) < 8)
527 sc->byte2 = SCB_GET_LUN(scb) << 5;
530 sc->length = sg->len;
534 * We can't allow the target to disconnect.
535 * This will be an untagged transaction and
536 * having the target disconnect will make this
537 * transaction indestinguishable from outstanding
538 * tagged transactions.
543 * This request sense could be because the
544 * the device lost power or in some other
545 * way has lost our transfer negotiations.
546 * Renegotiate if appropriate. Unit attention
547 * errors will be reported before any data
550 if (ahc_get_residual(scb)
551 == ahc_get_transfer_length(scb)) {
552 ahc_update_neg_request(ahc, &devinfo,
554 AHC_NEG_IF_NON_ASYNC);
556 if (tstate->auto_negotiate & devinfo.target_mask) {
557 hscb->control |= MK_MESSAGE;
558 scb->flags &= ~SCB_NEGOTIATE;
559 scb->flags |= SCB_AUTO_NEGOTIATE;
561 hscb->cdb_len = sizeof(*sc);
562 hscb->dataptr = sg->addr;
563 hscb->datacnt = sg->len;
564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
565 hscb->sgptr = ahc_htole32(hscb->sgptr);
567 scb->flags |= SCB_SENSE;
568 ahc_qinfifo_requeue_tail(ahc, scb);
569 ahc_outb(ahc, RETURN_1, SEND_SENSE);
571 * Ensure we have enough time to actually
572 * retrieve the sense.
574 ahc_scb_timer_reset(scb, 5 * 1000000);
584 /* Ensure we don't leave the selection hardware on */
585 ahc_outb(ahc, SCSISEQ,
586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
588 printf("%s:%c:%d: no active SCB for reconnecting "
589 "target - issuing BUS DEVICE RESET\n",
590 ahc_name(ahc), devinfo.channel, devinfo.target);
591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
592 "ARG_1 == 0x%x ACCUM = 0x%x\n",
593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
598 ahc_index_busy_tcl(ahc,
599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
600 ahc_inb(ahc, SAVED_LUN))),
601 ahc_inb(ahc, SINDEX));
602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
606 ahc_inb(ahc, SCB_CONTROL));
607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
611 ahc_dump_card_state(ahc);
612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
614 ahc->msgout_index = 0;
615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
616 ahc_outb(ahc, MSG_OUT, HOST_MSG);
622 u_int rejbyte = ahc_inb(ahc, ACCUM);
623 printf("%s:%c:%d: Warning - unknown message received from "
624 "target (0x%x). Rejecting\n",
625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
628 case PROTO_VIOLATION:
630 ahc_handle_proto_violation(ahc);
634 ahc_handle_ign_wide_residue(ahc, &devinfo);
637 ahc_reinitialize_dataptrs(ahc);
643 lastphase = ahc_inb(ahc, LASTPHASE);
644 printf("%s:%c:%d: unknown scsi bus phase %x, "
645 "lastphase = 0x%x. Attempting to continue\n",
646 ahc_name(ahc), devinfo.channel, devinfo.target,
647 lastphase, ahc_inb(ahc, SCSISIGI));
654 lastphase = ahc_inb(ahc, LASTPHASE);
655 printf("%s:%c:%d: Missed busfree. "
656 "Lastphase = 0x%x, Curphase = 0x%x\n",
657 ahc_name(ahc), devinfo.channel, devinfo.target,
658 lastphase, ahc_inb(ahc, SCSISIGI));
665 * The sequencer has encountered a message phase
666 * that requires host assistance for completion.
667 * While handling the message phase(s), we will be
668 * notified by the sequencer after each byte is
669 * transfered so we can track bus phase changes.
671 * If this is the first time we've seen a HOST_MSG_LOOP
672 * interrupt, initialize the state of the host message
675 if (ahc->msg_type == MSG_TYPE_NONE) {
680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
681 if (bus_phase != P_MESGIN
682 && bus_phase != P_MESGOUT) {
683 printf("ahc_intr: HOST_MSG_LOOP bad "
687 * Probably transitioned to bus free before
688 * we got here. Just punt the message.
690 ahc_clear_intstat(ahc);
695 scb_index = ahc_inb(ahc, SCB_TAG);
696 scb = ahc_lookup_scb(ahc, scb_index);
697 if (devinfo.role == ROLE_INITIATOR) {
699 panic("HOST_MSG_LOOP with "
700 "invalid SCB %x\n", scb_index);
702 if (bus_phase == P_MESGOUT)
703 ahc_setup_initiator_msgout(ahc,
708 MSG_TYPE_INITIATOR_MSGIN;
709 ahc->msgin_index = 0;
712 #ifdef AHC_TARGET_MODE
714 if (bus_phase == P_MESGOUT) {
716 MSG_TYPE_TARGET_MSGOUT;
717 ahc->msgin_index = 0;
720 ahc_setup_target_msgin(ahc,
727 ahc_handle_message_phase(ahc);
733 * If we've cleared the parity error interrupt
734 * but the sequencer still believes that SCSIPERR
735 * is true, it must be that the parity error is
736 * for the currently presented byte on the bus,
737 * and we are not in a phase (data-in) where we will
738 * eventually ack this byte. Ack the byte and
739 * throw it away in the hope that the target will
740 * take us to message out to deliver the appropriate
743 if ((intstat & SCSIINT) == 0
744 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
746 if ((ahc->features & AHC_DT) == 0) {
750 * The hardware will only let you ack bytes
751 * if the expected phase in SCSISIGO matches
752 * the current phase. Make sure this is
753 * currently the case.
755 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
756 ahc_outb(ahc, LASTPHASE, curphase);
757 ahc_outb(ahc, SCSISIGO, curphase);
759 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
763 * In a data phase. Faster to bitbucket
764 * the data than to individually ack each
765 * byte. This is also the only strategy
766 * that will work with AUTOACK enabled.
768 ahc_outb(ahc, SXFRCTL1,
769 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
771 while (--wait != 0) {
772 if ((ahc_inb(ahc, SCSISIGI)
777 ahc_outb(ahc, SXFRCTL1,
778 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
783 ahc_print_devinfo(ahc, &devinfo);
784 printf("Unable to clear parity error. "
786 scb_index = ahc_inb(ahc, SCB_TAG);
787 scb = ahc_lookup_scb(ahc, scb_index);
789 ahc_set_transaction_status(scb,
791 ahc_reset_channel(ahc, devinfo.channel,
795 ahc_inb(ahc, SCSIDATL);
803 * When the sequencer detects an overrun, it
804 * places the controller in "BITBUCKET" mode
805 * and allows the target to complete its transfer.
806 * Unfortunately, none of the counters get updated
807 * when the controller is in this mode, so we have
808 * no way of knowing how large the overrun was.
810 u_int scbindex = ahc_inb(ahc, SCB_TAG);
811 u_int lastphase = ahc_inb(ahc, LASTPHASE);
814 scb = ahc_lookup_scb(ahc, scbindex);
815 for (i = 0; i < num_phases; i++) {
816 if (lastphase == ahc_phase_table[i].phase)
819 ahc_print_path(ahc, scb);
820 printf("data overrun detected %s."
822 ahc_phase_table[i].phasemsg,
824 ahc_print_path(ahc, scb);
825 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
826 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
827 ahc_get_transfer_length(scb), scb->sg_count);
828 if (scb->sg_count > 0) {
829 for (i = 0; i < scb->sg_count; i++) {
831 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
833 (ahc_le32toh(scb->sg_list[i].len) >> 24
834 & SG_HIGH_ADDR_BITS),
835 ahc_le32toh(scb->sg_list[i].addr),
836 ahc_le32toh(scb->sg_list[i].len)
841 * Set this and it will take effect when the
842 * target does a command complete.
844 ahc_freeze_devq(ahc, scb);
845 if ((scb->flags & SCB_SENSE) == 0) {
846 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
848 scb->flags &= ~SCB_SENSE;
849 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
853 if ((ahc->features & AHC_ULTRA2) != 0) {
855 * Clear the channel in case we return
856 * to data phase later.
858 ahc_outb(ahc, SXFRCTL0,
859 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
860 ahc_outb(ahc, SXFRCTL0,
861 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
863 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
866 /* Ensure HHADDR is 0 for future DMA operations. */
867 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
868 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
869 ahc_outb(ahc, HADDR, 0);
870 ahc_outb(ahc, DSCOMMAND1, dscommand1);
878 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
879 ahc_name(ahc), devinfo.channel, devinfo.target,
881 scbindex = ahc_inb(ahc, SCB_TAG);
882 scb = ahc_lookup_scb(ahc, scbindex);
884 && (scb->flags & SCB_RECOVERY_SCB) != 0)
886 * Ensure that we didn't put a second instance of this
887 * SCB into the QINFIFO.
889 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
890 SCB_GET_CHANNEL(ahc, scb),
891 SCB_GET_LUN(scb), scb->hscb->tag,
892 ROLE_INITIATOR, /*status*/0,
898 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
899 ahc_dump_card_state(ahc);
907 scbptr = ahc_inb(ahc, SCBPTR);
908 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
909 scbptr, ahc_inb(ahc, ARG_1),
910 ahc->scb_data->hscbs[scbptr].tag);
911 ahc_dump_card_state(ahc);
917 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
918 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
919 "ARG_1 == 0x%x ACCUM = 0x%x\n",
920 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
921 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
922 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
923 "SINDEX == 0x%x\n, A == 0x%x\n",
924 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
925 ahc_index_busy_tcl(ahc,
926 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
927 ahc_inb(ahc, SAVED_LUN))),
928 ahc_inb(ahc, SINDEX),
929 ahc_inb(ahc, ACCUM));
930 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
931 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
932 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
933 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
934 ahc_inb(ahc, SCB_CONTROL));
935 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
936 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
937 ahc_dump_card_state(ahc);
942 printf("ahc_intr: seqint, "
943 "intstat == 0x%x, scsisigi = 0x%x\n",
944 intstat, ahc_inb(ahc, SCSISIGI));
949 * The sequencer is paused immediately on
950 * a SEQINT, so we should restart it when
957 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
966 if ((ahc->features & AHC_TWIN) != 0
967 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
971 intr_channel = cur_channel;
973 if ((ahc->features & AHC_ULTRA2) != 0)
974 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
977 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
978 if (status == 0 && status0 == 0) {
979 if ((ahc->features & AHC_TWIN) != 0) {
980 /* Try the other channel */
981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982 status = ahc_inb(ahc, SSTAT1)
983 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
984 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
987 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
988 ahc_outb(ahc, CLRINT, CLRSCSIINT);
994 /* Make sure the sequencer is in a safe location. */
995 ahc_clear_critical_section(ahc);
997 scb_index = ahc_inb(ahc, SCB_TAG);
998 scb = ahc_lookup_scb(ahc, scb_index);
1000 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1003 if ((ahc->features & AHC_ULTRA2) != 0
1004 && (status0 & IOERR) != 0) {
1007 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1008 printf("%s: Transceiver State Has Changed to %s mode\n",
1009 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1010 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1012 * When transitioning to SE mode, the reset line
1013 * glitches, triggering an arbitration bug in some
1014 * Ultra2 controllers. This bug is cleared when we
1015 * assert the reset line. Since a reset glitch has
1016 * already occurred with this transition and a
1017 * transceiver state change is handled just like
1018 * a bus reset anyway, asserting the reset line
1019 * ourselves is safe.
1021 ahc_reset_channel(ahc, intr_channel,
1022 /*Initiate Reset*/now_lvd == 0);
1023 } else if ((status & SCSIRSTI) != 0) {
1024 printf("%s: Someone reset channel %c\n",
1025 ahc_name(ahc), intr_channel);
1026 if (intr_channel != cur_channel)
1027 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1028 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1029 } else if ((status & SCSIPERR) != 0) {
1031 * Determine the bus phase and queue an appropriate message.
1032 * SCSIPERR is latched true as soon as a parity error
1033 * occurs. If the sequencer acked the transfer that
1034 * caused the parity error and the currently presented
1035 * transfer on the bus has correct parity, SCSIPERR will
1036 * be cleared by CLRSCSIPERR. Use this to determine if
1037 * we should look at the last phase the sequencer recorded,
1038 * or the current phase presented on the bus.
1040 struct ahc_devinfo devinfo;
1050 lastphase = ahc_inb(ahc, LASTPHASE);
1051 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1052 sstat2 = ahc_inb(ahc, SSTAT2);
1053 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1055 * For all phases save DATA, the sequencer won't
1056 * automatically ack a byte that has a parity error
1057 * in it. So the only way that the current phase
1058 * could be 'data-in' is if the parity error is for
1059 * an already acked byte in the data phase. During
1060 * synchronous data-in transfers, we may actually
1061 * ack bytes before latching the current phase in
1062 * LASTPHASE, leading to the discrepancy between
1063 * curphase and lastphase.
1065 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1066 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1067 errorphase = curphase;
1069 errorphase = lastphase;
1071 for (i = 0; i < num_phases; i++) {
1072 if (errorphase == ahc_phase_table[i].phase)
1075 mesg_out = ahc_phase_table[i].mesg_out;
1078 if (SCB_IS_SILENT(scb))
1081 ahc_print_path(ahc, scb);
1082 scb->flags |= SCB_TRANSMISSION_ERROR;
1084 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1085 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1086 scsirate = ahc_inb(ahc, SCSIRATE);
1087 if (silent == FALSE) {
1088 printf("parity error detected %s. "
1089 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1090 ahc_phase_table[i].phasemsg,
1091 ahc_inw(ahc, SEQADDR0),
1093 if ((ahc->features & AHC_DT) != 0) {
1094 if ((sstat2 & CRCVALERR) != 0)
1095 printf("\tCRC Value Mismatch\n");
1096 if ((sstat2 & CRCENDERR) != 0)
1097 printf("\tNo terminal CRC packet "
1099 if ((sstat2 & CRCREQERR) != 0)
1100 printf("\tIllegal CRC packet "
1102 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1103 printf("\tUnexpected %sDT Data Phase\n",
1104 (scsirate & SINGLE_EDGE)
1109 if ((ahc->features & AHC_DT) != 0
1110 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1112 * This error applies regardless of
1113 * data direction, so ignore the value
1114 * in the phase table.
1116 mesg_out = MSG_INITIATOR_DET_ERR;
1120 * We've set the hardware to assert ATN if we
1121 * get a parity error on "in" phases, so all we
1122 * need to do is stuff the message buffer with
1123 * the appropriate message. "In" phases have set
1124 * mesg_out to something other than MSG_NOP.
1126 if (mesg_out != MSG_NOOP) {
1127 if (ahc->msg_type != MSG_TYPE_NONE)
1128 ahc->send_msg_perror = TRUE;
1130 ahc_outb(ahc, MSG_OUT, mesg_out);
1133 * Force a renegotiation with this target just in
1134 * case we are out of sync for some external reason
1135 * unknown (or unreported) by the target.
1137 ahc_fetch_devinfo(ahc, &devinfo);
1138 ahc_force_renegotiation(ahc, &devinfo);
1140 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1142 } else if ((status & SELTO) != 0) {
1145 /* Stop the selection */
1146 ahc_outb(ahc, SCSISEQ, 0);
1148 /* No more pending messages */
1149 ahc_clear_msg_state(ahc);
1151 /* Clear interrupt state */
1152 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1153 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1156 * Although the driver does not care about the
1157 * 'Selection in Progress' status bit, the busy
1158 * LED does. SELINGO is only cleared by a sucessfull
1159 * selection, so we must manually clear it to insure
1160 * the LED turns off just incase no future successful
1161 * selections occur (e.g. no devices on the bus).
1163 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1165 scbptr = ahc_inb(ahc, WAITING_SCBH);
1166 ahc_outb(ahc, SCBPTR, scbptr);
1167 scb_index = ahc_inb(ahc, SCB_TAG);
1169 scb = ahc_lookup_scb(ahc, scb_index);
1171 printf("%s: ahc_intr - referenced scb not "
1172 "valid during SELTO scb(%d, %d)\n",
1173 ahc_name(ahc), scbptr, scb_index);
1174 ahc_dump_card_state(ahc);
1176 struct ahc_devinfo devinfo;
1178 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1179 ahc_print_path(ahc, scb);
1180 printf("Saw Selection Timeout for SCB 0x%x\n",
1184 ahc_scb_devinfo(ahc, &devinfo, scb);
1185 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1186 ahc_freeze_devq(ahc, scb);
1189 * Cancel any pending transactions on the device
1190 * now that it seems to be missing. This will
1191 * also revert us to async/narrow transfers until
1192 * we can renegotiate with the device.
1194 ahc_handle_devreset(ahc, &devinfo,
1196 "Selection Timeout",
1197 /*verbose_level*/1);
1199 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1201 } else if ((status & BUSFREE) != 0
1202 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1203 struct ahc_devinfo devinfo;
1208 u_int initiator_role_id;
1213 * Clear our selection hardware as soon as possible.
1214 * We may have an entry in the waiting Q for this target,
1215 * that is affected by this busfree and we don't want to
1216 * go about selecting the target while we handle the event.
1218 ahc_outb(ahc, SCSISEQ,
1219 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1222 * Disable busfree interrupts and clear the busfree
1223 * interrupt status. We do this here so that several
1224 * bus transactions occur prior to clearing the SCSIINT
1225 * latch. It can take a bit for the clearing to take effect.
1227 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1228 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1231 * Look at what phase we were last in.
1232 * If its message out, chances are pretty good
1233 * that the busfree was in response to one of
1234 * our abort requests.
1236 lastphase = ahc_inb(ahc, LASTPHASE);
1237 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1238 saved_lun = ahc_inb(ahc, SAVED_LUN);
1239 target = SCSIID_TARGET(ahc, saved_scsiid);
1240 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1241 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1242 ahc_compile_devinfo(&devinfo, initiator_role_id,
1243 target, saved_lun, channel, ROLE_INITIATOR);
1246 if (lastphase == P_MESGOUT) {
1249 tag = SCB_LIST_NULL;
1250 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1251 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1252 if (ahc->msgout_buf[ahc->msgout_index - 1]
1254 tag = scb->hscb->tag;
1255 ahc_print_path(ahc, scb);
1256 printf("SCB %d - Abort%s Completed.\n",
1257 scb->hscb->tag, tag == SCB_LIST_NULL ?
1259 ahc_abort_scbs(ahc, target, channel,
1264 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1265 MSG_BUS_DEV_RESET, TRUE)) {
1268 * Don't mark the user's request for this BDR
1269 * as completing with CAM_BDR_SENT. CAM3
1270 * specifies CAM_REQ_CMP.
1273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1274 && ahc_match_scb(ahc, scb, target, channel,
1278 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1281 ahc_compile_devinfo(&devinfo,
1287 ahc_handle_devreset(ahc, &devinfo,
1290 /*verbose_level*/0);
1292 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1293 MSG_EXT_PPR, FALSE)) {
1294 struct ahc_initiator_tinfo *tinfo;
1295 struct ahc_tmode_tstate *tstate;
1298 * PPR Rejected. Try non-ppr negotiation
1299 * and retry command.
1301 tinfo = ahc_fetch_transinfo(ahc,
1306 tinfo->curr.transport_version = 2;
1307 tinfo->goal.transport_version = 2;
1308 tinfo->goal.ppr_options = 0;
1309 ahc_qinfifo_requeue_tail(ahc, scb);
1311 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1312 MSG_EXT_WDTR, FALSE)) {
1314 * Negotiation Rejected. Go-narrow and
1317 ahc_set_width(ahc, &devinfo,
1318 MSG_EXT_WDTR_BUS_8_BIT,
1319 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1321 ahc_qinfifo_requeue_tail(ahc, scb);
1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324 MSG_EXT_SDTR, FALSE)) {
1326 * Negotiation Rejected. Go-async and
1329 ahc_set_syncrate(ahc, &devinfo,
1331 /*period*/0, /*offset*/0,
1333 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1335 ahc_qinfifo_requeue_tail(ahc, scb);
1339 if (printerror != 0) {
1345 if ((scb->hscb->control & TAG_ENB) != 0)
1346 tag = scb->hscb->tag;
1348 tag = SCB_LIST_NULL;
1349 ahc_print_path(ahc, scb);
1350 ahc_abort_scbs(ahc, target, channel,
1351 SCB_GET_LUN(scb), tag,
1356 * We had not fully identified this connection,
1357 * so we cannot abort anything.
1359 printf("%s: ", ahc_name(ahc));
1361 for (i = 0; i < num_phases; i++) {
1362 if (lastphase == ahc_phase_table[i].phase)
1365 if (lastphase != P_BUSFREE) {
1367 * Renegotiate with this device at the
1368 * next oportunity just in case this busfree
1369 * is due to a negotiation mismatch with the
1372 ahc_force_renegotiation(ahc, &devinfo);
1374 printf("Unexpected busfree %s\n"
1375 "SEQADDR == 0x%x\n",
1376 ahc_phase_table[i].phasemsg,
1377 ahc_inb(ahc, SEQADDR0)
1378 | (ahc_inb(ahc, SEQADDR1) << 8));
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1383 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1384 ahc_name(ahc), status);
1385 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1390 * Force renegotiation to occur the next time we initiate
1391 * a command to the current device.
1394 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1396 struct ahc_initiator_tinfo *targ_info;
1397 struct ahc_tmode_tstate *tstate;
1399 targ_info = ahc_fetch_transinfo(ahc,
1401 devinfo->our_scsiid,
1404 ahc_update_neg_request(ahc, devinfo, tstate,
1405 targ_info, AHC_NEG_IF_NON_ASYNC);
1408 #define AHC_MAX_STEPS 2000
1410 ahc_clear_critical_section(struct ahc_softc *ahc)
1417 if (ahc->num_critical_sections == 0)
1429 seqaddr = ahc_inb(ahc, SEQADDR0)
1430 | (ahc_inb(ahc, SEQADDR1) << 8);
1433 * Seqaddr represents the next instruction to execute,
1434 * so we are really executing the instruction just
1439 cs = ahc->critical_sections;
1440 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1442 if (cs->begin < seqaddr && cs->end >= seqaddr)
1446 if (i == ahc->num_critical_sections)
1449 if (steps > AHC_MAX_STEPS) {
1450 printf("%s: Infinite loop in critical section\n",
1452 ahc_dump_card_state(ahc);
1453 panic("critical section loop");
1457 if (stepping == FALSE) {
1460 * Disable all interrupt sources so that the
1461 * sequencer will not be stuck by a pausing
1462 * interrupt condition while we attempt to
1463 * leave a critical section.
1465 simode0 = ahc_inb(ahc, SIMODE0);
1466 ahc_outb(ahc, SIMODE0, 0);
1467 simode1 = ahc_inb(ahc, SIMODE1);
1468 if ((ahc->features & AHC_DT) != 0)
1470 * On DT class controllers, we
1471 * use the enhanced busfree logic.
1472 * Unfortunately we cannot re-enable
1473 * busfree detection within the
1474 * current connection, so we must
1475 * leave it on while single stepping.
1477 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1479 ahc_outb(ahc, SIMODE1, 0);
1480 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1481 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1484 if ((ahc->features & AHC_DT) != 0) {
1485 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1486 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1488 ahc_outb(ahc, HCNTRL, ahc->unpause);
1489 while (!ahc_is_paused(ahc))
1493 ahc_outb(ahc, SIMODE0, simode0);
1494 ahc_outb(ahc, SIMODE1, simode1);
1495 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1500 * Clear any pending interrupt status.
1503 ahc_clear_intstat(struct ahc_softc *ahc)
1505 /* Clear any interrupt conditions this may have caused */
1506 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1507 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1509 ahc_flush_device_writes(ahc);
1510 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1511 ahc_flush_device_writes(ahc);
1512 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1513 ahc_flush_device_writes(ahc);
1516 /**************************** Debugging Routines ******************************/
1518 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1522 ahc_print_scb(struct scb *scb)
1526 struct hardware_scb *hscb = scb->hscb;
1528 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1534 printf("Shared Data: ");
1535 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1536 printf("%#02x", hscb->shared_data.cdb[i]);
1537 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1538 ahc_le32toh(hscb->dataptr),
1539 ahc_le32toh(hscb->datacnt),
1540 ahc_le32toh(hscb->sgptr),
1542 if (scb->sg_count > 0) {
1543 for (i = 0; i < scb->sg_count; i++) {
1544 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1546 (ahc_le32toh(scb->sg_list[i].len) >> 24
1547 & SG_HIGH_ADDR_BITS),
1548 ahc_le32toh(scb->sg_list[i].addr),
1549 ahc_le32toh(scb->sg_list[i].len));
1554 /************************* Transfer Negotiation *******************************/
1556 * Allocate per target mode instance (ID we respond to as a target)
1557 * transfer negotiation data structures.
1559 static struct ahc_tmode_tstate *
1560 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1562 struct ahc_tmode_tstate *master_tstate;
1563 struct ahc_tmode_tstate *tstate;
1566 master_tstate = ahc->enabled_targets[ahc->our_id];
1567 if (channel == 'B') {
1569 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1571 if (ahc->enabled_targets[scsi_id] != NULL
1572 && ahc->enabled_targets[scsi_id] != master_tstate)
1573 panic("%s: ahc_alloc_tstate - Target already allocated",
1575 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1576 M_DEVBUF, M_NOWAIT);
1581 * If we have allocated a master tstate, copy user settings from
1582 * the master tstate (taken from SRAM or the EEPROM) for this
1583 * channel, but reset our current and goal settings to async/narrow
1584 * until an initiator talks to us.
1586 if (master_tstate != NULL) {
1587 memcpy(tstate, master_tstate, sizeof(*tstate));
1588 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1589 tstate->ultraenb = 0;
1590 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1591 memset(&tstate->transinfo[i].curr, 0,
1592 sizeof(tstate->transinfo[i].curr));
1593 memset(&tstate->transinfo[i].goal, 0,
1594 sizeof(tstate->transinfo[i].goal));
1597 memset(tstate, 0, sizeof(*tstate));
1598 ahc->enabled_targets[scsi_id] = tstate;
1602 #ifdef AHC_TARGET_MODE
1604 * Free per target mode instance (ID we respond to as a target)
1605 * transfer negotiation data structures.
1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1610 struct ahc_tmode_tstate *tstate;
1613 * Don't clean up our "master" tstate.
1614 * It has our default user settings.
1616 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1617 || (channel == 'A' && scsi_id == ahc->our_id))
1623 tstate = ahc->enabled_targets[scsi_id];
1625 free(tstate, M_DEVBUF);
1626 ahc->enabled_targets[scsi_id] = NULL;
1631 * Called when we have an active connection to a target on the bus,
1632 * this function finds the nearest syncrate to the input period limited
1633 * by the capabilities of the bus connectivity of and sync settings for
1636 struct ahc_syncrate *
1637 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1638 struct ahc_initiator_tinfo *tinfo,
1639 u_int *period, u_int *ppr_options, role_t role)
1641 struct ahc_transinfo *transinfo;
1644 if ((ahc->features & AHC_ULTRA2) != 0) {
1645 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1646 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1647 maxsync = AHC_SYNCRATE_DT;
1649 maxsync = AHC_SYNCRATE_ULTRA;
1650 /* Can't do DT on an SE bus */
1651 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1653 } else if ((ahc->features & AHC_ULTRA) != 0) {
1654 maxsync = AHC_SYNCRATE_ULTRA;
1656 maxsync = AHC_SYNCRATE_FAST;
1659 * Never allow a value higher than our current goal
1660 * period otherwise we may allow a target initiated
1661 * negotiation to go above the limit as set by the
1662 * user. In the case of an initiator initiated
1663 * sync negotiation, we limit based on the user
1664 * setting. This allows the system to still accept
1665 * incoming negotiations even if target initiated
1666 * negotiation is not performed.
1668 if (role == ROLE_TARGET)
1669 transinfo = &tinfo->user;
1671 transinfo = &tinfo->goal;
1672 *ppr_options &= transinfo->ppr_options;
1673 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1674 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
1675 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1677 if (transinfo->period == 0) {
1682 *period = max(*period, (u_int)transinfo->period);
1683 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1687 * Look up the valid period to SCSIRATE conversion in our table.
1688 * Return the period and offset that should be sent to the target
1689 * if this was the beginning of an SDTR.
1691 struct ahc_syncrate *
1692 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1693 u_int *ppr_options, u_int maxsync)
1695 struct ahc_syncrate *syncrate;
1697 if ((ahc->features & AHC_DT) == 0)
1698 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1700 /* Skip all DT only entries if DT is not available */
1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1702 && maxsync < AHC_SYNCRATE_ULTRA2)
1703 maxsync = AHC_SYNCRATE_ULTRA2;
1705 /* Now set the maxsync based on the card capabilities
1706 * DT is already done above */
1707 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1708 && maxsync < AHC_SYNCRATE_ULTRA)
1709 maxsync = AHC_SYNCRATE_ULTRA;
1710 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1711 && maxsync < AHC_SYNCRATE_FAST)
1712 maxsync = AHC_SYNCRATE_FAST;
1714 for (syncrate = &ahc_syncrates[maxsync];
1715 syncrate->rate != NULL;
1719 * The Ultra2 table doesn't go as low
1720 * as for the Fast/Ultra cards.
1722 if ((ahc->features & AHC_ULTRA2) != 0
1723 && (syncrate->sxfr_u2 == 0))
1726 if (*period <= syncrate->period) {
1728 * When responding to a target that requests
1729 * sync, the requested rate may fall between
1730 * two rates that we can output, but still be
1731 * a rate that we can receive. Because of this,
1732 * we want to respond to the target with
1733 * the same rate that it sent to us even
1734 * if the period we use to send data to it
1735 * is lower. Only lower the response period
1738 if (syncrate == &ahc_syncrates[maxsync])
1739 *period = syncrate->period;
1742 * At some speeds, we only support
1745 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1746 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1752 || (syncrate->rate == NULL)
1753 || ((ahc->features & AHC_ULTRA2) != 0
1754 && (syncrate->sxfr_u2 == 0))) {
1755 /* Use asynchronous transfers. */
1758 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1764 * Convert from an entry in our syncrate table to the SCSI equivalent
1765 * sync "period" factor.
1768 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1770 struct ahc_syncrate *syncrate;
1772 if ((ahc->features & AHC_ULTRA2) != 0)
1773 scsirate &= SXFR_ULTRA2;
1777 /* now set maxsync based on card capabilities */
1778 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
1779 maxsync = AHC_SYNCRATE_ULTRA2;
1780 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1781 && maxsync < AHC_SYNCRATE_ULTRA)
1782 maxsync = AHC_SYNCRATE_ULTRA;
1783 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1784 && maxsync < AHC_SYNCRATE_FAST)
1785 maxsync = AHC_SYNCRATE_FAST;
1788 syncrate = &ahc_syncrates[maxsync];
1789 while (syncrate->rate != NULL) {
1791 if ((ahc->features & AHC_ULTRA2) != 0) {
1792 if (syncrate->sxfr_u2 == 0)
1794 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1795 return (syncrate->period);
1796 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1797 return (syncrate->period);
1801 return (0); /* async */
1805 * Truncate the given synchronous offset to a value the
1806 * current adapter type and syncrate are capable of.
1809 ahc_validate_offset(struct ahc_softc *ahc,
1810 struct ahc_initiator_tinfo *tinfo,
1811 struct ahc_syncrate *syncrate,
1812 u_int *offset, int wide, role_t role)
1816 /* Limit offset to what we can do */
1817 if (syncrate == NULL) {
1819 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1820 maxoffset = MAX_OFFSET_ULTRA2;
1823 maxoffset = MAX_OFFSET_16BIT;
1825 maxoffset = MAX_OFFSET_8BIT;
1827 *offset = min(*offset, maxoffset);
1828 if (tinfo != NULL) {
1829 if (role == ROLE_TARGET)
1830 *offset = min(*offset, (u_int)tinfo->user.offset);
1832 *offset = min(*offset, (u_int)tinfo->goal.offset);
1837 * Truncate the given transfer width parameter to a value the
1838 * current adapter type is capable of.
1841 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1842 u_int *bus_width, role_t role)
1844 switch (*bus_width) {
1846 if (ahc->features & AHC_WIDE) {
1848 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1852 case MSG_EXT_WDTR_BUS_8_BIT:
1853 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1856 if (tinfo != NULL) {
1857 if (role == ROLE_TARGET)
1858 *bus_width = min((u_int)tinfo->user.width, *bus_width);
1860 *bus_width = min((u_int)tinfo->goal.width, *bus_width);
1865 * Update the bitmask of targets for which the controller should
1866 * negotiate with at the next convenient oportunity. This currently
1867 * means the next time we send the initial identify messages for
1868 * a new transaction.
1871 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1872 struct ahc_tmode_tstate *tstate,
1873 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1875 u_int auto_negotiate_orig;
1877 auto_negotiate_orig = tstate->auto_negotiate;
1878 if (neg_type == AHC_NEG_ALWAYS) {
1880 * Force our "current" settings to be
1881 * unknown so that unless a bus reset
1882 * occurs the need to renegotiate is
1883 * recorded persistently.
1885 if ((ahc->features & AHC_WIDE) != 0)
1886 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1887 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1888 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1890 if (tinfo->curr.period != tinfo->goal.period
1891 || tinfo->curr.width != tinfo->goal.width
1892 || tinfo->curr.offset != tinfo->goal.offset
1893 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1894 || (neg_type == AHC_NEG_IF_NON_ASYNC
1895 && (tinfo->goal.offset != 0
1896 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1897 || tinfo->goal.ppr_options != 0)))
1898 tstate->auto_negotiate |= devinfo->target_mask;
1900 tstate->auto_negotiate &= ~devinfo->target_mask;
1902 return (auto_negotiate_orig != tstate->auto_negotiate);
1906 * Update the user/goal/curr tables of synchronous negotiation
1907 * parameters as well as, in the case of a current or active update,
1908 * any data structures on the host controller. In the case of an
1909 * active update, the specified target is currently talking to us on
1910 * the bus, so the transfer parameter update must take effect
1914 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1915 struct ahc_syncrate *syncrate, u_int period,
1916 u_int offset, u_int ppr_options, u_int type, int paused)
1918 struct ahc_initiator_tinfo *tinfo;
1919 struct ahc_tmode_tstate *tstate;
1926 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1929 if (syncrate == NULL) {
1934 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1935 devinfo->target, &tstate);
1937 if ((type & AHC_TRANS_USER) != 0) {
1938 tinfo->user.period = period;
1939 tinfo->user.offset = offset;
1940 tinfo->user.ppr_options = ppr_options;
1943 if ((type & AHC_TRANS_GOAL) != 0) {
1944 tinfo->goal.period = period;
1945 tinfo->goal.offset = offset;
1946 tinfo->goal.ppr_options = ppr_options;
1949 old_period = tinfo->curr.period;
1950 old_offset = tinfo->curr.offset;
1951 old_ppr = tinfo->curr.ppr_options;
1953 if ((type & AHC_TRANS_CUR) != 0
1954 && (old_period != period
1955 || old_offset != offset
1956 || old_ppr != ppr_options)) {
1960 scsirate = tinfo->scsirate;
1961 if ((ahc->features & AHC_ULTRA2) != 0) {
1963 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1964 if (syncrate != NULL) {
1965 scsirate |= syncrate->sxfr_u2;
1966 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1967 scsirate |= ENABLE_CRC;
1969 scsirate |= SINGLE_EDGE;
1973 scsirate &= ~(SXFR|SOFS);
1975 * Ensure Ultra mode is set properly for
1978 tstate->ultraenb &= ~devinfo->target_mask;
1979 if (syncrate != NULL) {
1980 if (syncrate->sxfr & ULTRA_SXFR) {
1982 devinfo->target_mask;
1984 scsirate |= syncrate->sxfr & SXFR;
1985 scsirate |= offset & SOFS;
1990 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1991 sxfrctl0 &= ~FAST20;
1992 if (tstate->ultraenb & devinfo->target_mask)
1994 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1998 ahc_outb(ahc, SCSIRATE, scsirate);
1999 if ((ahc->features & AHC_ULTRA2) != 0)
2000 ahc_outb(ahc, SCSIOFFSET, offset);
2003 tinfo->scsirate = scsirate;
2004 tinfo->curr.period = period;
2005 tinfo->curr.offset = offset;
2006 tinfo->curr.ppr_options = ppr_options;
2008 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2009 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2012 printf("%s: target %d synchronous at %sMHz%s, "
2013 "offset = 0x%x\n", ahc_name(ahc),
2014 devinfo->target, syncrate->rate,
2015 (ppr_options & MSG_EXT_PPR_DT_REQ)
2016 ? " DT" : "", offset);
2018 printf("%s: target %d using "
2019 "asynchronous transfers\n",
2020 ahc_name(ahc), devinfo->target);
2025 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2026 tinfo, AHC_NEG_TO_GOAL);
2029 ahc_update_pending_scbs(ahc);
2033 * Update the user/goal/curr tables of wide negotiation
2034 * parameters as well as, in the case of a current or active update,
2035 * any data structures on the host controller. In the case of an
2036 * active update, the specified target is currently talking to us on
2037 * the bus, so the transfer parameter update must take effect
2041 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2042 u_int width, u_int type, int paused)
2044 struct ahc_initiator_tinfo *tinfo;
2045 struct ahc_tmode_tstate *tstate;
2050 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2052 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2053 devinfo->target, &tstate);
2055 if ((type & AHC_TRANS_USER) != 0)
2056 tinfo->user.width = width;
2058 if ((type & AHC_TRANS_GOAL) != 0)
2059 tinfo->goal.width = width;
2061 oldwidth = tinfo->curr.width;
2062 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2066 scsirate = tinfo->scsirate;
2067 scsirate &= ~WIDEXFER;
2068 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2069 scsirate |= WIDEXFER;
2071 tinfo->scsirate = scsirate;
2074 ahc_outb(ahc, SCSIRATE, scsirate);
2076 tinfo->curr.width = width;
2078 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2079 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2081 printf("%s: target %d using %dbit transfers\n",
2082 ahc_name(ahc), devinfo->target,
2083 8 * (0x01 << width));
2087 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2088 tinfo, AHC_NEG_TO_GOAL);
2090 ahc_update_pending_scbs(ahc);
2094 * Update the current state of tagged queuing for a given target.
2097 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2098 struct ahc_devinfo *devinfo, ahc_queue_alg alg)
2100 struct scsi_device *sdev = cmd->device;
2102 ahc_platform_set_tags(ahc, sdev, devinfo, alg);
2103 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2104 devinfo->lun, AC_TRANSFER_NEG);
2108 * When the transfer settings for a connection change, update any
2109 * in-transit SCBs to contain the new data so the hardware will
2110 * be set correctly during future (re)selections.
2113 ahc_update_pending_scbs(struct ahc_softc *ahc)
2115 struct scb *pending_scb;
2116 int pending_scb_count;
2122 * Traverse the pending SCB list and ensure that all of the
2123 * SCBs there have the proper settings.
2125 pending_scb_count = 0;
2126 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2127 struct ahc_devinfo devinfo;
2128 struct hardware_scb *pending_hscb;
2129 struct ahc_initiator_tinfo *tinfo;
2130 struct ahc_tmode_tstate *tstate;
2132 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2133 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2135 devinfo.target, &tstate);
2136 pending_hscb = pending_scb->hscb;
2137 pending_hscb->control &= ~ULTRAENB;
2138 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2139 pending_hscb->control |= ULTRAENB;
2140 pending_hscb->scsirate = tinfo->scsirate;
2141 pending_hscb->scsioffset = tinfo->curr.offset;
2142 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2143 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2144 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2145 pending_hscb->control &= ~MK_MESSAGE;
2147 ahc_sync_scb(ahc, pending_scb,
2148 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2149 pending_scb_count++;
2152 if (pending_scb_count == 0)
2155 if (ahc_is_paused(ahc)) {
2162 saved_scbptr = ahc_inb(ahc, SCBPTR);
2163 /* Ensure that the hscbs down on the card match the new information */
2164 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2165 struct hardware_scb *pending_hscb;
2169 ahc_outb(ahc, SCBPTR, i);
2170 scb_tag = ahc_inb(ahc, SCB_TAG);
2171 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2172 if (pending_scb == NULL)
2175 pending_hscb = pending_scb->hscb;
2176 control = ahc_inb(ahc, SCB_CONTROL);
2177 control &= ~(ULTRAENB|MK_MESSAGE);
2178 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2179 ahc_outb(ahc, SCB_CONTROL, control);
2180 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2181 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2183 ahc_outb(ahc, SCBPTR, saved_scbptr);
2189 /**************************** Pathing Information *****************************/
2191 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2197 if (ahc_inb(ahc, SSTAT0) & TARGET)
2200 role = ROLE_INITIATOR;
2202 if (role == ROLE_TARGET
2203 && (ahc->features & AHC_MULTI_TID) != 0
2204 && (ahc_inb(ahc, SEQ_FLAGS)
2205 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2206 /* We were selected, so pull our id from TARGIDIN */
2207 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2208 } else if ((ahc->features & AHC_ULTRA2) != 0)
2209 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2211 our_id = ahc_inb(ahc, SCSIID) & OID;
2213 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2214 ahc_compile_devinfo(devinfo,
2216 SCSIID_TARGET(ahc, saved_scsiid),
2217 ahc_inb(ahc, SAVED_LUN),
2218 SCSIID_CHANNEL(ahc, saved_scsiid),
2222 struct ahc_phase_table_entry*
2223 ahc_lookup_phase_entry(int phase)
2225 struct ahc_phase_table_entry *entry;
2226 struct ahc_phase_table_entry *last_entry;
2229 * num_phases doesn't include the default entry which
2230 * will be returned if the phase doesn't match.
2232 last_entry = &ahc_phase_table[num_phases];
2233 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2234 if (phase == entry->phase)
2241 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2242 u_int lun, char channel, role_t role)
2244 devinfo->our_scsiid = our_id;
2245 devinfo->target = target;
2247 devinfo->target_offset = target;
2248 devinfo->channel = channel;
2249 devinfo->role = role;
2251 devinfo->target_offset += 8;
2252 devinfo->target_mask = (0x01 << devinfo->target_offset);
2256 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2258 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2259 devinfo->target, devinfo->lun);
2263 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2269 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2270 role = ROLE_INITIATOR;
2271 if ((scb->flags & SCB_TARGET_SCB) != 0)
2273 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2274 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2278 /************************ Message Phase Processing ****************************/
2280 ahc_assert_atn(struct ahc_softc *ahc)
2285 if ((ahc->features & AHC_DT) == 0)
2286 scsisigo |= ahc_inb(ahc, SCSISIGI);
2287 ahc_outb(ahc, SCSISIGO, scsisigo);
2291 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2292 * or enters the initial message out phase, we are interrupted. Fill our
2293 * outgoing message buffer with the appropriate message and beging handing
2294 * the message phase(s) manually.
2297 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2301 * To facilitate adding multiple messages together,
2302 * each routine should increment the index and len
2303 * variables instead of setting them explicitly.
2305 ahc->msgout_index = 0;
2306 ahc->msgout_len = 0;
2308 if ((scb->flags & SCB_DEVICE_RESET) == 0
2309 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2312 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2313 if ((scb->hscb->control & DISCENB) != 0)
2314 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2315 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2318 if ((scb->hscb->control & TAG_ENB) != 0) {
2319 ahc->msgout_buf[ahc->msgout_index++] =
2320 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2321 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2322 ahc->msgout_len += 2;
2326 if (scb->flags & SCB_DEVICE_RESET) {
2327 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2329 ahc_print_path(ahc, scb);
2330 printf("Bus Device Reset Message Sent\n");
2332 * Clear our selection hardware in advance of
2333 * the busfree. We may have an entry in the waiting
2334 * Q for this target, and we don't want to go about
2335 * selecting while we handle the busfree and blow it
2338 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2339 } else if ((scb->flags & SCB_ABORT) != 0) {
2340 if ((scb->hscb->control & TAG_ENB) != 0)
2341 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2343 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2345 ahc_print_path(ahc, scb);
2346 printf("Abort%s Message Sent\n",
2347 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2349 * Clear our selection hardware in advance of
2350 * the busfree. We may have an entry in the waiting
2351 * Q for this target, and we don't want to go about
2352 * selecting while we handle the busfree and blow it
2355 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2356 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2357 ahc_build_transfer_msg(ahc, devinfo);
2359 printf("ahc_intr: AWAITING_MSG for an SCB that "
2360 "does not have a waiting message\n");
2361 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2362 devinfo->target_mask);
2363 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2364 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2365 ahc_inb(ahc, MSG_OUT), scb->flags);
2369 * Clear the MK_MESSAGE flag from the SCB so we aren't
2370 * asked to send this message again.
2372 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2373 scb->hscb->control &= ~MK_MESSAGE;
2374 ahc->msgout_index = 0;
2375 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2379 * Build an appropriate transfer negotiation message for the
2380 * currently active target.
2383 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2386 * We need to initiate transfer negotiations.
2387 * If our current and goal settings are identical,
2388 * we want to renegotiate due to a check condition.
2390 struct ahc_initiator_tinfo *tinfo;
2391 struct ahc_tmode_tstate *tstate;
2392 struct ahc_syncrate *rate;
2400 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2401 devinfo->target, &tstate);
2403 * Filter our period based on the current connection.
2404 * If we can't perform DT transfers on this segment (not in LVD
2405 * mode for instance), then our decision to issue a PPR message
2408 period = tinfo->goal.period;
2409 offset = tinfo->goal.offset;
2410 ppr_options = tinfo->goal.ppr_options;
2411 /* Target initiated PPR is not allowed in the SCSI spec */
2412 if (devinfo->role == ROLE_TARGET)
2414 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2415 &ppr_options, devinfo->role);
2416 dowide = tinfo->curr.width != tinfo->goal.width;
2417 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2419 * Only use PPR if we have options that need it, even if the device
2420 * claims to support it. There might be an expander in the way
2423 doppr = ppr_options != 0;
2425 if (!dowide && !dosync && !doppr) {
2426 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2427 dosync = tinfo->goal.offset != 0;
2430 if (!dowide && !dosync && !doppr) {
2432 * Force async with a WDTR message if we have a wide bus,
2433 * or just issue an SDTR with a 0 offset.
2435 if ((ahc->features & AHC_WIDE) != 0)
2441 ahc_print_devinfo(ahc, devinfo);
2442 printf("Ensuring async\n");
2446 /* Target initiated PPR is not allowed in the SCSI spec */
2447 if (devinfo->role == ROLE_TARGET)
2451 * Both the PPR message and SDTR message require the
2452 * goal syncrate to be limited to what the target device
2453 * is capable of handling (based on whether an LVD->SE
2454 * expander is on the bus), so combine these two cases.
2455 * Regardless, guarantee that if we are using WDTR and SDTR
2456 * messages that WDTR comes first.
2458 if (doppr || (dosync && !dowide)) {
2460 offset = tinfo->goal.offset;
2461 ahc_validate_offset(ahc, tinfo, rate, &offset,
2462 doppr ? tinfo->goal.width
2463 : tinfo->curr.width,
2466 ahc_construct_ppr(ahc, devinfo, period, offset,
2467 tinfo->goal.width, ppr_options);
2469 ahc_construct_sdtr(ahc, devinfo, period, offset);
2472 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2477 * Build a synchronous negotiation message in our message
2478 * buffer based on the input parameters.
2481 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2482 u_int period, u_int offset)
2485 period = AHC_ASYNC_XFER_PERIOD;
2486 ahc->msgout_index += spi_populate_sync_msg(
2487 ahc->msgout_buf + ahc->msgout_index, period, offset);
2488 ahc->msgout_len += 5;
2490 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2491 ahc_name(ahc), devinfo->channel, devinfo->target,
2492 devinfo->lun, period, offset);
2497 * Build a wide negotiation message in our message
2498 * buffer based on the input parameters.
2501 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2504 ahc->msgout_index += spi_populate_width_msg(
2505 ahc->msgout_buf + ahc->msgout_index, bus_width);
2506 ahc->msgout_len += 4;
2508 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2509 ahc_name(ahc), devinfo->channel, devinfo->target,
2510 devinfo->lun, bus_width);
2515 * Build a parallel protocol request message in our message
2516 * buffer based on the input parameters.
2519 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2520 u_int period, u_int offset, u_int bus_width,
2524 period = AHC_ASYNC_XFER_PERIOD;
2525 ahc->msgout_index += spi_populate_ppr_msg(
2526 ahc->msgout_buf + ahc->msgout_index, period, offset,
2527 bus_width, ppr_options);
2528 ahc->msgout_len += 8;
2530 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2531 "offset %x, ppr_options %x\n", ahc_name(ahc),
2532 devinfo->channel, devinfo->target, devinfo->lun,
2533 bus_width, period, offset, ppr_options);
2538 * Clear any active message state.
2541 ahc_clear_msg_state(struct ahc_softc *ahc)
2543 ahc->msgout_len = 0;
2544 ahc->msgin_index = 0;
2545 ahc->msg_type = MSG_TYPE_NONE;
2546 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2548 * The target didn't care to respond to our
2549 * message request, so clear ATN.
2551 ahc_outb(ahc, CLRSINT1, CLRATNO);
2553 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2554 ahc_outb(ahc, SEQ_FLAGS2,
2555 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2559 ahc_handle_proto_violation(struct ahc_softc *ahc)
2561 struct ahc_devinfo devinfo;
2569 ahc_fetch_devinfo(ahc, &devinfo);
2570 scbid = ahc_inb(ahc, SCB_TAG);
2571 scb = ahc_lookup_scb(ahc, scbid);
2572 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2573 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2574 lastphase = ahc_inb(ahc, LASTPHASE);
2575 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2578 * The reconnecting target either did not send an
2579 * identify message, or did, but we didn't find an SCB
2582 ahc_print_devinfo(ahc, &devinfo);
2583 printf("Target did not send an IDENTIFY message. "
2584 "LASTPHASE = 0x%x.\n", lastphase);
2586 } else if (scb == NULL) {
2588 * We don't seem to have an SCB active for this
2589 * transaction. Print an error and reset the bus.
2591 ahc_print_devinfo(ahc, &devinfo);
2592 printf("No SCB found during protocol violation\n");
2593 goto proto_violation_reset;
2595 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2596 if ((seq_flags & NO_CDB_SENT) != 0) {
2597 ahc_print_path(ahc, scb);
2598 printf("No or incomplete CDB sent to device.\n");
2599 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2601 * The target never bothered to provide status to
2602 * us prior to completing the command. Since we don't
2603 * know the disposition of this command, we must attempt
2604 * to abort it. Assert ATN and prepare to send an abort
2607 ahc_print_path(ahc, scb);
2608 printf("Completed command without status.\n");
2610 ahc_print_path(ahc, scb);
2611 printf("Unknown protocol violation.\n");
2612 ahc_dump_card_state(ahc);
2615 if ((lastphase & ~P_DATAIN_DT) == 0
2616 || lastphase == P_COMMAND) {
2617 proto_violation_reset:
2619 * Target either went directly to data/command
2620 * phase or didn't respond to our ATN.
2621 * The only safe thing to do is to blow
2622 * it away with a bus reset.
2624 found = ahc_reset_channel(ahc, 'A', TRUE);
2625 printf("%s: Issued Channel %c Bus Reset. "
2626 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2629 * Leave the selection hardware off in case
2630 * this abort attempt will affect yet to
2633 ahc_outb(ahc, SCSISEQ,
2634 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2635 ahc_assert_atn(ahc);
2636 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2638 ahc_print_devinfo(ahc, &devinfo);
2639 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2640 ahc->msgout_len = 1;
2641 ahc->msgout_index = 0;
2642 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2644 ahc_print_path(ahc, scb);
2645 scb->flags |= SCB_ABORT;
2647 printf("Protocol violation %s. Attempting to abort.\n",
2648 ahc_lookup_phase_entry(curphase)->phasemsg);
2653 * Manual message loop handler.
2656 ahc_handle_message_phase(struct ahc_softc *ahc)
2658 struct ahc_devinfo devinfo;
2662 ahc_fetch_devinfo(ahc, &devinfo);
2663 end_session = FALSE;
2664 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2667 switch (ahc->msg_type) {
2668 case MSG_TYPE_INITIATOR_MSGOUT:
2674 if (ahc->msgout_len == 0)
2675 panic("HOST_MSG_LOOP interrupt with no active message");
2678 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2679 ahc_print_devinfo(ahc, &devinfo);
2680 printf("INITIATOR_MSG_OUT");
2683 phasemis = bus_phase != P_MESGOUT;
2686 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2687 printf(" PHASEMIS %s\n",
2688 ahc_lookup_phase_entry(bus_phase)
2692 if (bus_phase == P_MESGIN) {
2694 * Change gears and see if
2695 * this messages is of interest to
2696 * us or should be passed back to
2699 ahc_outb(ahc, CLRSINT1, CLRATNO);
2700 ahc->send_msg_perror = FALSE;
2701 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2702 ahc->msgin_index = 0;
2709 if (ahc->send_msg_perror) {
2710 ahc_outb(ahc, CLRSINT1, CLRATNO);
2711 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2713 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2714 printf(" byte 0x%x\n", ahc->send_msg_perror);
2716 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2720 msgdone = ahc->msgout_index == ahc->msgout_len;
2723 * The target has requested a retry.
2724 * Re-assert ATN, reset our message index to
2727 ahc->msgout_index = 0;
2728 ahc_assert_atn(ahc);
2731 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2733 /* Last byte is signified by dropping ATN */
2734 ahc_outb(ahc, CLRSINT1, CLRATNO);
2738 * Clear our interrupt status and present
2739 * the next byte on the bus.
2741 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2743 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2744 printf(" byte 0x%x\n",
2745 ahc->msgout_buf[ahc->msgout_index]);
2747 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2750 case MSG_TYPE_INITIATOR_MSGIN:
2756 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2757 ahc_print_devinfo(ahc, &devinfo);
2758 printf("INITIATOR_MSG_IN");
2761 phasemis = bus_phase != P_MESGIN;
2764 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2765 printf(" PHASEMIS %s\n",
2766 ahc_lookup_phase_entry(bus_phase)
2770 ahc->msgin_index = 0;
2771 if (bus_phase == P_MESGOUT
2772 && (ahc->send_msg_perror == TRUE
2773 || (ahc->msgout_len != 0
2774 && ahc->msgout_index == 0))) {
2775 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2782 /* Pull the byte in without acking it */
2783 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2785 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2786 printf(" byte 0x%x\n",
2787 ahc->msgin_buf[ahc->msgin_index]);
2790 message_done = ahc_parse_msg(ahc, &devinfo);
2794 * Clear our incoming message buffer in case there
2795 * is another message following this one.
2797 ahc->msgin_index = 0;
2800 * If this message illicited a response,
2801 * assert ATN so the target takes us to the
2802 * message out phase.
2804 if (ahc->msgout_len != 0) {
2806 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2807 ahc_print_devinfo(ahc, &devinfo);
2808 printf("Asserting ATN for response\n");
2811 ahc_assert_atn(ahc);
2816 if (message_done == MSGLOOP_TERMINATED) {
2820 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2821 ahc_inb(ahc, SCSIDATL);
2825 case MSG_TYPE_TARGET_MSGIN:
2830 if (ahc->msgout_len == 0)
2831 panic("Target MSGIN with no active message");
2834 * If we interrupted a mesgout session, the initiator
2835 * will not know this until our first REQ. So, we
2836 * only honor mesgout requests after we've sent our
2839 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2840 && ahc->msgout_index > 0)
2841 msgout_request = TRUE;
2843 msgout_request = FALSE;
2845 if (msgout_request) {
2848 * Change gears and see if
2849 * this messages is of interest to
2850 * us or should be passed back to
2853 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2854 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2855 ahc->msgin_index = 0;
2856 /* Dummy read to REQ for first byte */
2857 ahc_inb(ahc, SCSIDATL);
2858 ahc_outb(ahc, SXFRCTL0,
2859 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2863 msgdone = ahc->msgout_index == ahc->msgout_len;
2865 ahc_outb(ahc, SXFRCTL0,
2866 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2872 * Present the next byte on the bus.
2874 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2875 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2878 case MSG_TYPE_TARGET_MSGOUT:
2884 * The initiator signals that this is
2885 * the last byte by dropping ATN.
2887 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2890 * Read the latched byte, but turn off SPIOEN first
2891 * so that we don't inadvertently cause a REQ for the
2894 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2895 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2896 msgdone = ahc_parse_msg(ahc, &devinfo);
2897 if (msgdone == MSGLOOP_TERMINATED) {
2899 * The message is *really* done in that it caused
2900 * us to go to bus free. The sequencer has already
2901 * been reset at this point, so pull the ejection
2910 * XXX Read spec about initiator dropping ATN too soon
2911 * and use msgdone to detect it.
2913 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2914 ahc->msgin_index = 0;
2917 * If this message illicited a response, transition
2918 * to the Message in phase and send it.
2920 if (ahc->msgout_len != 0) {
2921 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2922 ahc_outb(ahc, SXFRCTL0,
2923 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2924 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2925 ahc->msgin_index = 0;
2933 /* Ask for the next byte. */
2934 ahc_outb(ahc, SXFRCTL0,
2935 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2941 panic("Unknown REQINIT message type");
2945 ahc_clear_msg_state(ahc);
2946 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2948 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2952 * See if we sent a particular extended message to the target.
2953 * If "full" is true, return true only if the target saw the full
2954 * message. If "full" is false, return true if the target saw at
2955 * least the first byte of the message.
2958 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2966 while (index < ahc->msgout_len) {
2967 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2970 end_index = index + 1 + ahc->msgout_buf[index + 1];
2971 if (ahc->msgout_buf[index+2] == msgval
2972 && type == AHCMSG_EXT) {
2975 if (ahc->msgout_index > end_index)
2977 } else if (ahc->msgout_index > index)
2981 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2982 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2984 /* Skip tag type and tag id or residue param*/
2987 /* Single byte message */
2988 if (type == AHCMSG_1B
2989 && ahc->msgout_buf[index] == msgval
2990 && ahc->msgout_index > index)
3002 * Wait for a complete incoming message, parse it, and respond accordingly.
3005 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3007 struct ahc_initiator_tinfo *tinfo;
3008 struct ahc_tmode_tstate *tstate;
3012 u_int targ_scsirate;
3014 done = MSGLOOP_IN_PROG;
3017 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3018 devinfo->target, &tstate);
3019 targ_scsirate = tinfo->scsirate;
3022 * Parse as much of the message as is available,
3023 * rejecting it if we don't support it. When
3024 * the entire message is available and has been
3025 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3026 * that we have parsed an entire message.
3028 * In the case of extended messages, we accept the length
3029 * byte outright and perform more checking once we know the
3030 * extended message type.
3032 switch (ahc->msgin_buf[0]) {
3033 case MSG_DISCONNECT:
3034 case MSG_SAVEDATAPOINTER:
3035 case MSG_CMDCOMPLETE:
3036 case MSG_RESTOREPOINTERS:
3037 case MSG_IGN_WIDE_RESIDUE:
3039 * End our message loop as these are messages
3040 * the sequencer handles on its own.
3042 done = MSGLOOP_TERMINATED;
3044 case MSG_MESSAGE_REJECT:
3045 response = ahc_handle_msg_reject(ahc, devinfo);
3048 done = MSGLOOP_MSGCOMPLETE;
3052 /* Wait for enough of the message to begin validation */
3053 if (ahc->msgin_index < 2)
3055 switch (ahc->msgin_buf[2]) {
3058 struct ahc_syncrate *syncrate;
3064 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3070 * Wait until we have both args before validating
3071 * and acting on this message.
3073 * Add one to MSG_EXT_SDTR_LEN to account for
3074 * the extended message preamble.
3076 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3079 period = ahc->msgin_buf[3];
3081 saved_offset = offset = ahc->msgin_buf[4];
3082 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3085 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3086 targ_scsirate & WIDEXFER,
3089 printf("(%s:%c:%d:%d): Received "
3090 "SDTR period %x, offset %x\n\t"
3091 "Filtered to period %x, offset %x\n",
3092 ahc_name(ahc), devinfo->channel,
3093 devinfo->target, devinfo->lun,
3094 ahc->msgin_buf[3], saved_offset,
3097 ahc_set_syncrate(ahc, devinfo,
3099 offset, ppr_options,
3100 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3104 * See if we initiated Sync Negotiation
3105 * and didn't have to fall down to async
3108 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3110 if (saved_offset != offset) {
3111 /* Went too low - force async */
3116 * Send our own SDTR in reply
3119 && devinfo->role == ROLE_INITIATOR) {
3120 printf("(%s:%c:%d:%d): Target "
3122 ahc_name(ahc), devinfo->channel,
3123 devinfo->target, devinfo->lun);
3125 ahc->msgout_index = 0;
3126 ahc->msgout_len = 0;
3127 ahc_construct_sdtr(ahc, devinfo,
3129 ahc->msgout_index = 0;
3132 done = MSGLOOP_MSGCOMPLETE;
3139 u_int sending_reply;
3141 sending_reply = FALSE;
3142 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3148 * Wait until we have our arg before validating
3149 * and acting on this message.
3151 * Add one to MSG_EXT_WDTR_LEN to account for
3152 * the extended message preamble.
3154 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3157 bus_width = ahc->msgin_buf[3];
3158 saved_width = bus_width;
3159 ahc_validate_width(ahc, tinfo, &bus_width,
3162 printf("(%s:%c:%d:%d): Received WDTR "
3163 "%x filtered to %x\n",
3164 ahc_name(ahc), devinfo->channel,
3165 devinfo->target, devinfo->lun,
3166 saved_width, bus_width);
3169 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3171 * Don't send a WDTR back to the
3172 * target, since we asked first.
3173 * If the width went higher than our
3174 * request, reject it.
3176 if (saved_width > bus_width) {
3178 printf("(%s:%c:%d:%d): requested %dBit "
3179 "transfers. Rejecting...\n",
3180 ahc_name(ahc), devinfo->channel,
3181 devinfo->target, devinfo->lun,
3182 8 * (0x01 << bus_width));
3187 * Send our own WDTR in reply
3190 && devinfo->role == ROLE_INITIATOR) {
3191 printf("(%s:%c:%d:%d): Target "
3193 ahc_name(ahc), devinfo->channel,
3194 devinfo->target, devinfo->lun);
3196 ahc->msgout_index = 0;
3197 ahc->msgout_len = 0;
3198 ahc_construct_wdtr(ahc, devinfo, bus_width);
3199 ahc->msgout_index = 0;
3201 sending_reply = TRUE;
3204 * After a wide message, we are async, but
3205 * some devices don't seem to honor this portion
3206 * of the spec. Force a renegotiation of the
3207 * sync component of our transfer agreement even
3208 * if our goal is async. By updating our width
3209 * after forcing the negotiation, we avoid
3210 * renegotiating for width.
3212 ahc_update_neg_request(ahc, devinfo, tstate,
3213 tinfo, AHC_NEG_ALWAYS);
3214 ahc_set_width(ahc, devinfo, bus_width,
3215 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3217 if (sending_reply == FALSE && reject == FALSE) {
3220 * We will always have an SDTR to send.
3222 ahc->msgout_index = 0;
3223 ahc->msgout_len = 0;
3224 ahc_build_transfer_msg(ahc, devinfo);
3225 ahc->msgout_index = 0;
3228 done = MSGLOOP_MSGCOMPLETE;
3233 struct ahc_syncrate *syncrate;
3240 u_int saved_ppr_options;
3242 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3248 * Wait until we have all args before validating
3249 * and acting on this message.
3251 * Add one to MSG_EXT_PPR_LEN to account for
3252 * the extended message preamble.
3254 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3257 period = ahc->msgin_buf[3];
3258 offset = ahc->msgin_buf[5];
3259 bus_width = ahc->msgin_buf[6];
3260 saved_width = bus_width;
3261 ppr_options = ahc->msgin_buf[7];
3263 * According to the spec, a DT only
3264 * period factor with no DT option
3265 * set implies async.
3267 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3270 saved_ppr_options = ppr_options;
3271 saved_offset = offset;
3274 * Mask out any options we don't support
3275 * on any controller. Transfer options are
3276 * only available if we are negotiating wide.
3278 ppr_options &= MSG_EXT_PPR_DT_REQ;
3282 ahc_validate_width(ahc, tinfo, &bus_width,
3284 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3287 ahc_validate_offset(ahc, tinfo, syncrate,
3291 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3293 * If we are unable to do any of the
3294 * requested options (we went too low),
3295 * then we'll have to reject the message.
3297 if (saved_width > bus_width
3298 || saved_offset != offset
3299 || saved_ppr_options != ppr_options) {
3308 if (devinfo->role != ROLE_TARGET)
3309 printf("(%s:%c:%d:%d): Target "
3311 ahc_name(ahc), devinfo->channel,
3312 devinfo->target, devinfo->lun);
3314 printf("(%s:%c:%d:%d): Initiator "
3316 ahc_name(ahc), devinfo->channel,
3317 devinfo->target, devinfo->lun);
3318 ahc->msgout_index = 0;
3319 ahc->msgout_len = 0;
3320 ahc_construct_ppr(ahc, devinfo, period, offset,
3321 bus_width, ppr_options);
3322 ahc->msgout_index = 0;
3326 printf("(%s:%c:%d:%d): Received PPR width %x, "
3327 "period %x, offset %x,options %x\n"
3328 "\tFiltered to width %x, period %x, "
3329 "offset %x, options %x\n",
3330 ahc_name(ahc), devinfo->channel,
3331 devinfo->target, devinfo->lun,
3332 saved_width, ahc->msgin_buf[3],
3333 saved_offset, saved_ppr_options,
3334 bus_width, period, offset, ppr_options);
3336 ahc_set_width(ahc, devinfo, bus_width,
3337 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3339 ahc_set_syncrate(ahc, devinfo,
3341 offset, ppr_options,
3342 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3344 done = MSGLOOP_MSGCOMPLETE;
3348 /* Unknown extended message. Reject it. */
3354 #ifdef AHC_TARGET_MODE
3355 case MSG_BUS_DEV_RESET:
3356 ahc_handle_devreset(ahc, devinfo,
3358 "Bus Device Reset Received",
3359 /*verbose_level*/0);
3361 done = MSGLOOP_TERMINATED;
3365 case MSG_CLEAR_QUEUE:
3369 /* Target mode messages */
3370 if (devinfo->role != ROLE_TARGET) {
3374 tag = SCB_LIST_NULL;
3375 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3376 tag = ahc_inb(ahc, INITIATOR_TAG);
3377 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3378 devinfo->lun, tag, ROLE_TARGET,
3381 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3382 if (tstate != NULL) {
3383 struct ahc_tmode_lstate* lstate;
3385 lstate = tstate->enabled_luns[devinfo->lun];
3386 if (lstate != NULL) {
3387 ahc_queue_lstate_event(ahc, lstate,
3388 devinfo->our_scsiid,
3391 ahc_send_lstate_events(ahc, lstate);
3395 done = MSGLOOP_TERMINATED;
3399 case MSG_TERM_IO_PROC:
3407 * Setup to reject the message.
3409 ahc->msgout_index = 0;
3410 ahc->msgout_len = 1;
3411 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3412 done = MSGLOOP_MSGCOMPLETE;
3416 if (done != MSGLOOP_IN_PROG && !response)
3417 /* Clear the outgoing message buffer */
3418 ahc->msgout_len = 0;
3424 * Process a message reject message.
3427 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3430 * What we care about here is if we had an
3431 * outstanding SDTR or WDTR message for this
3432 * target. If we did, this is a signal that
3433 * the target is refusing negotiation.
3436 struct ahc_initiator_tinfo *tinfo;
3437 struct ahc_tmode_tstate *tstate;
3442 scb_index = ahc_inb(ahc, SCB_TAG);
3443 scb = ahc_lookup_scb(ahc, scb_index);
3444 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3445 devinfo->our_scsiid,
3446 devinfo->target, &tstate);
3447 /* Might be necessary */
3448 last_msg = ahc_inb(ahc, LAST_MSG);
3450 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3452 * Target does not support the PPR message.
3453 * Attempt to negotiate SPI-2 style.
3456 printf("(%s:%c:%d:%d): PPR Rejected. "
3457 "Trying WDTR/SDTR\n",
3458 ahc_name(ahc), devinfo->channel,
3459 devinfo->target, devinfo->lun);
3461 tinfo->goal.ppr_options = 0;
3462 tinfo->curr.transport_version = 2;
3463 tinfo->goal.transport_version = 2;
3464 ahc->msgout_index = 0;
3465 ahc->msgout_len = 0;
3466 ahc_build_transfer_msg(ahc, devinfo);
3467 ahc->msgout_index = 0;
3469 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3471 /* note 8bit xfers */
3472 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3473 "8bit transfers\n", ahc_name(ahc),
3474 devinfo->channel, devinfo->target, devinfo->lun);
3475 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3476 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3479 * No need to clear the sync rate. If the target
3480 * did not accept the command, our syncrate is
3481 * unaffected. If the target started the negotiation,
3482 * but rejected our response, we already cleared the
3483 * sync rate before sending our WDTR.
3485 if (tinfo->goal.offset != tinfo->curr.offset) {
3487 /* Start the sync negotiation */
3488 ahc->msgout_index = 0;
3489 ahc->msgout_len = 0;
3490 ahc_build_transfer_msg(ahc, devinfo);
3491 ahc->msgout_index = 0;
3494 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3495 /* note asynch xfers and clear flag */
3496 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3497 /*offset*/0, /*ppr_options*/0,
3498 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3500 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3501 "Using asynchronous transfers\n",
3502 ahc_name(ahc), devinfo->channel,
3503 devinfo->target, devinfo->lun);
3504 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3508 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3510 if (tag_type == MSG_SIMPLE_TASK) {
3511 printf("(%s:%c:%d:%d): refuses tagged commands. "
3512 "Performing non-tagged I/O\n", ahc_name(ahc),
3513 devinfo->channel, devinfo->target, devinfo->lun);
3514 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
3517 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3518 "Performing simple queue tagged I/O only\n",
3519 ahc_name(ahc), devinfo->channel, devinfo->target,
3520 devinfo->lun, tag_type == MSG_ORDERED_TASK
3521 ? "ordered" : "head of queue");
3522 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
3527 * Resend the identify for this CCB as the target
3528 * may believe that the selection is invalid otherwise.
3530 ahc_outb(ahc, SCB_CONTROL,
3531 ahc_inb(ahc, SCB_CONTROL) & mask);
3532 scb->hscb->control &= mask;
3533 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3534 /*type*/MSG_SIMPLE_TASK);
3535 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3536 ahc_assert_atn(ahc);
3539 * This transaction is now at the head of
3540 * the untagged queue for this target.
3542 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3543 struct scb_tailq *untagged_q;
3546 &(ahc->untagged_queues[devinfo->target_offset]);
3547 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3548 scb->flags |= SCB_UNTAGGEDQ;
3550 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3554 * Requeue all tagged commands for this target
3555 * currently in our posession so they can be
3556 * converted to untagged commands.
3558 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3559 SCB_GET_CHANNEL(ahc, scb),
3560 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3561 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3565 * Otherwise, we ignore it.
3567 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3568 ahc_name(ahc), devinfo->channel, devinfo->target,
3575 * Process an ingnore wide residue message.
3578 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3583 scb_index = ahc_inb(ahc, SCB_TAG);
3584 scb = ahc_lookup_scb(ahc, scb_index);
3586 * XXX Actually check data direction in the sequencer?
3587 * Perhaps add datadir to some spare bits in the hscb?
3589 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3590 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3592 * Ignore the message if we haven't
3593 * seen an appropriate data phase yet.
3597 * If the residual occurred on the last
3598 * transfer and the transfer request was
3599 * expected to end on an odd count, do
3600 * nothing. Otherwise, subtract a byte
3601 * and update the residual count accordingly.
3605 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3606 if ((sgptr & SG_LIST_NULL) != 0
3607 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3609 * If the residual occurred on the last
3610 * transfer and the transfer request was
3611 * expected to end on an odd count, do
3615 struct ahc_dma_seg *sg;
3620 /* Pull in all of the sgptr */
3621 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3622 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3624 if ((sgptr & SG_LIST_NULL) != 0) {
3626 * The residual data count is not updated
3627 * for the command run to completion case.
3628 * Explicitly zero the count.
3630 data_cnt &= ~AHC_SG_LEN_MASK;
3633 data_addr = ahc_inl(ahc, SHADDR);
3637 sgptr &= SG_PTR_MASK;
3639 sg = ahc_sg_bus_to_virt(scb, sgptr);
3642 * The residual sg ptr points to the next S/G
3643 * to load so we must go back one.
3646 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3647 if (sg != scb->sg_list
3648 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3651 sglen = ahc_le32toh(sg->len);
3653 * Preserve High Address and SG_LIST bits
3654 * while setting the count to 1.
3656 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3657 data_addr = ahc_le32toh(sg->addr)
3658 + (sglen & AHC_SG_LEN_MASK) - 1;
3661 * Increment sg so it points to the
3665 sgptr = ahc_sg_virt_to_bus(scb, sg);
3667 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3668 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3670 * Toggle the "oddness" of the transfer length
3671 * to handle this mid-transfer ignore wide
3672 * residue. This ensures that the oddness is
3673 * correct for subsequent data transfers.
3675 ahc_outb(ahc, SCB_LUN,
3676 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3683 * Reinitialize the data pointers for the active transfer
3684 * based on its current residual.
3687 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3690 struct ahc_dma_seg *sg;
3696 scb_index = ahc_inb(ahc, SCB_TAG);
3697 scb = ahc_lookup_scb(ahc, scb_index);
3698 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3699 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3700 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3701 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3703 sgptr &= SG_PTR_MASK;
3704 sg = ahc_sg_bus_to_virt(scb, sgptr);
3706 /* The residual sg_ptr always points to the next sg */
3709 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3710 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3711 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3713 dataptr = ahc_le32toh(sg->addr)
3714 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3716 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3719 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3720 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3721 ahc_outb(ahc, HADDR,
3722 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3723 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3725 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3726 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3727 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3728 ahc_outb(ahc, HADDR, dataptr);
3729 ahc_outb(ahc, HCNT + 2, resid >> 16);
3730 ahc_outb(ahc, HCNT + 1, resid >> 8);
3731 ahc_outb(ahc, HCNT, resid);
3732 if ((ahc->features & AHC_ULTRA2) == 0) {
3733 ahc_outb(ahc, STCNT + 2, resid >> 16);
3734 ahc_outb(ahc, STCNT + 1, resid >> 8);
3735 ahc_outb(ahc, STCNT, resid);
3740 * Handle the effects of issuing a bus device reset message.
3743 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3744 cam_status status, char *message, int verbose_level)
3746 #ifdef AHC_TARGET_MODE
3747 struct ahc_tmode_tstate* tstate;
3752 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3753 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3756 #ifdef AHC_TARGET_MODE
3758 * Send an immediate notify ccb to all target mord peripheral
3759 * drivers affected by this action.
3761 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3762 if (tstate != NULL) {
3763 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3764 struct ahc_tmode_lstate* lstate;
3766 lstate = tstate->enabled_luns[lun];
3770 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3771 MSG_BUS_DEV_RESET, /*arg*/0);
3772 ahc_send_lstate_events(ahc, lstate);
3778 * Go back to async/narrow transfers and renegotiate.
3780 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3781 AHC_TRANS_CUR, /*paused*/TRUE);
3782 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3783 /*period*/0, /*offset*/0, /*ppr_options*/0,
3784 AHC_TRANS_CUR, /*paused*/TRUE);
3786 if (status != CAM_SEL_TIMEOUT)
3787 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3788 CAM_LUN_WILDCARD, AC_SENT_BDR);
3791 && (verbose_level <= bootverbose))
3792 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3793 message, devinfo->channel, devinfo->target, found);
3796 #ifdef AHC_TARGET_MODE
3798 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3803 * To facilitate adding multiple messages together,
3804 * each routine should increment the index and len
3805 * variables instead of setting them explicitly.
3807 ahc->msgout_index = 0;
3808 ahc->msgout_len = 0;
3810 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3811 ahc_build_transfer_msg(ahc, devinfo);
3813 panic("ahc_intr: AWAITING target message with no message");
3815 ahc->msgout_index = 0;
3816 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3819 /**************************** Initialization **********************************/
3821 * Allocate a controller structure for a new device
3822 * and perform initial initializion.
3825 ahc_alloc(void *platform_arg, char *name)
3827 struct ahc_softc *ahc;
3831 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3833 printf("aic7xxx: cannot malloc softc!\n");
3834 free(name, M_DEVBUF);
3838 ahc = device_get_softc((device_t)platform_arg);
3840 memset(ahc, 0, sizeof(*ahc));
3841 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3842 M_DEVBUF, M_NOWAIT);
3843 if (ahc->seep_config == NULL) {
3845 free(ahc, M_DEVBUF);
3847 free(name, M_DEVBUF);
3850 LIST_INIT(&ahc->pending_scbs);
3851 /* We don't know our unit number until the OSM sets it */
3854 ahc->description = NULL;
3856 ahc->channel_b = 'B';
3857 ahc->chip = AHC_NONE;
3858 ahc->features = AHC_FENONE;
3859 ahc->bugs = AHC_BUGNONE;
3860 ahc->flags = AHC_FNONE;
3862 * Default to all error reporting enabled with the
3863 * sequencer operating at its fastest speed.
3864 * The bus attach code may modify this.
3866 ahc->seqctl = FASTMODE;
3868 for (i = 0; i < AHC_NUM_TARGETS; i++)
3869 TAILQ_INIT(&ahc->untagged_queues[i]);
3870 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3878 ahc_softc_init(struct ahc_softc *ahc)
3881 /* The IRQMS bit is only valid on VL and EISA chips */
3882 if ((ahc->chip & AHC_PCI) == 0)
3883 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3886 ahc->pause = ahc->unpause | PAUSE;
3887 /* XXX The shared scb data stuff should be deprecated */
3888 if (ahc->scb_data == NULL) {
3889 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3890 M_DEVBUF, M_NOWAIT);
3891 if (ahc->scb_data == NULL)
3893 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3900 ahc_set_unit(struct ahc_softc *ahc, int unit)
3906 ahc_set_name(struct ahc_softc *ahc, char *name)
3908 if (ahc->name != NULL)
3909 free(ahc->name, M_DEVBUF);
3914 ahc_free(struct ahc_softc *ahc)
3918 switch (ahc->init_level) {
3924 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3925 ahc->shared_data_dmamap);
3928 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3929 ahc->shared_data_dmamap);
3930 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3931 ahc->shared_data_dmamap);
3934 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3937 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3945 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
3947 ahc_platform_free(ahc);
3948 ahc_fini_scbdata(ahc);
3949 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3950 struct ahc_tmode_tstate *tstate;
3952 tstate = ahc->enabled_targets[i];
3953 if (tstate != NULL) {
3954 #ifdef AHC_TARGET_MODE
3957 for (j = 0; j < AHC_NUM_LUNS; j++) {
3958 struct ahc_tmode_lstate *lstate;
3960 lstate = tstate->enabled_luns[j];
3961 if (lstate != NULL) {
3962 xpt_free_path(lstate->path);
3963 free(lstate, M_DEVBUF);
3967 free(tstate, M_DEVBUF);
3970 #ifdef AHC_TARGET_MODE
3971 if (ahc->black_hole != NULL) {
3972 xpt_free_path(ahc->black_hole->path);
3973 free(ahc->black_hole, M_DEVBUF);
3976 if (ahc->name != NULL)
3977 free(ahc->name, M_DEVBUF);
3978 if (ahc->seep_config != NULL)
3979 free(ahc->seep_config, M_DEVBUF);
3981 free(ahc, M_DEVBUF);
3987 ahc_shutdown(void *arg)
3989 struct ahc_softc *ahc;
3992 ahc = (struct ahc_softc *)arg;
3994 /* This will reset most registers to 0, but not all */
3995 ahc_reset(ahc, /*reinit*/FALSE);
3996 ahc_outb(ahc, SCSISEQ, 0);
3997 ahc_outb(ahc, SXFRCTL0, 0);
3998 ahc_outb(ahc, DSPCISTATUS, 0);
4000 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4001 ahc_outb(ahc, i, 0);
4005 * Reset the controller and record some information about it
4006 * that is only available just after a reset. If "reinit" is
4007 * non-zero, this reset occured after initial configuration
4008 * and the caller requests that the chip be fully reinitialized
4009 * to a runable state. Chip interrupts are *not* enabled after
4010 * a reinitialization. The caller must enable interrupts via
4011 * ahc_intr_enable().
4014 ahc_reset(struct ahc_softc *ahc, int reinit)
4017 u_int sxfrctl1_a, sxfrctl1_b;
4022 * Preserve the value of the SXFRCTL1 register for all channels.
4023 * It contains settings that affect termination and we don't want
4024 * to disturb the integrity of the bus.
4028 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4032 * Save channel B's settings in case this chip
4033 * is setup for TWIN channel operation.
4035 sblkctl = ahc_inb(ahc, SBLKCTL);
4036 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4037 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4038 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4040 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4042 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4045 * Ensure that the reset has finished. We delay 1000us
4046 * prior to reading the register to make sure the chip
4047 * has sufficiently completed its reset to handle register
4053 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4056 printf("%s: WARNING - Failed chip reset! "
4057 "Trying to initialize anyway.\n", ahc_name(ahc));
4059 ahc_outb(ahc, HCNTRL, ahc->pause);
4061 /* Determine channel configuration */
4062 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4063 /* No Twin Channel PCI cards */
4064 if ((ahc->chip & AHC_PCI) != 0)
4065 sblkctl &= ~SELBUSB;
4068 /* Single Narrow Channel */
4072 ahc->features |= AHC_WIDE;
4076 ahc->features |= AHC_TWIN;
4079 printf(" Unsupported adapter type. Ignoring\n");
4086 * We must always initialize STPWEN to 1 before we
4087 * restore the saved values. STPWEN is initialized
4088 * to a tri-state condition which can only be cleared
4091 if ((ahc->features & AHC_TWIN) != 0) {
4094 sblkctl = ahc_inb(ahc, SBLKCTL);
4095 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4096 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4097 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4099 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4104 * If a recovery action has forced a chip reset,
4105 * re-initialize the chip to our liking.
4107 error = ahc->bus_chip_init(ahc);
4117 * Determine the number of SCBs available on the controller
4120 ahc_probe_scbs(struct ahc_softc *ahc) {
4123 for (i = 0; i < AHC_SCB_MAX; i++) {
4125 ahc_outb(ahc, SCBPTR, i);
4126 ahc_outb(ahc, SCB_BASE, i);
4127 if (ahc_inb(ahc, SCB_BASE) != i)
4129 ahc_outb(ahc, SCBPTR, 0);
4130 if (ahc_inb(ahc, SCB_BASE) != 0)
4137 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4141 baddr = (dma_addr_t *)arg;
4142 *baddr = segs->ds_addr;
4146 ahc_build_free_scb_list(struct ahc_softc *ahc)
4152 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4155 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4158 ahc_outb(ahc, SCBPTR, i);
4161 * Touch all SCB bytes to avoid parity errors
4162 * should one of our debugging routines read
4163 * an otherwise uninitiatlized byte.
4165 for (j = 0; j < scbsize; j++)
4166 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4168 /* Clear the control byte. */
4169 ahc_outb(ahc, SCB_CONTROL, 0);
4171 /* Set the next pointer */
4172 if ((ahc->flags & AHC_PAGESCBS) != 0)
4173 ahc_outb(ahc, SCB_NEXT, i+1);
4175 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4177 /* Make the tag number, SCSIID, and lun invalid */
4178 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4179 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4180 ahc_outb(ahc, SCB_LUN, 0xFF);
4183 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4184 /* SCB 0 heads the free list. */
4185 ahc_outb(ahc, FREE_SCBH, 0);
4188 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4191 /* Make sure that the last SCB terminates the free list */
4192 ahc_outb(ahc, SCBPTR, i-1);
4193 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4197 ahc_init_scbdata(struct ahc_softc *ahc)
4199 struct scb_data *scb_data;
4201 scb_data = ahc->scb_data;
4202 SLIST_INIT(&scb_data->free_scbs);
4203 SLIST_INIT(&scb_data->sg_maps);
4205 /* Allocate SCB resources */
4206 scb_data->scbarray =
4207 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4208 M_DEVBUF, M_NOWAIT);
4209 if (scb_data->scbarray == NULL)
4211 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4213 /* Determine the number of hardware SCBs and initialize them */
4215 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4216 if (ahc->scb_data->maxhscbs == 0) {
4217 printf("%s: No SCB space found\n", ahc_name(ahc));
4222 * Create our DMA tags. These tags define the kinds of device
4223 * accessible memory allocations and memory mappings we will
4224 * need to perform during normal operation.
4226 * Unless we need to further restrict the allocation, we rely
4227 * on the restrictions of the parent dmat, hence the common
4228 * use of MAXADDR and MAXSIZE.
4231 /* DMA tag for our hardware scb structures */
4232 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4233 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4234 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4235 /*highaddr*/BUS_SPACE_MAXADDR,
4236 /*filter*/NULL, /*filterarg*/NULL,
4237 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4239 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4240 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4244 scb_data->init_level++;
4246 /* Allocation for our hscbs */
4247 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4248 (void **)&scb_data->hscbs,
4249 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4253 scb_data->init_level++;
4255 /* And permanently map them */
4256 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4258 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4259 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4261 scb_data->init_level++;
4263 /* DMA tag for our sense buffers */
4264 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4265 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4266 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4267 /*highaddr*/BUS_SPACE_MAXADDR,
4268 /*filter*/NULL, /*filterarg*/NULL,
4269 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4271 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4272 /*flags*/0, &scb_data->sense_dmat) != 0) {
4276 scb_data->init_level++;
4279 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4280 (void **)&scb_data->sense,
4281 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4285 scb_data->init_level++;
4287 /* And permanently map them */
4288 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4290 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4291 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4293 scb_data->init_level++;
4295 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4296 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4297 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4298 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4299 /*highaddr*/BUS_SPACE_MAXADDR,
4300 /*filter*/NULL, /*filterarg*/NULL,
4301 PAGE_SIZE, /*nsegments*/1,
4302 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4303 /*flags*/0, &scb_data->sg_dmat) != 0) {
4307 scb_data->init_level++;
4309 /* Perform initial CCB allocation */
4310 memset(scb_data->hscbs, 0,
4311 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4312 ahc_alloc_scbs(ahc);
4314 if (scb_data->numscbs == 0) {
4315 printf("%s: ahc_init_scbdata - "
4316 "Unable to allocate initial scbs\n",
4322 * Reserve the next queued SCB.
4324 ahc->next_queued_scb = ahc_get_scb(ahc);
4327 * Note that we were successfull
4337 ahc_fini_scbdata(struct ahc_softc *ahc)
4339 struct scb_data *scb_data;
4341 scb_data = ahc->scb_data;
4342 if (scb_data == NULL)
4345 switch (scb_data->init_level) {
4349 struct sg_map_node *sg_map;
4351 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4352 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4353 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4355 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4358 free(sg_map, M_DEVBUF);
4360 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4363 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4364 scb_data->sense_dmamap);
4366 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4367 scb_data->sense_dmamap);
4368 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4369 scb_data->sense_dmamap);
4371 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4373 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4374 scb_data->hscb_dmamap);
4376 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4377 scb_data->hscb_dmamap);
4378 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4379 scb_data->hscb_dmamap);
4381 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4386 if (scb_data->scbarray != NULL)
4387 free(scb_data->scbarray, M_DEVBUF);
4391 ahc_alloc_scbs(struct ahc_softc *ahc)
4393 struct scb_data *scb_data;
4394 struct scb *next_scb;
4395 struct sg_map_node *sg_map;
4396 dma_addr_t physaddr;
4397 struct ahc_dma_seg *segs;
4401 scb_data = ahc->scb_data;
4402 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4403 /* Can't allocate any more */
4406 next_scb = &scb_data->scbarray[scb_data->numscbs];
4408 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4413 /* Allocate S/G space for the next batch of SCBS */
4414 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4415 (void **)&sg_map->sg_vaddr,
4416 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4417 free(sg_map, M_DEVBUF);
4421 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4423 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4424 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4425 &sg_map->sg_physaddr, /*flags*/0);
4427 segs = sg_map->sg_vaddr;
4428 physaddr = sg_map->sg_physaddr;
4430 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4431 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4432 for (i = 0; i < newcount; i++) {
4433 struct scb_platform_data *pdata;
4437 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4438 M_DEVBUF, M_NOWAIT);
4441 next_scb->platform_data = pdata;
4442 next_scb->sg_map = sg_map;
4443 next_scb->sg_list = segs;
4445 * The sequencer always starts with the second entry.
4446 * The first entry is embedded in the scb.
4448 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4449 next_scb->ahc_softc = ahc;
4450 next_scb->flags = SCB_FREE;
4452 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4457 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4458 next_scb->hscb->tag = ahc->scb_data->numscbs;
4459 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4460 next_scb, links.sle);
4462 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4464 ahc->scb_data->numscbs++;
4469 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4473 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4475 if ((ahc->features & AHC_TWIN) != 0)
4476 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4477 "B SCSI Id=%d, primary %c, ",
4478 ahc->our_id, ahc->our_id_b,
4479 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4485 if ((ahc->features & AHC_ULTRA) != 0) {
4487 } else if ((ahc->features & AHC_DT) != 0) {
4488 speed = "Ultra160 ";
4489 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4492 if ((ahc->features & AHC_WIDE) != 0) {
4497 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4498 speed, type, ahc->channel, ahc->our_id);
4502 if ((ahc->flags & AHC_PAGESCBS) != 0)
4503 sprintf(buf, "%d/%d SCBs",
4504 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4506 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4510 ahc_chip_init(struct ahc_softc *ahc)
4516 u_int scsiseq_template;
4519 ahc_outb(ahc, SEQ_FLAGS, 0);
4520 ahc_outb(ahc, SEQ_FLAGS2, 0);
4522 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4523 if (ahc->features & AHC_TWIN) {
4526 * Setup Channel B first.
4528 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4529 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4530 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4531 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4532 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4533 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4534 if ((ahc->features & AHC_ULTRA2) != 0)
4535 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4536 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4537 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4539 /* Select Channel A */
4540 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4542 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4543 if ((ahc->features & AHC_ULTRA2) != 0)
4544 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4546 ahc_outb(ahc, SCSIID, ahc->our_id);
4547 scsi_conf = ahc_inb(ahc, SCSICONF);
4548 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4550 |ENSTIMER|ACTNEGEN);
4551 if ((ahc->features & AHC_ULTRA2) != 0)
4552 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4553 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4554 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4556 /* There are no untagged SCBs active yet. */
4557 for (i = 0; i < 16; i++) {
4558 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4559 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4563 * The SCB based BTT allows an entry per
4564 * target and lun pair.
4566 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4567 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4571 /* All of our queues are empty */
4572 for (i = 0; i < 256; i++)
4573 ahc->qoutfifo[i] = SCB_LIST_NULL;
4574 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4576 for (i = 0; i < 256; i++)
4577 ahc->qinfifo[i] = SCB_LIST_NULL;
4579 if ((ahc->features & AHC_MULTI_TID) != 0) {
4580 ahc_outb(ahc, TARGID, 0);
4581 ahc_outb(ahc, TARGID + 1, 0);
4585 * Tell the sequencer where it can find our arrays in memory.
4587 physaddr = ahc->scb_data->hscb_busaddr;
4588 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4589 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4590 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4591 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4593 physaddr = ahc->shared_data_busaddr;
4594 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4595 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4596 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4597 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4600 * Initialize the group code to command length table.
4601 * This overrides the values in TARG_SCSIRATE, so only
4602 * setup the table after we have processed that information.
4604 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4605 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4606 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4607 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4608 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4609 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4610 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4611 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4613 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4614 ahc_outb(ahc, HS_MAILBOX, 0);
4616 /* Tell the sequencer of our initial queue positions */
4617 if ((ahc->features & AHC_TARGETMODE) != 0) {
4618 ahc->tqinfifonext = 1;
4619 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4620 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4622 ahc->qinfifonext = 0;
4623 ahc->qoutfifonext = 0;
4624 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4625 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4626 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4627 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4628 ahc_outb(ahc, SDSCB_QOFF, 0);
4630 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4631 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4632 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4635 /* We don't have any waiting selections */
4636 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4638 /* Our disconnection list is empty too */
4639 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4641 /* Message out buffer starts empty */
4642 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4645 * Setup the allowed SCSI Sequences based on operational mode.
4646 * If we are a target, we'll enalbe select in operations once
4647 * we've had a lun enabled.
4649 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4650 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4651 scsiseq_template |= ENRSELI;
4652 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4654 /* Initialize our list of free SCBs. */
4655 ahc_build_free_scb_list(ahc);
4658 * Tell the sequencer which SCB will be the next one it receives.
4660 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4663 * Load the Sequencer program and Enable the adapter
4667 printf("%s: Downloading Sequencer Program...",
4670 error = ahc_loadseq(ahc);
4674 if ((ahc->features & AHC_ULTRA2) != 0) {
4678 * Wait for up to 500ms for our transceivers
4679 * to settle. If the adapter does not have
4680 * a cable attached, the transceivers may
4681 * never settle, so don't complain if we
4685 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4694 * Start the board, ready for normal operation
4697 ahc_init(struct ahc_softc *ahc)
4705 size_t driver_data_size;
4708 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4709 ahc->flags |= AHC_SEQUENCER_DEBUG;
4712 #ifdef AHC_PRINT_SRAM
4713 printf("Scratch Ram:");
4714 for (i = 0x20; i < 0x5f; i++) {
4715 if (((i % 8) == 0) && (i != 0)) {
4718 printf (" 0x%x", ahc_inb(ahc, i));
4720 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4721 for (i = 0x70; i < 0x7f; i++) {
4722 if (((i % 8) == 0) && (i != 0)) {
4725 printf (" 0x%x", ahc_inb(ahc, i));
4730 * Reading uninitialized scratch ram may
4731 * generate parity errors.
4733 ahc_outb(ahc, CLRINT, CLRPARERR);
4734 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4739 * Assume we have a board at this stage and it has been reset.
4741 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4742 ahc->our_id = ahc->our_id_b = 7;
4745 * Default to allowing initiator operations.
4747 ahc->flags |= AHC_INITIATORROLE;
4750 * Only allow target mode features if this unit has them enabled.
4752 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4753 ahc->features &= ~AHC_TARGETMODE;
4756 /* DMA tag for mapping buffers into device visible space. */
4757 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4758 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4759 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4760 ? (dma_addr_t)0x7FFFFFFFFFULL
4761 : BUS_SPACE_MAXADDR_32BIT,
4762 /*highaddr*/BUS_SPACE_MAXADDR,
4763 /*filter*/NULL, /*filterarg*/NULL,
4764 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4765 /*nsegments*/AHC_NSEG,
4766 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4767 /*flags*/BUS_DMA_ALLOCNOW,
4768 &ahc->buffer_dmat) != 0) {
4776 * DMA tag for our command fifos and other data in system memory
4777 * the card's sequencer must be able to access. For initiator
4778 * roles, we need to allocate space for the qinfifo and qoutfifo.
4779 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4780 * When providing for the target mode role, we must additionally
4781 * provide space for the incoming target command fifo and an extra
4782 * byte to deal with a dma bug in some chip versions.
4784 driver_data_size = 2 * 256 * sizeof(uint8_t);
4785 if ((ahc->features & AHC_TARGETMODE) != 0)
4786 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4787 + /*DMA WideOdd Bug Buffer*/1;
4788 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4789 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4790 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4791 /*highaddr*/BUS_SPACE_MAXADDR,
4792 /*filter*/NULL, /*filterarg*/NULL,
4795 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4796 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4802 /* Allocation of driver data */
4803 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4804 (void **)&ahc->qoutfifo,
4805 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4811 /* And permanently map it in */
4812 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4813 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4814 &ahc->shared_data_busaddr, /*flags*/0);
4816 if ((ahc->features & AHC_TARGETMODE) != 0) {
4817 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4818 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4819 ahc->dma_bug_buf = ahc->shared_data_busaddr
4820 + driver_data_size - 1;
4821 /* All target command blocks start out invalid. */
4822 for (i = 0; i < AHC_TMODE_CMDS; i++)
4823 ahc->targetcmds[i].cmd_valid = 0;
4824 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4825 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4827 ahc->qinfifo = &ahc->qoutfifo[256];
4831 /* Allocate SCB data now that buffer_dmat is initialized */
4832 if (ahc->scb_data->maxhscbs == 0)
4833 if (ahc_init_scbdata(ahc) != 0)
4837 * Allocate a tstate to house information for our
4838 * initiator presence on the bus as well as the user
4839 * data for any target mode initiator.
4841 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4842 printf("%s: unable to allocate ahc_tmode_tstate. "
4843 "Failing attach\n", ahc_name(ahc));
4847 if ((ahc->features & AHC_TWIN) != 0) {
4848 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4849 printf("%s: unable to allocate ahc_tmode_tstate. "
4850 "Failing attach\n", ahc_name(ahc));
4855 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4856 ahc->flags |= AHC_PAGESCBS;
4858 ahc->flags &= ~AHC_PAGESCBS;
4862 if (ahc_debug & AHC_SHOW_MISC) {
4863 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4864 "ahc_dma %u bytes\n",
4866 (u_int)sizeof(struct hardware_scb),
4867 (u_int)sizeof(struct scb),
4868 (u_int)sizeof(struct ahc_dma_seg));
4870 #endif /* AHC_DEBUG */
4873 * Look at the information that board initialization or
4874 * the board bios has left us.
4876 if (ahc->features & AHC_TWIN) {
4877 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4878 if ((scsi_conf & RESET_SCSI) != 0
4879 && (ahc->flags & AHC_INITIATORROLE) != 0)
4880 ahc->flags |= AHC_RESET_BUS_B;
4883 scsi_conf = ahc_inb(ahc, SCSICONF);
4884 if ((scsi_conf & RESET_SCSI) != 0
4885 && (ahc->flags & AHC_INITIATORROLE) != 0)
4886 ahc->flags |= AHC_RESET_BUS_A;
4889 tagenable = ALL_TARGETS_MASK;
4891 /* Grab the disconnection disable table and invert it for our needs */
4892 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4893 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4894 "device parameters\n", ahc_name(ahc));
4895 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4896 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4897 discenable = ALL_TARGETS_MASK;
4898 if ((ahc->features & AHC_ULTRA) != 0)
4899 ultraenb = ALL_TARGETS_MASK;
4901 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4902 | ahc_inb(ahc, DISC_DSB));
4903 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4904 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4905 | ahc_inb(ahc, ULTRA_ENB);
4908 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4911 for (i = 0; i <= max_targ; i++) {
4912 struct ahc_initiator_tinfo *tinfo;
4913 struct ahc_tmode_tstate *tstate;
4919 our_id = ahc->our_id;
4921 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4923 our_id = ahc->our_id_b;
4926 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4927 target_id, &tstate);
4928 /* Default to async narrow across the board */
4929 memset(tinfo, 0, sizeof(*tinfo));
4930 if (ahc->flags & AHC_USEDEFAULTS) {
4931 if ((ahc->features & AHC_WIDE) != 0)
4932 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4935 * These will be truncated when we determine the
4936 * connection type we have with the target.
4938 tinfo->user.period = ahc_syncrates->period;
4939 tinfo->user.offset = MAX_OFFSET;
4944 /* Take the settings leftover in scratch RAM. */
4945 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4947 if ((ahc->features & AHC_ULTRA2) != 0) {
4951 if ((scsirate & SOFS) == 0x0F) {
4953 * Haven't negotiated yet,
4954 * so the format is different.
4956 scsirate = (scsirate & SXFR) >> 4
4959 | (scsirate & WIDEXFER);
4960 offset = MAX_OFFSET_ULTRA2;
4962 offset = ahc_inb(ahc, TARG_OFFSET + i);
4963 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4964 /* Set to the lowest sync rate, 5MHz */
4966 maxsync = AHC_SYNCRATE_ULTRA2;
4967 if ((ahc->features & AHC_DT) != 0)
4968 maxsync = AHC_SYNCRATE_DT;
4969 tinfo->user.period =
4970 ahc_find_period(ahc, scsirate, maxsync);
4972 tinfo->user.period = 0;
4974 tinfo->user.offset = MAX_OFFSET;
4975 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4976 && (ahc->features & AHC_DT) != 0)
4977 tinfo->user.ppr_options =
4979 } else if ((scsirate & SOFS) != 0) {
4980 if ((scsirate & SXFR) == 0x40
4981 && (ultraenb & mask) != 0) {
4982 /* Treat 10MHz as a non-ultra speed */
4986 tinfo->user.period =
4987 ahc_find_period(ahc, scsirate,
4989 ? AHC_SYNCRATE_ULTRA
4990 : AHC_SYNCRATE_FAST);
4991 if (tinfo->user.period != 0)
4992 tinfo->user.offset = MAX_OFFSET;
4994 if (tinfo->user.period == 0)
4995 tinfo->user.offset = 0;
4996 if ((scsirate & WIDEXFER) != 0
4997 && (ahc->features & AHC_WIDE) != 0)
4998 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4999 tinfo->user.protocol_version = 4;
5000 if ((ahc->features & AHC_DT) != 0)
5001 tinfo->user.transport_version = 3;
5003 tinfo->user.transport_version = 2;
5004 tinfo->goal.protocol_version = 2;
5005 tinfo->goal.transport_version = 2;
5006 tinfo->curr.protocol_version = 2;
5007 tinfo->curr.transport_version = 2;
5009 tstate->ultraenb = 0;
5011 ahc->user_discenable = discenable;
5012 ahc->user_tagenable = tagenable;
5014 return (ahc->bus_chip_init(ahc));
5018 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5022 hcntrl = ahc_inb(ahc, HCNTRL);
5024 ahc->pause &= ~INTEN;
5025 ahc->unpause &= ~INTEN;
5028 ahc->pause |= INTEN;
5029 ahc->unpause |= INTEN;
5031 ahc_outb(ahc, HCNTRL, hcntrl);
5035 * Ensure that the card is paused in a location
5036 * outside of all critical sections and that all
5037 * pending work is completed prior to returning.
5038 * This routine should only be called from outside
5039 * an interrupt context.
5042 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5049 ahc->flags |= AHC_ALL_INTERRUPTS;
5055 * Give the sequencer some time to service
5056 * any active selections.
5063 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5064 intstat = ahc_inb(ahc, INTSTAT);
5065 if ((intstat & INT_PEND) == 0) {
5066 ahc_clear_critical_section(ahc);
5067 intstat = ahc_inb(ahc, INTSTAT);
5070 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5071 && ((intstat & INT_PEND) != 0
5072 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5073 if (maxloops == 0) {
5074 printf("Infinite interrupt loop, INTSTAT = %x",
5075 ahc_inb(ahc, INTSTAT));
5077 ahc_platform_flushwork(ahc);
5078 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5082 ahc_suspend(struct ahc_softc *ahc)
5085 ahc_pause_and_flushwork(ahc);
5087 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5092 #ifdef AHC_TARGET_MODE
5094 * XXX What about ATIOs that have not yet been serviced?
5095 * Perhaps we should just refuse to be suspended if we
5096 * are acting in a target role.
5098 if (ahc->pending_device != NULL) {
5108 ahc_resume(struct ahc_softc *ahc)
5111 ahc_reset(ahc, /*reinit*/TRUE);
5112 ahc_intr_enable(ahc, TRUE);
5117 /************************** Busy Target Table *********************************/
5119 * Return the untagged transaction id for a given target/channel lun.
5120 * Optionally, clear the entry.
5123 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5126 u_int target_offset;
5128 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5131 saved_scbptr = ahc_inb(ahc, SCBPTR);
5132 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5133 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5134 ahc_outb(ahc, SCBPTR, saved_scbptr);
5136 target_offset = TCL_TARGET_OFFSET(tcl);
5137 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5144 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5146 u_int target_offset;
5148 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5151 saved_scbptr = ahc_inb(ahc, SCBPTR);
5152 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5153 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5154 ahc_outb(ahc, SCBPTR, saved_scbptr);
5156 target_offset = TCL_TARGET_OFFSET(tcl);
5157 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5162 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5164 u_int target_offset;
5166 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5169 saved_scbptr = ahc_inb(ahc, SCBPTR);
5170 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5171 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5172 ahc_outb(ahc, SCBPTR, saved_scbptr);
5174 target_offset = TCL_TARGET_OFFSET(tcl);
5175 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5179 /************************** SCB and SCB queue management **********************/
5181 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5182 char channel, int lun, u_int tag, role_t role)
5184 int targ = SCB_GET_TARGET(ahc, scb);
5185 char chan = SCB_GET_CHANNEL(ahc, scb);
5186 int slun = SCB_GET_LUN(scb);
5189 match = ((chan == channel) || (channel == ALL_CHANNELS));
5191 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5193 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5195 #ifdef AHC_TARGET_MODE
5198 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5199 if (role == ROLE_INITIATOR) {
5200 match = (group != XPT_FC_GROUP_TMODE)
5201 && ((tag == scb->hscb->tag)
5202 || (tag == SCB_LIST_NULL));
5203 } else if (role == ROLE_TARGET) {
5204 match = (group == XPT_FC_GROUP_TMODE)
5205 && ((tag == scb->io_ctx->csio.tag_id)
5206 || (tag == SCB_LIST_NULL));
5208 #else /* !AHC_TARGET_MODE */
5209 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5210 #endif /* AHC_TARGET_MODE */
5217 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5223 target = SCB_GET_TARGET(ahc, scb);
5224 lun = SCB_GET_LUN(scb);
5225 channel = SCB_GET_CHANNEL(ahc, scb);
5227 ahc_search_qinfifo(ahc, target, channel, lun,
5228 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5229 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5231 ahc_platform_freeze_devq(ahc, scb);
5235 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5237 struct scb *prev_scb;
5240 if (ahc_qinfifo_count(ahc) != 0) {
5244 prev_pos = ahc->qinfifonext - 1;
5245 prev_tag = ahc->qinfifo[prev_pos];
5246 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5248 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5249 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5250 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5252 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5257 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5260 if (prev_scb == NULL) {
5261 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5263 prev_scb->hscb->next = scb->hscb->tag;
5264 ahc_sync_scb(ahc, prev_scb,
5265 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5267 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5268 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5269 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5273 ahc_qinfifo_count(struct ahc_softc *ahc)
5278 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5279 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5280 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5282 qinpos = ahc_inb(ahc, QINPOS);
5283 diff = ahc->qinfifonext - qinpos;
5288 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5289 int lun, u_int tag, role_t role, uint32_t status,
5290 ahc_search_action action)
5293 struct scb *prev_scb;
5303 qintail = ahc->qinfifonext;
5304 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5306 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5307 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5309 qinstart = ahc_inb(ahc, QINPOS);
5314 if (action == SEARCH_COMPLETE) {
5316 * Don't attempt to run any queued untagged transactions
5317 * until we are done with the abort process.
5319 ahc_freeze_untagged_queues(ahc);
5323 * Start with an empty queue. Entries that are not chosen
5324 * for removal will be re-added to the queue as we go.
5326 ahc->qinfifonext = qinpos;
5327 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5329 while (qinpos != qintail) {
5330 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5332 printf("qinpos = %d, SCB index = %d\n",
5333 qinpos, ahc->qinfifo[qinpos]);
5337 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5339 * We found an scb that needs to be acted on.
5343 case SEARCH_COMPLETE:
5348 ostat = ahc_get_transaction_status(scb);
5349 if (ostat == CAM_REQ_INPROG)
5350 ahc_set_transaction_status(scb, status);
5351 cstat = ahc_get_transaction_status(scb);
5352 if (cstat != CAM_REQ_CMP)
5353 ahc_freeze_scb(scb);
5354 if ((scb->flags & SCB_ACTIVE) == 0)
5355 printf("Inactive SCB in qinfifo\n");
5363 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5368 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5374 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5375 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5377 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5380 if (action != SEARCH_COUNT
5382 && (qinstart != ahc->qinfifonext)) {
5384 * The sequencer may be in the process of dmaing
5385 * down the SCB at the beginning of the queue.
5386 * This could be problematic if either the first,
5387 * or the second SCB is removed from the queue
5388 * (the first SCB includes a pointer to the "next"
5389 * SCB to dma). If we have removed any entries, swap
5390 * the first element in the queue with the next HSCB
5391 * so the sequencer will notice that NEXT_QUEUED_SCB
5392 * has changed during its dma attempt and will retry
5395 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5398 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5399 found, qinstart, ahc->qinfifonext);
5400 panic("First/Second Qinfifo fixup\n");
5403 * ahc_swap_with_next_hscb forces our next pointer to
5404 * point to the reserved SCB for future commands. Save
5405 * and restore our original next pointer to maintain
5408 next = scb->hscb->next;
5409 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5410 ahc_swap_with_next_hscb(ahc, scb);
5411 scb->hscb->next = next;
5412 ahc->qinfifo[qinstart] = scb->hscb->tag;
5414 /* Tell the card about the new head of the qinfifo. */
5415 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5417 /* Fixup the tail "next" pointer. */
5418 qintail = ahc->qinfifonext - 1;
5419 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5420 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5424 * Search waiting for selection list.
5426 curscbptr = ahc_inb(ahc, SCBPTR);
5427 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5428 prev = SCB_LIST_NULL;
5430 while (next != SCB_LIST_NULL) {
5433 ahc_outb(ahc, SCBPTR, next);
5434 scb_index = ahc_inb(ahc, SCB_TAG);
5435 if (scb_index >= ahc->scb_data->numscbs) {
5436 printf("Waiting List inconsistency. "
5437 "SCB index == %d, yet numscbs == %d.",
5438 scb_index, ahc->scb_data->numscbs);
5439 ahc_dump_card_state(ahc);
5440 panic("for safety");
5442 scb = ahc_lookup_scb(ahc, scb_index);
5444 printf("scb_index = %d, next = %d\n",
5446 panic("Waiting List traversal\n");
5448 if (ahc_match_scb(ahc, scb, target, channel,
5449 lun, SCB_LIST_NULL, role)) {
5451 * We found an scb that needs to be acted on.
5455 case SEARCH_COMPLETE:
5460 ostat = ahc_get_transaction_status(scb);
5461 if (ostat == CAM_REQ_INPROG)
5462 ahc_set_transaction_status(scb,
5464 cstat = ahc_get_transaction_status(scb);
5465 if (cstat != CAM_REQ_CMP)
5466 ahc_freeze_scb(scb);
5467 if ((scb->flags & SCB_ACTIVE) == 0)
5468 printf("Inactive SCB in Waiting List\n");
5473 next = ahc_rem_wscb(ahc, next, prev);
5477 next = ahc_inb(ahc, SCB_NEXT);
5483 next = ahc_inb(ahc, SCB_NEXT);
5486 ahc_outb(ahc, SCBPTR, curscbptr);
5488 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5489 channel, lun, status, action);
5491 if (action == SEARCH_COMPLETE)
5492 ahc_release_untagged_queues(ahc);
5497 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5498 int target, char channel, int lun, uint32_t status,
5499 ahc_search_action action)
5506 if (action == SEARCH_COMPLETE) {
5508 * Don't attempt to run any queued untagged transactions
5509 * until we are done with the abort process.
5511 ahc_freeze_untagged_queues(ahc);
5516 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5519 if (target != CAM_TARGET_WILDCARD) {
5530 for (; i < maxtarget; i++) {
5531 struct scb_tailq *untagged_q;
5532 struct scb *next_scb;
5534 untagged_q = &(ahc->untagged_queues[i]);
5535 next_scb = TAILQ_FIRST(untagged_q);
5536 while (next_scb != NULL) {
5539 next_scb = TAILQ_NEXT(scb, links.tqe);
5542 * The head of the list may be the currently
5543 * active untagged command for a device.
5544 * We're only searching for commands that
5545 * have not been started. A transaction
5546 * marked active but still in the qinfifo
5547 * is removed by the qinfifo scanning code
5550 if ((scb->flags & SCB_ACTIVE) != 0)
5553 if (ahc_match_scb(ahc, scb, target, channel, lun,
5554 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5555 || (ctx != NULL && ctx != scb->io_ctx))
5559 * We found an scb that needs to be acted on.
5563 case SEARCH_COMPLETE:
5568 ostat = ahc_get_transaction_status(scb);
5569 if (ostat == CAM_REQ_INPROG)
5570 ahc_set_transaction_status(scb, status);
5571 cstat = ahc_get_transaction_status(scb);
5572 if (cstat != CAM_REQ_CMP)
5573 ahc_freeze_scb(scb);
5574 if ((scb->flags & SCB_ACTIVE) == 0)
5575 printf("Inactive SCB in untaggedQ\n");
5580 scb->flags &= ~SCB_UNTAGGEDQ;
5581 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5589 if (action == SEARCH_COMPLETE)
5590 ahc_release_untagged_queues(ahc);
5595 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5596 int lun, u_int tag, int stop_on_first, int remove,
5606 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5607 prev = SCB_LIST_NULL;
5610 /* restore this when we're done */
5611 active_scb = ahc_inb(ahc, SCBPTR);
5613 /* Silence compiler */
5614 active_scb = SCB_LIST_NULL;
5616 while (next != SCB_LIST_NULL) {
5619 ahc_outb(ahc, SCBPTR, next);
5620 scb_index = ahc_inb(ahc, SCB_TAG);
5621 if (scb_index >= ahc->scb_data->numscbs) {
5622 printf("Disconnected List inconsistency. "
5623 "SCB index == %d, yet numscbs == %d.",
5624 scb_index, ahc->scb_data->numscbs);
5625 ahc_dump_card_state(ahc);
5626 panic("for safety");
5630 panic("Disconnected List Loop. "
5631 "cur SCBPTR == %x, prev SCBPTR == %x.",
5634 scbp = ahc_lookup_scb(ahc, scb_index);
5635 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5636 tag, ROLE_INITIATOR)) {
5640 ahc_rem_scb_from_disc_list(ahc, prev, next);
5643 next = ahc_inb(ahc, SCB_NEXT);
5649 next = ahc_inb(ahc, SCB_NEXT);
5653 ahc_outb(ahc, SCBPTR, active_scb);
5658 * Remove an SCB from the on chip list of disconnected transactions.
5659 * This is empty/unused if we are not performing SCB paging.
5662 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5666 ahc_outb(ahc, SCBPTR, scbptr);
5667 next = ahc_inb(ahc, SCB_NEXT);
5669 ahc_outb(ahc, SCB_CONTROL, 0);
5671 ahc_add_curscb_to_free_list(ahc);
5673 if (prev != SCB_LIST_NULL) {
5674 ahc_outb(ahc, SCBPTR, prev);
5675 ahc_outb(ahc, SCB_NEXT, next);
5677 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5683 * Add the SCB as selected by SCBPTR onto the on chip list of
5684 * free hardware SCBs. This list is empty/unused if we are not
5685 * performing SCB paging.
5688 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5691 * Invalidate the tag so that our abort
5692 * routines don't think it's active.
5694 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5696 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5697 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5698 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5703 * Manipulate the waiting for selection list and return the
5704 * scb that follows the one that we remove.
5707 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5712 * Select the SCB we want to abort and
5713 * pull the next pointer out of it.
5715 curscb = ahc_inb(ahc, SCBPTR);
5716 ahc_outb(ahc, SCBPTR, scbpos);
5717 next = ahc_inb(ahc, SCB_NEXT);
5719 /* Clear the necessary fields */
5720 ahc_outb(ahc, SCB_CONTROL, 0);
5722 ahc_add_curscb_to_free_list(ahc);
5724 /* update the waiting list */
5725 if (prev == SCB_LIST_NULL) {
5726 /* First in the list */
5727 ahc_outb(ahc, WAITING_SCBH, next);
5730 * Ensure we aren't attempting to perform
5731 * selection for this entry.
5733 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5736 * Select the scb that pointed to us
5737 * and update its next pointer.
5739 ahc_outb(ahc, SCBPTR, prev);
5740 ahc_outb(ahc, SCB_NEXT, next);
5744 * Point us back at the original scb position.
5746 ahc_outb(ahc, SCBPTR, curscb);
5750 /******************************** Error Handling ******************************/
5752 * Abort all SCBs that match the given description (target/channel/lun/tag),
5753 * setting their status to the passed in status if the status has not already
5754 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5755 * is paused before it is called.
5758 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5759 int lun, u_int tag, role_t role, uint32_t status)
5762 struct scb *scbp_next;
5772 * Don't attempt to run any queued untagged transactions
5773 * until we are done with the abort process.
5775 ahc_freeze_untagged_queues(ahc);
5777 /* restore this when we're done */
5778 active_scb = ahc_inb(ahc, SCBPTR);
5780 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5781 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5784 * Clean out the busy target table for any untagged commands.
5788 if (target != CAM_TARGET_WILDCARD) {
5795 if (lun == CAM_LUN_WILDCARD) {
5798 * Unless we are using an SCB based
5799 * busy targets table, there is only
5800 * one table entry for all luns of
5805 if ((ahc->flags & AHC_SCB_BTT) != 0)
5806 maxlun = AHC_NUM_LUNS;
5812 if (role != ROLE_TARGET) {
5813 for (;i < maxtarget; i++) {
5814 for (j = minlun;j < maxlun; j++) {
5818 tcl = BUILD_TCL(i << 4, j);
5819 scbid = ahc_index_busy_tcl(ahc, tcl);
5820 scbp = ahc_lookup_scb(ahc, scbid);
5822 || ahc_match_scb(ahc, scbp, target, channel,
5823 lun, tag, role) == 0)
5825 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5830 * Go through the disconnected list and remove any entries we
5831 * have queued for completion, 0'ing their control byte too.
5832 * We save the active SCB and restore it ourselves, so there
5833 * is no reason for this search to restore it too.
5835 ahc_search_disc_list(ahc, target, channel, lun, tag,
5836 /*stop_on_first*/FALSE, /*remove*/TRUE,
5837 /*save_state*/FALSE);
5841 * Go through the hardware SCB array looking for commands that
5842 * were active but not on any list. In some cases, these remnants
5843 * might not still have mappings in the scbindex array (e.g. unexpected
5844 * bus free with the same scb queued for an abort). Don't hold this
5847 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5850 ahc_outb(ahc, SCBPTR, i);
5851 scbid = ahc_inb(ahc, SCB_TAG);
5852 scbp = ahc_lookup_scb(ahc, scbid);
5853 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5855 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5856 ahc_add_curscb_to_free_list(ahc);
5860 * Go through the pending CCB list and look for
5861 * commands for this target that are still active.
5862 * These are other tagged commands that were
5863 * disconnected when the reset occurred.
5865 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5866 while (scbp_next != NULL) {
5868 scbp_next = LIST_NEXT(scbp, pending_links);
5869 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5872 ostat = ahc_get_transaction_status(scbp);
5873 if (ostat == CAM_REQ_INPROG)
5874 ahc_set_transaction_status(scbp, status);
5875 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5876 ahc_freeze_scb(scbp);
5877 if ((scbp->flags & SCB_ACTIVE) == 0)
5878 printf("Inactive SCB on pending list\n");
5879 ahc_done(ahc, scbp);
5883 ahc_outb(ahc, SCBPTR, active_scb);
5884 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5885 ahc_release_untagged_queues(ahc);
5890 ahc_reset_current_bus(struct ahc_softc *ahc)
5894 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5895 scsiseq = ahc_inb(ahc, SCSISEQ);
5896 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5897 ahc_flush_device_writes(ahc);
5898 ahc_delay(AHC_BUSRESET_DELAY);
5899 /* Turn off the bus reset */
5900 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5902 ahc_clear_intstat(ahc);
5904 /* Re-enable reset interrupts */
5905 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5909 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5911 struct ahc_devinfo devinfo;
5912 u_int initiator, target, max_scsiid;
5920 ahc->pending_device = NULL;
5922 ahc_compile_devinfo(&devinfo,
5923 CAM_TARGET_WILDCARD,
5924 CAM_TARGET_WILDCARD,
5926 channel, ROLE_UNKNOWN);
5929 /* Make sure the sequencer is in a safe location. */
5930 ahc_clear_critical_section(ahc);
5933 * Run our command complete fifos to ensure that we perform
5934 * completion processing on any commands that 'completed'
5935 * before the reset occurred.
5937 ahc_run_qoutfifo(ahc);
5938 #ifdef AHC_TARGET_MODE
5940 * XXX - In Twin mode, the tqinfifo may have commands
5941 * for an unaffected channel in it. However, if
5942 * we have run out of ATIO resources to drain that
5943 * queue, we may not get them all out here. Further,
5944 * the blocked transactions for the reset channel
5945 * should just be killed off, irrespecitve of whether
5946 * we are blocked on ATIO resources. Write a routine
5947 * to compact the tqinfifo appropriately.
5949 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5950 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5955 * Reset the bus if we are initiating this reset
5957 sblkctl = ahc_inb(ahc, SBLKCTL);
5959 if ((ahc->features & AHC_TWIN) != 0
5960 && ((sblkctl & SELBUSB) != 0))
5962 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5963 if (cur_channel != channel) {
5964 /* Case 1: Command for another bus is active
5965 * Stealthily reset the other bus without
5966 * upsetting the current bus.
5968 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5969 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5970 #ifdef AHC_TARGET_MODE
5972 * Bus resets clear ENSELI, so we cannot
5973 * defer re-enabling bus reset interrupts
5974 * if we are in target mode.
5976 if ((ahc->flags & AHC_TARGETROLE) != 0)
5977 simode1 |= ENSCSIRST;
5979 ahc_outb(ahc, SIMODE1, simode1);
5981 ahc_reset_current_bus(ahc);
5982 ahc_clear_intstat(ahc);
5983 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5984 ahc_outb(ahc, SBLKCTL, sblkctl);
5985 restart_needed = FALSE;
5987 /* Case 2: A command from this bus is active or we're idle */
5988 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5989 #ifdef AHC_TARGET_MODE
5991 * Bus resets clear ENSELI, so we cannot
5992 * defer re-enabling bus reset interrupts
5993 * if we are in target mode.
5995 if ((ahc->flags & AHC_TARGETROLE) != 0)
5996 simode1 |= ENSCSIRST;
5998 ahc_outb(ahc, SIMODE1, simode1);
6000 ahc_reset_current_bus(ahc);
6001 ahc_clear_intstat(ahc);
6002 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6003 restart_needed = TRUE;
6007 * Clean up all the state information for the
6008 * pending transactions on this bus.
6010 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6011 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6012 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6014 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6016 #ifdef AHC_TARGET_MODE
6018 * Send an immediate notify ccb to all target more peripheral
6019 * drivers affected by this action.
6021 for (target = 0; target <= max_scsiid; target++) {
6022 struct ahc_tmode_tstate* tstate;
6025 tstate = ahc->enabled_targets[target];
6028 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6029 struct ahc_tmode_lstate* lstate;
6031 lstate = tstate->enabled_luns[lun];
6035 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6036 EVENT_TYPE_BUS_RESET, /*arg*/0);
6037 ahc_send_lstate_events(ahc, lstate);
6041 /* Notify the XPT that a bus reset occurred */
6042 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6043 CAM_LUN_WILDCARD, AC_BUS_RESET);
6046 * Revert to async/narrow transfers until we renegotiate.
6048 for (target = 0; target <= max_scsiid; target++) {
6050 if (ahc->enabled_targets[target] == NULL)
6052 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6053 struct ahc_devinfo devinfo;
6055 ahc_compile_devinfo(&devinfo, target, initiator,
6057 channel, ROLE_UNKNOWN);
6058 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6059 AHC_TRANS_CUR, /*paused*/TRUE);
6060 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6061 /*period*/0, /*offset*/0,
6062 /*ppr_options*/0, AHC_TRANS_CUR,
6075 /***************************** Residual Processing ****************************/
6077 * Calculate the residual for a just completed SCB.
6080 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6082 struct hardware_scb *hscb;
6083 struct status_pkt *spkt;
6085 uint32_t resid_sgptr;
6091 * SG_RESID_VALID clear in sgptr.
6092 * 2) Transferless command
6093 * 3) Never performed any transfers.
6094 * sgptr has SG_FULL_RESID set.
6095 * 4) No residual but target did not
6096 * save data pointers after the
6097 * last transfer, so sgptr was
6099 * 5) We have a partial residual.
6100 * Use residual_sgptr to determine
6105 sgptr = ahc_le32toh(hscb->sgptr);
6106 if ((sgptr & SG_RESID_VALID) == 0)
6109 sgptr &= ~SG_RESID_VALID;
6111 if ((sgptr & SG_LIST_NULL) != 0)
6115 spkt = &hscb->shared_data.status;
6116 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6117 if ((sgptr & SG_FULL_RESID) != 0) {
6119 resid = ahc_get_transfer_length(scb);
6120 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6123 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6124 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6126 struct ahc_dma_seg *sg;
6129 * Remainder of the SG where the transfer
6132 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6133 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6135 /* The residual sg_ptr always points to the next sg */
6139 * Add up the contents of all residual
6140 * SG segments that are after the SG where
6141 * the transfer stopped.
6143 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6145 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6148 if ((scb->flags & SCB_SENSE) == 0)
6149 ahc_set_residual(scb, resid);
6151 ahc_set_sense_residual(scb, resid);
6154 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6155 ahc_print_path(ahc, scb);
6156 printf("Handled %sResidual of %d bytes\n",
6157 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6162 /******************************* Target Mode **********************************/
6163 #ifdef AHC_TARGET_MODE
6165 * Add a target mode event to this lun's queue
6168 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6169 u_int initiator_id, u_int event_type, u_int event_arg)
6171 struct ahc_tmode_event *event;
6174 xpt_freeze_devq(lstate->path, /*count*/1);
6175 if (lstate->event_w_idx >= lstate->event_r_idx)
6176 pending = lstate->event_w_idx - lstate->event_r_idx;
6178 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6179 - (lstate->event_r_idx - lstate->event_w_idx);
6181 if (event_type == EVENT_TYPE_BUS_RESET
6182 || event_type == MSG_BUS_DEV_RESET) {
6184 * Any earlier events are irrelevant, so reset our buffer.
6185 * This has the effect of allowing us to deal with reset
6186 * floods (an external device holding down the reset line)
6187 * without losing the event that is really interesting.
6189 lstate->event_r_idx = 0;
6190 lstate->event_w_idx = 0;
6191 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6194 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6195 xpt_print_path(lstate->path);
6196 printf("immediate event %x:%x lost\n",
6197 lstate->event_buffer[lstate->event_r_idx].event_type,
6198 lstate->event_buffer[lstate->event_r_idx].event_arg);
6199 lstate->event_r_idx++;
6200 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6201 lstate->event_r_idx = 0;
6202 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6205 event = &lstate->event_buffer[lstate->event_w_idx];
6206 event->initiator_id = initiator_id;
6207 event->event_type = event_type;
6208 event->event_arg = event_arg;
6209 lstate->event_w_idx++;
6210 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6211 lstate->event_w_idx = 0;
6215 * Send any target mode events queued up waiting
6216 * for immediate notify resources.
6219 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6221 struct ccb_hdr *ccbh;
6222 struct ccb_immed_notify *inot;
6224 while (lstate->event_r_idx != lstate->event_w_idx
6225 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6226 struct ahc_tmode_event *event;
6228 event = &lstate->event_buffer[lstate->event_r_idx];
6229 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6230 inot = (struct ccb_immed_notify *)ccbh;
6231 switch (event->event_type) {
6232 case EVENT_TYPE_BUS_RESET:
6233 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6236 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6237 inot->message_args[0] = event->event_type;
6238 inot->message_args[1] = event->event_arg;
6241 inot->initiator_id = event->initiator_id;
6242 inot->sense_len = 0;
6243 xpt_done((union ccb *)inot);
6244 lstate->event_r_idx++;
6245 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6246 lstate->event_r_idx = 0;
6251 /******************** Sequencer Program Patching/Download *********************/
6255 ahc_dumpseq(struct ahc_softc* ahc)
6259 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6260 ahc_outb(ahc, SEQADDR0, 0);
6261 ahc_outb(ahc, SEQADDR1, 0);
6262 for (i = 0; i < ahc->instruction_ram_size; i++) {
6263 uint8_t ins_bytes[4];
6265 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6266 printf("0x%08x\n", ins_bytes[0] << 24
6267 | ins_bytes[1] << 16
6275 ahc_loadseq(struct ahc_softc *ahc)
6277 struct cs cs_table[num_critical_sections];
6278 u_int begin_set[num_critical_sections];
6279 u_int end_set[num_critical_sections];
6280 struct patch *cur_patch;
6285 u_int sg_prefetch_cnt;
6287 uint8_t download_consts[7];
6290 * Start out with 0 critical sections
6291 * that apply to this firmware load.
6295 memset(begin_set, 0, sizeof(begin_set));
6296 memset(end_set, 0, sizeof(end_set));
6298 /* Setup downloadable constant table */
6299 download_consts[QOUTFIFO_OFFSET] = 0;
6300 if (ahc->targetcmds != NULL)
6301 download_consts[QOUTFIFO_OFFSET] += 32;
6302 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6303 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6304 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6305 sg_prefetch_cnt = ahc->pci_cachesize;
6306 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6307 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6308 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6309 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6310 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6312 cur_patch = patches;
6315 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6316 ahc_outb(ahc, SEQADDR0, 0);
6317 ahc_outb(ahc, SEQADDR1, 0);
6319 for (i = 0; i < sizeof(seqprog)/4; i++) {
6320 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6322 * Don't download this instruction as it
6323 * is in a patch that was removed.
6328 if (downloaded == ahc->instruction_ram_size) {
6330 * We're about to exceed the instruction
6331 * storage capacity for this chip. Fail
6334 printf("\n%s: Program too large for instruction memory "
6335 "size of %d!\n", ahc_name(ahc),
6336 ahc->instruction_ram_size);
6341 * Move through the CS table until we find a CS
6342 * that might apply to this instruction.
6344 for (; cur_cs < num_critical_sections; cur_cs++) {
6345 if (critical_sections[cur_cs].end <= i) {
6346 if (begin_set[cs_count] == TRUE
6347 && end_set[cs_count] == FALSE) {
6348 cs_table[cs_count].end = downloaded;
6349 end_set[cs_count] = TRUE;
6354 if (critical_sections[cur_cs].begin <= i
6355 && begin_set[cs_count] == FALSE) {
6356 cs_table[cs_count].begin = downloaded;
6357 begin_set[cs_count] = TRUE;
6361 ahc_download_instr(ahc, i, download_consts);
6365 ahc->num_critical_sections = cs_count;
6366 if (cs_count != 0) {
6368 cs_count *= sizeof(struct cs);
6369 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6370 if (ahc->critical_sections == NULL)
6371 panic("ahc_loadseq: Could not malloc");
6372 memcpy(ahc->critical_sections, cs_table, cs_count);
6374 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6377 printf(" %d instructions downloaded\n", downloaded);
6378 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6379 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6385 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6386 u_int start_instr, u_int *skip_addr)
6388 struct patch *cur_patch;
6389 struct patch *last_patch;
6392 num_patches = ARRAY_SIZE(patches);
6393 last_patch = &patches[num_patches];
6394 cur_patch = *start_patch;
6396 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6398 if (cur_patch->patch_func(ahc) == 0) {
6400 /* Start rejecting code */
6401 *skip_addr = start_instr + cur_patch->skip_instr;
6402 cur_patch += cur_patch->skip_patch;
6404 /* Accepted this patch. Advance to the next
6405 * one and wait for our intruction pointer to
6412 *start_patch = cur_patch;
6413 if (start_instr < *skip_addr)
6414 /* Still skipping */
6421 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6423 union ins_formats instr;
6424 struct ins_format1 *fmt1_ins;
6425 struct ins_format3 *fmt3_ins;
6429 * The firmware is always compiled into a little endian format.
6431 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6433 fmt1_ins = &instr.format1;
6436 /* Pull the opcode */
6437 opcode = instr.format1.opcode;
6448 struct patch *cur_patch;
6454 fmt3_ins = &instr.format3;
6456 address = fmt3_ins->address;
6457 cur_patch = patches;
6460 for (i = 0; i < address;) {
6462 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6464 if (skip_addr > i) {
6467 end_addr = min(address, skip_addr);
6468 address_offset += end_addr - i;
6474 address -= address_offset;
6475 fmt3_ins->address = address;
6484 if (fmt1_ins->parity != 0) {
6485 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6487 fmt1_ins->parity = 0;
6488 if ((ahc->features & AHC_CMD_CHAN) == 0
6489 && opcode == AIC_OP_BMOV) {
6491 * Block move was added at the same time
6492 * as the command channel. Verify that
6493 * this is only a move of a single element
6494 * and convert the BMOV to a MOV
6495 * (AND with an immediate of FF).
6497 if (fmt1_ins->immediate != 1)
6498 panic("%s: BMOV not supported\n",
6500 fmt1_ins->opcode = AIC_OP_AND;
6501 fmt1_ins->immediate = 0xff;
6505 if ((ahc->features & AHC_ULTRA2) != 0) {
6508 /* Calculate odd parity for the instruction */
6509 for (i = 0, count = 0; i < 31; i++) {
6513 if ((instr.integer & mask) != 0)
6516 if ((count & 0x01) == 0)
6517 instr.format1.parity = 1;
6519 /* Compress the instruction for older sequencers */
6520 if (fmt3_ins != NULL) {
6523 | (fmt3_ins->source << 8)
6524 | (fmt3_ins->address << 16)
6525 | (fmt3_ins->opcode << 25);
6529 | (fmt1_ins->source << 8)
6530 | (fmt1_ins->destination << 16)
6531 | (fmt1_ins->ret << 24)
6532 | (fmt1_ins->opcode << 25);
6535 /* The sequencer is a little endian cpu */
6536 instr.integer = ahc_htole32(instr.integer);
6537 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6540 panic("Unknown opcode encountered in seq program");
6546 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6547 const char *name, u_int address, u_int value,
6548 u_int *cur_column, u_int wrap_point)
6553 if (cur_column != NULL && *cur_column >= wrap_point) {
6557 printed = printf("%s[0x%x]", name, value);
6558 if (table == NULL) {
6559 printed += printf(" ");
6560 *cur_column += printed;
6564 while (printed_mask != 0xFF) {
6567 for (entry = 0; entry < num_entries; entry++) {
6568 if (((value & table[entry].mask)
6569 != table[entry].value)
6570 || ((printed_mask & table[entry].mask)
6571 == table[entry].mask))
6574 printed += printf("%s%s",
6575 printed_mask == 0 ? ":(" : "|",
6577 printed_mask |= table[entry].mask;
6581 if (entry >= num_entries)
6584 if (printed_mask != 0)
6585 printed += printf(") ");
6587 printed += printf(" ");
6588 if (cur_column != NULL)
6589 *cur_column += printed;
6594 ahc_dump_card_state(struct ahc_softc *ahc)
6597 struct scb_tailq *untagged_q;
6608 uint8_t saved_scbptr;
6610 if (ahc_is_paused(ahc)) {
6617 saved_scbptr = ahc_inb(ahc, SCBPTR);
6618 last_phase = ahc_inb(ahc, LASTPHASE);
6619 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6620 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6621 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6622 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6624 printf("Card was paused\n");
6625 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6626 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6627 ahc_inb(ahc, ARG_2));
6628 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6629 ahc_inb(ahc, SCBPTR));
6631 if ((ahc->features & AHC_DT) != 0)
6632 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6633 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6634 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6635 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6636 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6637 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6638 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6639 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6640 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6641 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6642 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6643 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6644 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6645 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6646 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6647 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6648 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6649 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6650 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6654 for (i = 0; i < STACK_SIZE; i++)
6655 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6656 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6657 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6658 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6660 printf("QINFIFO entries: ");
6661 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6662 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6663 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6665 qinpos = ahc_inb(ahc, QINPOS);
6666 qintail = ahc->qinfifonext;
6667 while (qinpos != qintail) {
6668 printf("%d ", ahc->qinfifo[qinpos]);
6673 printf("Waiting Queue entries: ");
6674 scb_index = ahc_inb(ahc, WAITING_SCBH);
6676 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6677 ahc_outb(ahc, SCBPTR, scb_index);
6678 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6679 scb_index = ahc_inb(ahc, SCB_NEXT);
6683 printf("Disconnected Queue entries: ");
6684 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6686 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6687 ahc_outb(ahc, SCBPTR, scb_index);
6688 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6689 scb_index = ahc_inb(ahc, SCB_NEXT);
6693 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6694 printf("QOUTFIFO entries: ");
6695 qoutpos = ahc->qoutfifonext;
6697 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6698 printf("%d ", ahc->qoutfifo[qoutpos]);
6703 printf("Sequencer Free SCB List: ");
6704 scb_index = ahc_inb(ahc, FREE_SCBH);
6706 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6707 ahc_outb(ahc, SCBPTR, scb_index);
6708 printf("%d ", scb_index);
6709 scb_index = ahc_inb(ahc, SCB_NEXT);
6713 printf("Sequencer SCB Info: ");
6714 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6715 ahc_outb(ahc, SCBPTR, i);
6716 cur_col = printf("\n%3d ", i);
6718 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6719 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6720 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6721 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6725 printf("Pending list: ");
6727 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6730 cur_col = printf("\n%3d ", scb->hscb->tag);
6731 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6732 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6733 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6734 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6735 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6737 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6739 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6745 printf("Kernel Free SCB list: ");
6747 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6750 printf("%d ", scb->hscb->tag);
6754 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6755 for (target = 0; target <= maxtarget; target++) {
6756 untagged_q = &ahc->untagged_queues[target];
6757 if (TAILQ_FIRST(untagged_q) == NULL)
6759 printf("Untagged Q(%d): ", target);
6761 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6764 printf("%d ", scb->hscb->tag);
6769 ahc_platform_dump_card_state(ahc);
6770 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6771 ahc_outb(ahc, SCBPTR, saved_scbptr);
6776 /************************* Target Mode ****************************************/
6777 #ifdef AHC_TARGET_MODE
6779 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6780 struct ahc_tmode_tstate **tstate,
6781 struct ahc_tmode_lstate **lstate,
6782 int notfound_failure)
6785 if ((ahc->features & AHC_TARGETMODE) == 0)
6786 return (CAM_REQ_INVALID);
6789 * Handle the 'black hole' device that sucks up
6790 * requests to unattached luns on enabled targets.
6792 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6793 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6795 *lstate = ahc->black_hole;
6799 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
6800 if (ccb->ccb_h.target_id >= max_id)
6801 return (CAM_TID_INVALID);
6803 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6804 return (CAM_LUN_INVALID);
6806 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6808 if (*tstate != NULL)
6810 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6813 if (notfound_failure != 0 && *lstate == NULL)
6814 return (CAM_PATH_INVALID);
6816 return (CAM_REQ_CMP);
6820 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6822 struct ahc_tmode_tstate *tstate;
6823 struct ahc_tmode_lstate *lstate;
6824 struct ccb_en_lun *cel;
6834 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6835 /*notfound_failure*/FALSE);
6837 if (status != CAM_REQ_CMP) {
6838 ccb->ccb_h.status = status;
6842 if (cam_sim_bus(sim) == 0)
6843 our_id = ahc->our_id;
6845 our_id = ahc->our_id_b;
6847 if (ccb->ccb_h.target_id != our_id) {
6849 * our_id represents our initiator ID, or
6850 * the ID of the first target to have an
6851 * enabled lun in target mode. There are
6852 * two cases that may preclude enabling a
6853 * target id other than our_id.
6855 * o our_id is for an active initiator role.
6856 * Since the hardware does not support
6857 * reselections to the initiator role at
6858 * anything other than our_id, and our_id
6859 * is used by the hardware to indicate the
6860 * ID to use for both select-out and
6861 * reselect-out operations, the only target
6862 * ID we can support in this mode is our_id.
6864 * o The MULTARGID feature is not available and
6865 * a previous target mode ID has been enabled.
6867 if ((ahc->features & AHC_MULTIROLE) != 0) {
6869 if ((ahc->features & AHC_MULTI_TID) != 0
6870 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6872 * Only allow additional targets if
6873 * the initiator role is disabled.
6874 * The hardware cannot handle a re-select-in
6875 * on the initiator id during a re-select-out
6876 * on a different target id.
6878 status = CAM_TID_INVALID;
6879 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6880 || ahc->enabled_luns > 0) {
6882 * Only allow our target id to change
6883 * if the initiator role is not configured
6884 * and there are no enabled luns which
6885 * are attached to the currently registered
6888 status = CAM_TID_INVALID;
6890 } else if ((ahc->features & AHC_MULTI_TID) == 0
6891 && ahc->enabled_luns > 0) {
6893 status = CAM_TID_INVALID;
6897 if (status != CAM_REQ_CMP) {
6898 ccb->ccb_h.status = status;
6903 * We now have an id that is valid.
6904 * If we aren't in target mode, switch modes.
6906 if ((ahc->flags & AHC_TARGETROLE) == 0
6907 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6909 ahc_flag saved_flags;
6911 printf("Configuring Target Mode\n");
6913 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6914 ccb->ccb_h.status = CAM_BUSY;
6915 ahc_unlock(ahc, &s);
6918 saved_flags = ahc->flags;
6919 ahc->flags |= AHC_TARGETROLE;
6920 if ((ahc->features & AHC_MULTIROLE) == 0)
6921 ahc->flags &= ~AHC_INITIATORROLE;
6923 error = ahc_loadseq(ahc);
6926 * Restore original configuration and notify
6927 * the caller that we cannot support target mode.
6928 * Since the adapter started out in this
6929 * configuration, the firmware load will succeed,
6930 * so there is no point in checking ahc_loadseq's
6933 ahc->flags = saved_flags;
6934 (void)ahc_loadseq(ahc);
6936 ahc_unlock(ahc, &s);
6937 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6941 ahc_unlock(ahc, &s);
6944 target = ccb->ccb_h.target_id;
6945 lun = ccb->ccb_h.target_lun;
6946 channel = SIM_CHANNEL(ahc, sim);
6947 target_mask = 0x01 << target;
6951 if (cel->enable != 0) {
6954 /* Are we already enabled?? */
6955 if (lstate != NULL) {
6956 xpt_print_path(ccb->ccb_h.path);
6957 printf("Lun already enabled\n");
6958 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6962 if (cel->grp6_len != 0
6963 || cel->grp7_len != 0) {
6965 * Don't (yet?) support vendor
6966 * specific commands.
6968 ccb->ccb_h.status = CAM_REQ_INVALID;
6969 printf("Non-zero Group Codes\n");
6975 * Setup our data structures.
6977 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6978 tstate = ahc_alloc_tstate(ahc, target, channel);
6979 if (tstate == NULL) {
6980 xpt_print_path(ccb->ccb_h.path);
6981 printf("Couldn't allocate tstate\n");
6982 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6986 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6987 if (lstate == NULL) {
6988 xpt_print_path(ccb->ccb_h.path);
6989 printf("Couldn't allocate lstate\n");
6990 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6993 memset(lstate, 0, sizeof(*lstate));
6994 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6995 xpt_path_path_id(ccb->ccb_h.path),
6996 xpt_path_target_id(ccb->ccb_h.path),
6997 xpt_path_lun_id(ccb->ccb_h.path));
6998 if (status != CAM_REQ_CMP) {
6999 free(lstate, M_DEVBUF);
7000 xpt_print_path(ccb->ccb_h.path);
7001 printf("Couldn't allocate path\n");
7002 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7005 SLIST_INIT(&lstate->accept_tios);
7006 SLIST_INIT(&lstate->immed_notifies);
7009 if (target != CAM_TARGET_WILDCARD) {
7010 tstate->enabled_luns[lun] = lstate;
7011 ahc->enabled_luns++;
7013 if ((ahc->features & AHC_MULTI_TID) != 0) {
7016 targid_mask = ahc_inb(ahc, TARGID)
7017 | (ahc_inb(ahc, TARGID + 1) << 8);
7019 targid_mask |= target_mask;
7020 ahc_outb(ahc, TARGID, targid_mask);
7021 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7023 ahc_update_scsiid(ahc, targid_mask);
7028 channel = SIM_CHANNEL(ahc, sim);
7029 our_id = SIM_SCSI_ID(ahc, sim);
7032 * This can only happen if selections
7035 if (target != our_id) {
7040 sblkctl = ahc_inb(ahc, SBLKCTL);
7041 cur_channel = (sblkctl & SELBUSB)
7043 if ((ahc->features & AHC_TWIN) == 0)
7045 swap = cur_channel != channel;
7047 ahc->our_id = target;
7049 ahc->our_id_b = target;
7052 ahc_outb(ahc, SBLKCTL,
7055 ahc_outb(ahc, SCSIID, target);
7058 ahc_outb(ahc, SBLKCTL, sblkctl);
7062 ahc->black_hole = lstate;
7063 /* Allow select-in operations */
7064 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7065 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7067 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7068 scsiseq = ahc_inb(ahc, SCSISEQ);
7070 ahc_outb(ahc, SCSISEQ, scsiseq);
7073 ahc_unlock(ahc, &s);
7074 ccb->ccb_h.status = CAM_REQ_CMP;
7075 xpt_print_path(ccb->ccb_h.path);
7076 printf("Lun now enabled for target mode\n");
7081 if (lstate == NULL) {
7082 ccb->ccb_h.status = CAM_LUN_INVALID;
7088 ccb->ccb_h.status = CAM_REQ_CMP;
7089 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7090 struct ccb_hdr *ccbh;
7092 ccbh = &scb->io_ctx->ccb_h;
7093 if (ccbh->func_code == XPT_CONT_TARGET_IO
7094 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7095 printf("CTIO pending\n");
7096 ccb->ccb_h.status = CAM_REQ_INVALID;
7097 ahc_unlock(ahc, &s);
7102 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7103 printf("ATIOs pending\n");
7104 ccb->ccb_h.status = CAM_REQ_INVALID;
7107 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7108 printf("INOTs pending\n");
7109 ccb->ccb_h.status = CAM_REQ_INVALID;
7112 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7113 ahc_unlock(ahc, &s);
7117 xpt_print_path(ccb->ccb_h.path);
7118 printf("Target mode disabled\n");
7119 xpt_free_path(lstate->path);
7120 free(lstate, M_DEVBUF);
7123 /* Can we clean up the target too? */
7124 if (target != CAM_TARGET_WILDCARD) {
7125 tstate->enabled_luns[lun] = NULL;
7126 ahc->enabled_luns--;
7127 for (empty = 1, i = 0; i < 8; i++)
7128 if (tstate->enabled_luns[i] != NULL) {
7134 ahc_free_tstate(ahc, target, channel,
7136 if (ahc->features & AHC_MULTI_TID) {
7139 targid_mask = ahc_inb(ahc, TARGID)
7140 | (ahc_inb(ahc, TARGID + 1)
7143 targid_mask &= ~target_mask;
7144 ahc_outb(ahc, TARGID, targid_mask);
7145 ahc_outb(ahc, TARGID+1,
7146 (targid_mask >> 8));
7147 ahc_update_scsiid(ahc, targid_mask);
7152 ahc->black_hole = NULL;
7155 * We can't allow selections without
7156 * our black hole device.
7160 if (ahc->enabled_luns == 0) {
7161 /* Disallow select-in */
7164 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7166 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7167 scsiseq = ahc_inb(ahc, SCSISEQ);
7169 ahc_outb(ahc, SCSISEQ, scsiseq);
7171 if ((ahc->features & AHC_MULTIROLE) == 0) {
7172 printf("Configuring Initiator Mode\n");
7173 ahc->flags &= ~AHC_TARGETROLE;
7174 ahc->flags |= AHC_INITIATORROLE;
7176 * Returning to a configuration that
7177 * fit previously will always succeed.
7179 (void)ahc_loadseq(ahc);
7182 * Unpaused. The extra unpause
7183 * that follows is harmless.
7188 ahc_unlock(ahc, &s);
7193 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7198 if ((ahc->features & AHC_MULTI_TID) == 0)
7199 panic("ahc_update_scsiid called on non-multitid unit\n");
7202 * Since we will rely on the TARGID mask
7203 * for selection enables, ensure that OID
7204 * in SCSIID is not set to some other ID
7205 * that we don't want to allow selections on.
7207 if ((ahc->features & AHC_ULTRA2) != 0)
7208 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7210 scsiid = ahc_inb(ahc, SCSIID);
7211 scsiid_mask = 0x1 << (scsiid & OID);
7212 if ((targid_mask & scsiid_mask) == 0) {
7215 /* ffs counts from 1 */
7216 our_id = ffs(targid_mask);
7218 our_id = ahc->our_id;
7224 if ((ahc->features & AHC_ULTRA2) != 0)
7225 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7227 ahc_outb(ahc, SCSIID, scsiid);
7231 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7233 struct target_cmd *cmd;
7236 * If the card supports auto-access pause,
7237 * we can access the card directly regardless
7238 * of whether it is paused or not.
7240 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7243 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7244 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7247 * Only advance through the queue if we
7248 * have the resources to process the command.
7250 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7254 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7255 ahc->shared_data_dmamap,
7256 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7257 sizeof(struct target_cmd),
7258 BUS_DMASYNC_PREREAD);
7259 ahc->tqinfifonext++;
7262 * Lazily update our position in the target mode incoming
7263 * command queue as seen by the sequencer.
7265 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7266 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7269 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7270 hs_mailbox &= ~HOST_TQINPOS;
7271 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7272 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7276 ahc_outb(ahc, KERNEL_TQINPOS,
7277 ahc->tqinfifonext & HOST_TQINPOS);
7286 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7288 struct ahc_tmode_tstate *tstate;
7289 struct ahc_tmode_lstate *lstate;
7290 struct ccb_accept_tio *atio;
7296 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7297 target = SCSIID_OUR_ID(cmd->scsiid);
7298 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7301 tstate = ahc->enabled_targets[target];
7304 lstate = tstate->enabled_luns[lun];
7307 * Commands for disabled luns go to the black hole driver.
7310 lstate = ahc->black_hole;
7312 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7314 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7316 * Wait for more ATIOs from the peripheral driver for this lun.
7319 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7322 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7324 printf("Incoming command from %d for %d:%d%s\n",
7325 initiator, target, lun,
7326 lstate == ahc->black_hole ? "(Black Holed)" : "");
7328 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7330 if (lstate == ahc->black_hole) {
7331 /* Fill in the wildcards */
7332 atio->ccb_h.target_id = target;
7333 atio->ccb_h.target_lun = lun;
7337 * Package it up and send it off to
7338 * whomever has this lun enabled.
7340 atio->sense_len = 0;
7341 atio->init_id = initiator;
7342 if (byte[0] != 0xFF) {
7343 /* Tag was included */
7344 atio->tag_action = *byte++;
7345 atio->tag_id = *byte++;
7346 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7348 atio->ccb_h.flags = 0;
7352 /* Okay. Now determine the cdb size based on the command code */
7353 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7369 /* Only copy the opcode. */
7371 printf("Reserved or VU command code type encountered\n");
7375 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7377 atio->ccb_h.status |= CAM_CDB_RECVD;
7379 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7381 * We weren't allowed to disconnect.
7382 * We're hanging on the bus until a
7383 * continue target I/O comes in response
7384 * to this accept tio.
7387 printf("Received Immediate Command %d:%d:%d - %p\n",
7388 initiator, target, lun, ahc->pending_device);
7390 ahc->pending_device = lstate;
7391 ahc_freeze_ccb((union ccb *)atio);
7392 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7394 xpt_done((union ccb*)atio);
projects / linux-2.6 / blob