git.oblomov.eu Git - linux-2.6/blob - drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why is a timer used to detect insert events?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  *
  34  * So we use the timer to check the status manually.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/mm.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <linux/mmc/host.h>
  45 #include <asm/io.h>
  46 #include <asm/mach-au1x00/au1000.h>
  47 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  48 #include <asm/mach-au1x00/au1100_mmc.h>
  49 #include <asm/scatterlist.h>
  50
  51 #include <au1xxx.h>
  52 #include "au1xmmc.h"
  53
  54 #define DRIVER_NAME "au1xxx-mmc"
  55
  56 /* Set this to enable special debugging macros */
  57
  58 #ifdef DEBUG
  59 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
  60 #else
  61 #define DBG(fmt, idx, args...)
  62 #endif
  63
  64 const struct {
  65         u32 iobase;
  66         u32 tx_devid, rx_devid;
  67         u16 bcsrpwr;
  68         u16 bcsrstatus;
  69         u16 wpstatus;
  70 } au1xmmc_card_table[] = {
  71         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
  72           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
  73 #ifndef CONFIG_MIPS_DB1200
  74         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
  75           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
  76 #endif
  77 };
  78
  79 #define AU1XMMC_CONTROLLER_COUNT \
  80         (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
  81
  82 /* This array stores pointers for the hosts (used by the IRQ handler) */
  83 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
  84 static int dma = 1;
  85
  86 #ifdef MODULE
  87 module_param(dma, bool, 0);
  88 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
  89 #endif
  90
  91 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
  92 {
  93         u32 val = au_readl(HOST_CONFIG(host));
  94         val |= mask;
  95         au_writel(val, HOST_CONFIG(host));
  96         au_sync();
  97 }
  98
  99 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 100 {
 101         u32 val = au_readl(HOST_CONFIG2(host));
 102
 103         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 104         au_sync_delay(1);
 105
 106         /* SEND_STOP will turn off clock control - this re-enables it */
 107         val &= ~SD_CONFIG2_DF;
 108
 109         au_writel(val, HOST_CONFIG2(host));
 110         au_sync();
 111 }
 112
 113 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 114 {
 115         u32 val = au_readl(HOST_CONFIG(host));
 116         val &= ~mask;
 117         au_writel(val, HOST_CONFIG(host));
 118         au_sync();
 119 }
 120
 121 static inline void SEND_STOP(struct au1xmmc_host *host)
 122 {
 123
 124         /* We know the value of CONFIG2, so avoid a read we don't need */
 125         u32 mask = SD_CONFIG2_EN;
 126
 127         WARN_ON(host->status != HOST_S_DATA);
 128         host->status = HOST_S_STOP;
 129
 130         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
 131         au_sync();
 132
 133         /* Send the stop commmand */
 134         au_writel(STOP_CMD, HOST_CMD(host));
 135 }
 136
 137 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 138 {
 139
 140         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
 141
 142         bcsr->board &= ~val;
 143         if (state) bcsr->board |= val;
 144
 145         au_sync_delay(1);
 146 }
 147
 148 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
 149 {
 150         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
 151                 ? 1 : 0;
 152 }
 153
 154 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 155 {
 156         struct au1xmmc_host *host = mmc_priv(mmc);
 157         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
 158                 ? 1 : 0;
 159 }
 160
 161 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 162 {
 163
 164         struct mmc_request *mrq = host->mrq;
 165
 166         host->mrq = NULL;
 167         host->flags &= HOST_F_ACTIVE;
 168
 169         host->dma.len = 0;
 170         host->dma.dir = 0;
 171
 172         host->pio.index  = 0;
 173         host->pio.offset = 0;
 174         host->pio.len = 0;
 175
 176         host->status = HOST_S_IDLE;
 177
 178         bcsr->disk_leds |= (1 << 8);
 179
 180         mmc_request_done(host->mmc, mrq);
 181 }
 182
 183 static void au1xmmc_tasklet_finish(unsigned long param)
 184 {
 185         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 186         au1xmmc_finish_request(host);
 187 }
 188
 189 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 190                                 struct mmc_command *cmd, unsigned int flags)
 191 {
 192         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 193
 194         switch (mmc_resp_type(cmd)) {
 195         case MMC_RSP_NONE:
 196                 break;
 197         case MMC_RSP_R1:
 198                 mmccmd |= SD_CMD_RT_1;
 199                 break;
 200         case MMC_RSP_R1B:
 201                 mmccmd |= SD_CMD_RT_1B;
 202                 break;
 203         case MMC_RSP_R2:
 204                 mmccmd |= SD_CMD_RT_2;
 205                 break;
 206         case MMC_RSP_R3:
 207                 mmccmd |= SD_CMD_RT_3;
 208                 break;
 209         default:
 210                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 211                         mmc_resp_type(cmd));
 212                 return MMC_ERR_INVALID;
 213         }
 214
 215         if (flags & MMC_DATA_READ) {
 216                 if (flags & MMC_DATA_MULTI)
 217                         mmccmd |= SD_CMD_CT_4;
 218                 else
 219                         mmccmd |= SD_CMD_CT_2;
 220         } else if (flags & MMC_DATA_WRITE) {
 221                 if (flags & MMC_DATA_MULTI)
 222                         mmccmd |= SD_CMD_CT_3;
 223                 else
 224                         mmccmd |= SD_CMD_CT_1;
 225         }
 226
 227         au_writel(cmd->arg, HOST_CMDARG(host));
 228         au_sync();
 229
 230         if (wait)
 231                 IRQ_OFF(host, SD_CONFIG_CR);
 232
 233         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 234         au_sync();
 235
 236         /* Wait for the command to go on the line */
 237
 238         while(1) {
 239                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
 240                         break;
 241         }
 242
 243         /* Wait for the command to come back */
 244
 245         if (wait) {
 246                 u32 status = au_readl(HOST_STATUS(host));
 247
 248                 while(!(status & SD_STATUS_CR))
 249                         status = au_readl(HOST_STATUS(host));
 250
 251                 /* Clear the CR status */
 252                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 253
 254                 IRQ_ON(host, SD_CONFIG_CR);
 255         }
 256
 257         return MMC_ERR_NONE;
 258 }
 259
 260 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 261 {
 262
 263         struct mmc_request *mrq = host->mrq;
 264         struct mmc_data *data;
 265         u32 crc;
 266
 267         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
 268
 269         if (host->mrq == NULL)
 270                 return;
 271
 272         data = mrq->cmd->data;
 273
 274         if (status == 0)
 275                 status = au_readl(HOST_STATUS(host));
 276
 277         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 278
 279         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 280                 status = au_readl(HOST_STATUS(host));
 281
 282         data->error = MMC_ERR_NONE;
 283         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 284
 285         /* Process any errors */
 286
 287         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 288         if (host->flags & HOST_F_XMIT)
 289                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 290
 291         if (crc)
 292                 data->error = MMC_ERR_BADCRC;
 293
 294         /* Clear the CRC bits */
 295         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 296
 297         data->bytes_xfered = 0;
 298
 299         if (data->error == MMC_ERR_NONE) {
 300                 if (host->flags & HOST_F_DMA) {
 301                         u32 chan = DMA_CHANNEL(host);
 302
 303                         chan_tab_t *c = *((chan_tab_t **) chan);
 304                         au1x_dma_chan_t *cp = c->chan_ptr;
 305                         data->bytes_xfered = cp->ddma_bytecnt;
 306                 }
 307                 else
 308                         data->bytes_xfered =
 309                                 (data->blocks * data->blksz) -
 310                                 host->pio.len;
 311         }
 312
 313         au1xmmc_finish_request(host);
 314 }
 315
 316 static void au1xmmc_tasklet_data(unsigned long param)
 317 {
 318         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 319
 320         u32 status = au_readl(HOST_STATUS(host));
 321         au1xmmc_data_complete(host, status);
 322 }
 323
 324 #define AU1XMMC_MAX_TRANSFER 8
 325
 326 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 327 {
 328
 329         struct mmc_data *data = 0;
 330         int sg_len, max, count = 0;
 331         unsigned char *sg_ptr;
 332         u32 status = 0;
 333         struct scatterlist *sg;
 334
 335         data = host->mrq->data;
 336
 337         if (!(host->flags & HOST_F_XMIT))
 338                 return;
 339
 340         /* This is the pointer to the data buffer */
 341         sg = &data->sg[host->pio.index];
 342         sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
 343
 344         /* This is the space left inside the buffer */
 345         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 346
 347         /* Check to if we need less then the size of the sg_buffer */
 348
 349         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 350         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
 351
 352         for(count = 0; count < max; count++ ) {
 353                 unsigned char val;
 354
 355                 status = au_readl(HOST_STATUS(host));
 356
 357                 if (!(status & SD_STATUS_TH))
 358                         break;
 359
 360                 val = *sg_ptr++;
 361
 362                 au_writel((unsigned long) val, HOST_TXPORT(host));
 363                 au_sync();
 364         }
 365
 366         host->pio.len -= count;
 367         host->pio.offset += count;
 368
 369         if (count == sg_len) {
 370                 host->pio.index++;
 371                 host->pio.offset = 0;
 372         }
 373
 374         if (host->pio.len == 0) {
 375                 IRQ_OFF(host, SD_CONFIG_TH);
 376
 377                 if (host->flags & HOST_F_STOP)
 378                         SEND_STOP(host);
 379
 380                 tasklet_schedule(&host->data_task);
 381         }
 382 }
 383
 384 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 385 {
 386
 387         struct mmc_data *data = 0;
 388         int sg_len = 0, max = 0, count = 0;
 389         unsigned char *sg_ptr = 0;
 390         u32 status = 0;
 391         struct scatterlist *sg;
 392
 393         data = host->mrq->data;
 394
 395         if (!(host->flags & HOST_F_RECV))
 396                 return;
 397
 398         max = host->pio.len;
 399
 400         if (host->pio.index < host->dma.len) {
 401                 sg = &data->sg[host->pio.index];
 402                 sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
 403
 404                 /* This is the space left inside the buffer */
 405                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 406
 407                 /* Check to if we need less then the size of the sg_buffer */
 408                 if (sg_len < max) max = sg_len;
 409         }
 410
 411         if (max > AU1XMMC_MAX_TRANSFER)
 412                 max = AU1XMMC_MAX_TRANSFER;
 413
 414         for(count = 0; count < max; count++ ) {
 415                 u32 val;
 416                 status = au_readl(HOST_STATUS(host));
 417
 418                 if (!(status & SD_STATUS_NE))
 419                         break;
 420
 421                 if (status & SD_STATUS_RC) {
 422                         DBG("RX CRC Error [%d + %d].\n", host->id,
 423                                         host->pio.len, count);
 424                         break;
 425                 }
 426
 427                 if (status & SD_STATUS_RO) {
 428                         DBG("RX Overrun [%d + %d]\n", host->id,
 429                                         host->pio.len, count);
 430                         break;
 431                 }
 432                 else if (status & SD_STATUS_RU) {
 433                         DBG("RX Underrun [%d + %d]\n", host->id,
 434                                         host->pio.len,  count);
 435                         break;
 436                 }
 437
 438                 val = au_readl(HOST_RXPORT(host));
 439
 440                 if (sg_ptr)
 441                         *sg_ptr++ = (unsigned char) (val & 0xFF);
 442         }
 443
 444         host->pio.len -= count;
 445         host->pio.offset += count;
 446
 447         if (sg_len && count == sg_len) {
 448                 host->pio.index++;
 449                 host->pio.offset = 0;
 450         }
 451
 452         if (host->pio.len == 0) {
 453                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
 454                 IRQ_OFF(host, SD_CONFIG_NE);
 455
 456                 if (host->flags & HOST_F_STOP)
 457                         SEND_STOP(host);
 458
 459                 tasklet_schedule(&host->data_task);
 460         }
 461 }
 462
 463 /* static void au1xmmc_cmd_complete
 464    This is called when a command has been completed - grab the response
 465    and check for errors.  Then start the data transfer if it is indicated.
 466 */
 467
 468 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 469 {
 470
 471         struct mmc_request *mrq = host->mrq;
 472         struct mmc_command *cmd;
 473         int trans;
 474
 475         if (!host->mrq)
 476                 return;
 477
 478         cmd = mrq->cmd;
 479         cmd->error = MMC_ERR_NONE;
 480
 481         if (cmd->flags & MMC_RSP_PRESENT) {
 482                 if (cmd->flags & MMC_RSP_136) {
 483                         u32 r[4];
 484                         int i;
 485
 486                         r[0] = au_readl(host->iobase + SD_RESP3);
 487                         r[1] = au_readl(host->iobase + SD_RESP2);
 488                         r[2] = au_readl(host->iobase + SD_RESP1);
 489                         r[3] = au_readl(host->iobase + SD_RESP0);
 490
 491                         /* The CRC is omitted from the response, so really
 492                          * we only got 120 bytes, but the engine expects
 493                          * 128 bits, so we have to shift things up
 494                          */
 495
 496                         for(i = 0; i < 4; i++) {
 497                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 498                                 if (i != 3)
 499                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 500                         }
 501                 } else {
 502                         /* Techincally, we should be getting all 48 bits of
 503                          * the response (SD_RESP1 + SD_RESP2), but because
 504                          * our response omits the CRC, our data ends up
 505                          * being shifted 8 bits to the right.  In this case,
 506                          * that means that the OSR data starts at bit 31,
 507                          * so we can just read RESP0 and return that
 508                          */
 509                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 510                 }
 511         }
 512
 513         /* Figure out errors */
 514
 515         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 516                 cmd->error = MMC_ERR_BADCRC;
 517
 518         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 519
 520         if (!trans || cmd->error != MMC_ERR_NONE) {
 521
 522                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
 523                 tasklet_schedule(&host->finish_task);
 524                 return;
 525         }
 526
 527         host->status = HOST_S_DATA;
 528
 529         if (host->flags & HOST_F_DMA) {
 530                 u32 channel = DMA_CHANNEL(host);
 531
 532                 /* Start the DMA as soon as the buffer gets something in it */
 533
 534                 if (host->flags & HOST_F_RECV) {
 535                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 536
 537                         while((status & mask) != mask)
 538                                 status = au_readl(HOST_STATUS(host));
 539                 }
 540
 541                 au1xxx_dbdma_start(channel);
 542         }
 543 }
 544
 545 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 546 {
 547
 548         unsigned int pbus = get_au1x00_speed();
 549         unsigned int divisor;
 550         u32 config;
 551
 552         /* From databook:
 553            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 554         */
 555
 556         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 557         pbus /= 2;
 558
 559         divisor = ((pbus / rate) / 2) - 1;
 560
 561         config = au_readl(HOST_CONFIG(host));
 562
 563         config &= ~(SD_CONFIG_DIV);
 564         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 565
 566         au_writel(config, HOST_CONFIG(host));
 567         au_sync();
 568 }
 569
 570 static int
 571 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
 572 {
 573
 574         int datalen = data->blocks * data->blksz;
 575
 576         if (dma != 0)
 577                 host->flags |= HOST_F_DMA;
 578
 579         if (data->flags & MMC_DATA_READ)
 580                 host->flags |= HOST_F_RECV;
 581         else
 582                 host->flags |= HOST_F_XMIT;
 583
 584         if (host->mrq->stop)
 585                 host->flags |= HOST_F_STOP;
 586
 587         host->dma.dir = DMA_BIDIRECTIONAL;
 588
 589         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 590                                    data->sg_len, host->dma.dir);
 591
 592         if (host->dma.len == 0)
 593                 return MMC_ERR_TIMEOUT;
 594
 595         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 596
 597         if (host->flags & HOST_F_DMA) {
 598                 int i;
 599                 u32 channel = DMA_CHANNEL(host);
 600
 601                 au1xxx_dbdma_stop(channel);
 602
 603                 for(i = 0; i < host->dma.len; i++) {
 604                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 605                         struct scatterlist *sg = &data->sg[i];
 606                         int sg_len = sg->length;
 607
 608                         int len = (datalen > sg_len) ? sg_len : datalen;
 609
 610                         if (i == host->dma.len - 1)
 611                                 flags = DDMA_FLAGS_IE;
 612
 613                         if (host->flags & HOST_F_XMIT){
 614                                 ret = au1xxx_dbdma_put_source_flags(channel,
 615                                         (void *) (page_address(sg->page) +
 616                                                   sg->offset),
 617                                         len, flags);
 618                         }
 619                         else {
 620                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 621                                         (void *) (page_address(sg->page) +
 622                                                   sg->offset),
 623                                         len, flags);
 624                         }
 625
 626                         if (!ret)
 627                                 goto dataerr;
 628
 629                         datalen -= len;
 630                 }
 631         }
 632         else {
 633                 host->pio.index = 0;
 634                 host->pio.offset = 0;
 635                 host->pio.len = datalen;
 636
 637                 if (host->flags & HOST_F_XMIT)
 638                         IRQ_ON(host, SD_CONFIG_TH);
 639                 else
 640                         IRQ_ON(host, SD_CONFIG_NE);
 641                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
 642         }
 643
 644         return MMC_ERR_NONE;
 645
 646  dataerr:
 647         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
 648         return MMC_ERR_TIMEOUT;
 649 }
 650
 651 /* static void au1xmmc_request
 652    This actually starts a command or data transaction
 653 */
 654
 655 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 656 {
 657
 658         struct au1xmmc_host *host = mmc_priv(mmc);
 659         unsigned int flags = 0;
 660         int ret = MMC_ERR_NONE;
 661
 662         WARN_ON(irqs_disabled());
 663         WARN_ON(host->status != HOST_S_IDLE);
 664
 665         host->mrq = mrq;
 666         host->status = HOST_S_CMD;
 667
 668         bcsr->disk_leds &= ~(1 << 8);
 669
 670         if (mrq->data) {
 671                 FLUSH_FIFO(host);
 672                 flags = mrq->data->flags;
 673                 ret = au1xmmc_prepare_data(host, mrq->data);
 674         }
 675
 676         if (ret == MMC_ERR_NONE)
 677                 ret = au1xmmc_send_command(host, 0, mrq->cmd, flags);
 678
 679         if (ret != MMC_ERR_NONE) {
 680                 mrq->cmd->error = ret;
 681                 au1xmmc_finish_request(host);
 682         }
 683 }
 684
 685 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 686 {
 687
 688         /* Apply the clock */
 689         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 690         au_sync_delay(1);
 691
 692         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 693         au_sync_delay(5);
 694
 695         au_writel(~0, HOST_STATUS(host));
 696         au_sync();
 697
 698         au_writel(0, HOST_BLKSIZE(host));
 699         au_writel(0x001fffff, HOST_TIMEOUT(host));
 700         au_sync();
 701
 702         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 703         au_sync();
 704
 705         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 706         au_sync_delay(1);
 707
 708         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 709         au_sync();
 710
 711         /* Configure interrupts */
 712         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 713         au_sync();
 714 }
 715
 716
 717 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
 718 {
 719         struct au1xmmc_host *host = mmc_priv(mmc);
 720
 721         if (ios->power_mode == MMC_POWER_OFF)
 722                 au1xmmc_set_power(host, 0);
 723         else if (ios->power_mode == MMC_POWER_ON) {
 724                 au1xmmc_set_power(host, 1);
 725         }
 726
 727         if (ios->clock && ios->clock != host->clock) {
 728                 au1xmmc_set_clock(host, ios->clock);
 729                 host->clock = ios->clock;
 730         }
 731 }
 732
 733 static void au1xmmc_dma_callback(int irq, void *dev_id)
 734 {
 735         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
 736
 737         /* Avoid spurious interrupts */
 738
 739         if (!host->mrq)
 740                 return;
 741
 742         if (host->flags & HOST_F_STOP)
 743                 SEND_STOP(host);
 744
 745         tasklet_schedule(&host->data_task);
 746 }
 747
 748 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 749 #define STATUS_DATA_IN  (SD_STATUS_NE)
 750 #define STATUS_DATA_OUT (SD_STATUS_TH)
 751
 752 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 753 {
 754
 755         u32 status;
 756         int i, ret = 0;
 757
 758         disable_irq(AU1100_SD_IRQ);
 759
 760         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 761                 struct au1xmmc_host * host = au1xmmc_hosts[i];
 762                 u32 handled = 1;
 763
 764                 status = au_readl(HOST_STATUS(host));
 765
 766                 if (host->mrq && (status & STATUS_TIMEOUT)) {
 767                         if (status & SD_STATUS_RAT)
 768                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 769
 770                         else if (status & SD_STATUS_DT)
 771                                 host->mrq->data->error = MMC_ERR_TIMEOUT;
 772
 773                         /* In PIO mode, interrupts might still be enabled */
 774                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 775
 776                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
 777                         tasklet_schedule(&host->finish_task);
 778                 }
 779 #if 0
 780                 else if (status & SD_STATUS_DD) {
 781
 782                         /* Sometimes we get a DD before a NE in PIO mode */
 783
 784                         if (!(host->flags & HOST_F_DMA) &&
 785                                         (status & SD_STATUS_NE))
 786                                 au1xmmc_receive_pio(host);
 787                         else {
 788                                 au1xmmc_data_complete(host, status);
 789                                 //tasklet_schedule(&host->data_task);
 790                         }
 791                 }
 792 #endif
 793                 else if (status & (SD_STATUS_CR)) {
 794                         if (host->status == HOST_S_CMD)
 795                                 au1xmmc_cmd_complete(host,status);
 796                 }
 797                 else if (!(host->flags & HOST_F_DMA)) {
 798                         if ((host->flags & HOST_F_XMIT) &&
 799                             (status & STATUS_DATA_OUT))
 800                                 au1xmmc_send_pio(host);
 801                         else if ((host->flags & HOST_F_RECV) &&
 802                             (status & STATUS_DATA_IN))
 803                                 au1xmmc_receive_pio(host);
 804                 }
 805                 else if (status & 0x203FBC70) {
 806                         DBG("Unhandled status %8.8x\n", host->id, status);
 807                         handled = 0;
 808                 }
 809
 810                 au_writel(status, HOST_STATUS(host));
 811                 au_sync();
 812
 813                 ret |= handled;
 814         }
 815
 816         enable_irq(AU1100_SD_IRQ);
 817         return ret;
 818 }
 819
 820 static void au1xmmc_poll_event(unsigned long arg)
 821 {
 822         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
 823
 824         int card = au1xmmc_card_inserted(host);
 825         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
 826
 827         if (card != controller) {
 828                 host->flags &= ~HOST_F_ACTIVE;
 829                 if (card) host->flags |= HOST_F_ACTIVE;
 830                 mmc_detect_change(host->mmc, 0);
 831         }
 832
 833         if (host->mrq != NULL) {
 834                 u32 status = au_readl(HOST_STATUS(host));
 835                 DBG("PENDING - %8.8x\n", host->id, status);
 836         }
 837
 838         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
 839 }
 840
 841 static dbdev_tab_t au1xmmc_mem_dbdev =
 842 {
 843         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
 844 };
 845
 846 static void au1xmmc_init_dma(struct au1xmmc_host *host)
 847 {
 848
 849         u32 rxchan, txchan;
 850
 851         int txid = au1xmmc_card_table[host->id].tx_devid;
 852         int rxid = au1xmmc_card_table[host->id].rx_devid;
 853
 854         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
 855            of 8 bits.  And since devices are shared, we need to create
 856            our own to avoid freaking out other devices
 857         */
 858
 859         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
 860
 861         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
 862                                          au1xmmc_dma_callback, (void *) host);
 863
 864         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
 865                                          au1xmmc_dma_callback, (void *) host);
 866
 867         au1xxx_dbdma_set_devwidth(txchan, 8);
 868         au1xxx_dbdma_set_devwidth(rxchan, 8);
 869
 870         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
 871         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
 872
 873         host->tx_chan = txchan;
 874         host->rx_chan = rxchan;
 875 }
 876
 877 static const struct mmc_host_ops au1xmmc_ops = {
 878         .request        = au1xmmc_request,
 879         .set_ios        = au1xmmc_set_ios,
 880         .get_ro         = au1xmmc_card_readonly,
 881 };
 882
 883 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 884 {
 885
 886         int i, ret = 0;
 887
 888         /* THe interrupt is shared among all controllers */
 889         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
 890
 891         if (ret) {
 892                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
 893                                 AU1100_SD_IRQ, ret);
 894                 return -ENXIO;
 895         }
 896
 897         disable_irq(AU1100_SD_IRQ);
 898
 899         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 900                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 901                 struct au1xmmc_host *host = 0;
 902
 903                 if (!mmc) {
 904                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
 905                         au1xmmc_hosts[i] = 0;
 906                         continue;
 907                 }
 908
 909                 mmc->ops = &au1xmmc_ops;
 910
 911                 mmc->f_min =   450000;
 912                 mmc->f_max = 24000000;
 913
 914                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
 915                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
 916
 917                 mmc->max_blk_size = 2048;
 918                 mmc->max_blk_count = 512;
 919
 920                 mmc->ocr_avail = AU1XMMC_OCR;
 921
 922                 host = mmc_priv(mmc);
 923                 host->mmc = mmc;
 924
 925                 host->id = i;
 926                 host->iobase = au1xmmc_card_table[host->id].iobase;
 927                 host->clock = 0;
 928                 host->power_mode = MMC_POWER_OFF;
 929
 930                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
 931                 host->status = HOST_S_IDLE;
 932
 933                 init_timer(&host->timer);
 934
 935                 host->timer.function = au1xmmc_poll_event;
 936                 host->timer.data = (unsigned long) host;
 937                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
 938
 939                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
 940                                 (unsigned long) host);
 941
 942                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
 943                                 (unsigned long) host);
 944
 945                 spin_lock_init(&host->lock);
 946
 947                 if (dma != 0)
 948                         au1xmmc_init_dma(host);
 949
 950                 au1xmmc_reset_controller(host);
 951
 952                 mmc_add_host(mmc);
 953                 au1xmmc_hosts[i] = host;
 954
 955                 add_timer(&host->timer);
 956
 957                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
 958                        host->id, host->iobase, dma ? "dma" : "pio");
 959         }
 960
 961         enable_irq(AU1100_SD_IRQ);
 962
 963         return 0;
 964 }
 965
 966 static int __devexit au1xmmc_remove(struct platform_device *pdev)
 967 {
 968
 969         int i;
 970
 971         disable_irq(AU1100_SD_IRQ);
 972
 973         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 974                 struct au1xmmc_host *host = au1xmmc_hosts[i];
 975                 if (!host) continue;
 976
 977                 tasklet_kill(&host->data_task);
 978                 tasklet_kill(&host->finish_task);
 979
 980                 del_timer_sync(&host->timer);
 981                 au1xmmc_set_power(host, 0);
 982
 983                 mmc_remove_host(host->mmc);
 984
 985                 au1xxx_dbdma_chan_free(host->tx_chan);
 986                 au1xxx_dbdma_chan_free(host->rx_chan);
 987
 988                 au_writel(0x0, HOST_ENABLE(host));
 989                 au_sync();
 990         }
 991
 992         free_irq(AU1100_SD_IRQ, 0);
 993         return 0;
 994 }
 995
 996 static struct platform_driver au1xmmc_driver = {
 997         .probe         = au1xmmc_probe,
 998         .remove        = au1xmmc_remove,
 999         .suspend       = NULL,
1000         .resume        = NULL,
1001         .driver        = {
1002                 .name  = DRIVER_NAME,
1003         },
1004 };
1005
1006 static int __init au1xmmc_init(void)
1007 {
1008         return platform_driver_register(&au1xmmc_driver);
1009 }
1010
1011 static void __exit au1xmmc_exit(void)
1012 {
1013         platform_driver_unregister(&au1xmmc_driver);
1014 }
1015
1016 module_init(au1xmmc_init);
1017 module_exit(au1xmmc_exit);
1018
1019 #ifdef MODULE
1020 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1021 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1022 MODULE_LICENSE("GPL");
1023 #endif
1024