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   1 /* pci_sun4v.c: SUN4V specific PCI controller support.
   2  *
   3  * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/percpu.h>
  13 #include <linux/irq.h>
  14 #include <linux/msi.h>
  15
  16 #include <asm/pbm.h>
  17 #include <asm/iommu.h>
  18 #include <asm/irq.h>
  19 #include <asm/upa.h>
  20 #include <asm/pstate.h>
  21 #include <asm/oplib.h>
  22 #include <asm/hypervisor.h>
  23 #include <asm/prom.h>
  24
  25 #include "pci_impl.h"
  26 #include "iommu_common.h"
  27
  28 #include "pci_sun4v.h"
  29
  30 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
  31
  32 struct pci_iommu_batch {
  33         struct pci_dev  *pdev;          /* Device mapping is for.       */
  34         unsigned long   prot;           /* IOMMU page protections       */
  35         unsigned long   entry;          /* Index into IOTSB.            */
  36         u64             *pglist;        /* List of physical pages       */
  37         unsigned long   npages;         /* Number of pages in list.     */
  38 };
  39
  40 static DEFINE_PER_CPU(struct pci_iommu_batch, pci_iommu_batch);
  41
  42 /* Interrupts must be disabled.  */
  43 static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
  44 {
  45         struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
  46
  47         p->pdev         = pdev;
  48         p->prot         = prot;
  49         p->entry        = entry;
  50         p->npages       = 0;
  51 }
  52
  53 /* Interrupts must be disabled.  */
  54 static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
  55 {
  56         struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
  57         unsigned long devhandle = pbm->devhandle;
  58         unsigned long prot = p->prot;
  59         unsigned long entry = p->entry;
  60         u64 *pglist = p->pglist;
  61         unsigned long npages = p->npages;
  62
  63         while (npages != 0) {
  64                 long num;
  65
  66                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
  67                                           npages, prot, __pa(pglist));
  68                 if (unlikely(num < 0)) {
  69                         if (printk_ratelimit())
  70                                 printk("pci_iommu_batch_flush: IOMMU map of "
  71                                        "[%08lx:%08lx:%lx:%lx:%lx] failed with "
  72                                        "status %ld\n",
  73                                        devhandle, HV_PCI_TSBID(0, entry),
  74                                        npages, prot, __pa(pglist), num);
  75                         return -1;
  76                 }
  77
  78                 entry += num;
  79                 npages -= num;
  80                 pglist += num;
  81         }
  82
  83         p->entry = entry;
  84         p->npages = 0;
  85
  86         return 0;
  87 }
  88
  89 /* Interrupts must be disabled.  */
  90 static inline long pci_iommu_batch_add(u64 phys_page)
  91 {
  92         struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
  93
  94         BUG_ON(p->npages >= PGLIST_NENTS);
  95
  96         p->pglist[p->npages++] = phys_page;
  97         if (p->npages == PGLIST_NENTS)
  98                 return pci_iommu_batch_flush(p);
  99
 100         return 0;
 101 }
 102
 103 /* Interrupts must be disabled.  */
 104 static inline long pci_iommu_batch_end(void)
 105 {
 106         struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
 107
 108         BUG_ON(p->npages >= PGLIST_NENTS);
 109
 110         return pci_iommu_batch_flush(p);
 111 }
 112
 113 static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
 114 {
 115         unsigned long n, i, start, end, limit;
 116         int pass;
 117
 118         limit = arena->limit;
 119         start = arena->hint;
 120         pass = 0;
 121
 122 again:
 123         n = find_next_zero_bit(arena->map, limit, start);
 124         end = n + npages;
 125         if (unlikely(end >= limit)) {
 126                 if (likely(pass < 1)) {
 127                         limit = start;
 128                         start = 0;
 129                         pass++;
 130                         goto again;
 131                 } else {
 132                         /* Scanned the whole thing, give up. */
 133                         return -1;
 134                 }
 135         }
 136
 137         for (i = n; i < end; i++) {
 138                 if (test_bit(i, arena->map)) {
 139                         start = i + 1;
 140                         goto again;
 141                 }
 142         }
 143
 144         for (i = n; i < end; i++)
 145                 __set_bit(i, arena->map);
 146
 147         arena->hint = end;
 148
 149         return n;
 150 }
 151
 152 static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
 153 {
 154         unsigned long i;
 155
 156         for (i = base; i < (base + npages); i++)
 157                 __clear_bit(i, arena->map);
 158 }
 159
 160 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
 161 {
 162         struct pci_iommu *iommu;
 163         unsigned long flags, order, first_page, npages, n;
 164         void *ret;
 165         long entry;
 166
 167         size = IO_PAGE_ALIGN(size);
 168         order = get_order(size);
 169         if (unlikely(order >= MAX_ORDER))
 170                 return NULL;
 171
 172         npages = size >> IO_PAGE_SHIFT;
 173
 174         first_page = __get_free_pages(gfp, order);
 175         if (unlikely(first_page == 0UL))
 176                 return NULL;
 177
 178         memset((char *)first_page, 0, PAGE_SIZE << order);
 179
 180         iommu = pdev->dev.archdata.iommu;
 181
 182         spin_lock_irqsave(&iommu->lock, flags);
 183         entry = pci_arena_alloc(&iommu->arena, npages);
 184         spin_unlock_irqrestore(&iommu->lock, flags);
 185
 186         if (unlikely(entry < 0L))
 187                 goto arena_alloc_fail;
 188
 189         *dma_addrp = (iommu->page_table_map_base +
 190                       (entry << IO_PAGE_SHIFT));
 191         ret = (void *) first_page;
 192         first_page = __pa(first_page);
 193
 194         local_irq_save(flags);
 195
 196         pci_iommu_batch_start(pdev,
 197                               (HV_PCI_MAP_ATTR_READ |
 198                                HV_PCI_MAP_ATTR_WRITE),
 199                               entry);
 200
 201         for (n = 0; n < npages; n++) {
 202                 long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
 203                 if (unlikely(err < 0L))
 204                         goto iommu_map_fail;
 205         }
 206
 207         if (unlikely(pci_iommu_batch_end() < 0L))
 208                 goto iommu_map_fail;
 209
 210         local_irq_restore(flags);
 211
 212         return ret;
 213
 214 iommu_map_fail:
 215         /* Interrupts are disabled.  */
 216         spin_lock(&iommu->lock);
 217         pci_arena_free(&iommu->arena, entry, npages);
 218         spin_unlock_irqrestore(&iommu->lock, flags);
 219
 220 arena_alloc_fail:
 221         free_pages(first_page, order);
 222         return NULL;
 223 }
 224
 225 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
 226 {
 227         struct pci_pbm_info *pbm;
 228         struct pci_iommu *iommu;
 229         unsigned long flags, order, npages, entry;
 230         u32 devhandle;
 231
 232         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 233         iommu = pdev->dev.archdata.iommu;
 234         pbm = pdev->dev.archdata.host_controller;
 235         devhandle = pbm->devhandle;
 236         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 237
 238         spin_lock_irqsave(&iommu->lock, flags);
 239
 240         pci_arena_free(&iommu->arena, entry, npages);
 241
 242         do {
 243                 unsigned long num;
 244
 245                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 246                                             npages);
 247                 entry += num;
 248                 npages -= num;
 249         } while (npages != 0);
 250
 251         spin_unlock_irqrestore(&iommu->lock, flags);
 252
 253         order = get_order(size);
 254         if (order < 10)
 255                 free_pages((unsigned long)cpu, order);
 256 }
 257
 258 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
 259 {
 260         struct pci_iommu *iommu;
 261         unsigned long flags, npages, oaddr;
 262         unsigned long i, base_paddr;
 263         u32 bus_addr, ret;
 264         unsigned long prot;
 265         long entry;
 266
 267         iommu = pdev->dev.archdata.iommu;
 268
 269         if (unlikely(direction == PCI_DMA_NONE))
 270                 goto bad;
 271
 272         oaddr = (unsigned long)ptr;
 273         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 274         npages >>= IO_PAGE_SHIFT;
 275
 276         spin_lock_irqsave(&iommu->lock, flags);
 277         entry = pci_arena_alloc(&iommu->arena, npages);
 278         spin_unlock_irqrestore(&iommu->lock, flags);
 279
 280         if (unlikely(entry < 0L))
 281                 goto bad;
 282
 283         bus_addr = (iommu->page_table_map_base +
 284                     (entry << IO_PAGE_SHIFT));
 285         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 286         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 287         prot = HV_PCI_MAP_ATTR_READ;
 288         if (direction != PCI_DMA_TODEVICE)
 289                 prot |= HV_PCI_MAP_ATTR_WRITE;
 290
 291         local_irq_save(flags);
 292
 293         pci_iommu_batch_start(pdev, prot, entry);
 294
 295         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
 296                 long err = pci_iommu_batch_add(base_paddr);
 297                 if (unlikely(err < 0L))
 298                         goto iommu_map_fail;
 299         }
 300         if (unlikely(pci_iommu_batch_end() < 0L))
 301                 goto iommu_map_fail;
 302
 303         local_irq_restore(flags);
 304
 305         return ret;
 306
 307 bad:
 308         if (printk_ratelimit())
 309                 WARN_ON(1);
 310         return PCI_DMA_ERROR_CODE;
 311
 312 iommu_map_fail:
 313         /* Interrupts are disabled.  */
 314         spin_lock(&iommu->lock);
 315         pci_arena_free(&iommu->arena, entry, npages);
 316         spin_unlock_irqrestore(&iommu->lock, flags);
 317
 318         return PCI_DMA_ERROR_CODE;
 319 }
 320
 321 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 322 {
 323         struct pci_pbm_info *pbm;
 324         struct pci_iommu *iommu;
 325         unsigned long flags, npages;
 326         long entry;
 327         u32 devhandle;
 328
 329         if (unlikely(direction == PCI_DMA_NONE)) {
 330                 if (printk_ratelimit())
 331                         WARN_ON(1);
 332                 return;
 333         }
 334
 335         iommu = pdev->dev.archdata.iommu;
 336         pbm = pdev->dev.archdata.host_controller;
 337         devhandle = pbm->devhandle;
 338
 339         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 340         npages >>= IO_PAGE_SHIFT;
 341         bus_addr &= IO_PAGE_MASK;
 342
 343         spin_lock_irqsave(&iommu->lock, flags);
 344
 345         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
 346         pci_arena_free(&iommu->arena, entry, npages);
 347
 348         do {
 349                 unsigned long num;
 350
 351                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 352                                             npages);
 353                 entry += num;
 354                 npages -= num;
 355         } while (npages != 0);
 356
 357         spin_unlock_irqrestore(&iommu->lock, flags);
 358 }
 359
 360 #define SG_ENT_PHYS_ADDRESS(SG) \
 361         (__pa(page_address((SG)->page)) + (SG)->offset)
 362
 363 static inline long fill_sg(long entry, struct pci_dev *pdev,
 364                            struct scatterlist *sg,
 365                            int nused, int nelems, unsigned long prot)
 366 {
 367         struct scatterlist *dma_sg = sg;
 368         struct scatterlist *sg_end = sg + nelems;
 369         unsigned long flags;
 370         int i;
 371
 372         local_irq_save(flags);
 373
 374         pci_iommu_batch_start(pdev, prot, entry);
 375
 376         for (i = 0; i < nused; i++) {
 377                 unsigned long pteval = ~0UL;
 378                 u32 dma_npages;
 379
 380                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
 381                               dma_sg->dma_length +
 382                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
 383                 do {
 384                         unsigned long offset;
 385                         signed int len;
 386
 387                         /* If we are here, we know we have at least one
 388                          * more page to map.  So walk forward until we
 389                          * hit a page crossing, and begin creating new
 390                          * mappings from that spot.
 391                          */
 392                         for (;;) {
 393                                 unsigned long tmp;
 394
 395                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
 396                                 len = sg->length;
 397                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
 398                                         pteval = tmp & IO_PAGE_MASK;
 399                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
 400                                         break;
 401                                 }
 402                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
 403                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
 404                                         offset = 0UL;
 405                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
 406                                         break;
 407                                 }
 408                                 sg++;
 409                         }
 410
 411                         pteval = (pteval & IOPTE_PAGE);
 412                         while (len > 0) {
 413                                 long err;
 414
 415                                 err = pci_iommu_batch_add(pteval);
 416                                 if (unlikely(err < 0L))
 417                                         goto iommu_map_failed;
 418
 419                                 pteval += IO_PAGE_SIZE;
 420                                 len -= (IO_PAGE_SIZE - offset);
 421                                 offset = 0;
 422                                 dma_npages--;
 423                         }
 424
 425                         pteval = (pteval & IOPTE_PAGE) + len;
 426                         sg++;
 427
 428                         /* Skip over any tail mappings we've fully mapped,
 429                          * adjusting pteval along the way.  Stop when we
 430                          * detect a page crossing event.
 431                          */
 432                         while (sg < sg_end &&
 433                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
 434                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
 435                                ((pteval ^
 436                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
 437                                 pteval += sg->length;
 438                                 sg++;
 439                         }
 440                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
 441                                 pteval = ~0UL;
 442                 } while (dma_npages != 0);
 443                 dma_sg++;
 444         }
 445
 446         if (unlikely(pci_iommu_batch_end() < 0L))
 447                 goto iommu_map_failed;
 448
 449         local_irq_restore(flags);
 450         return 0;
 451
 452 iommu_map_failed:
 453         local_irq_restore(flags);
 454         return -1L;
 455 }
 456
 457 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 458 {
 459         struct pci_iommu *iommu;
 460         unsigned long flags, npages, prot;
 461         u32 dma_base;
 462         struct scatterlist *sgtmp;
 463         long entry, err;
 464         int used;
 465
 466         /* Fast path single entry scatterlists. */
 467         if (nelems == 1) {
 468                 sglist->dma_address =
 469                         pci_4v_map_single(pdev,
 470                                           (page_address(sglist->page) + sglist->offset),
 471                                           sglist->length, direction);
 472                 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
 473                         return 0;
 474                 sglist->dma_length = sglist->length;
 475                 return 1;
 476         }
 477
 478         iommu = pdev->dev.archdata.iommu;
 479
 480         if (unlikely(direction == PCI_DMA_NONE))
 481                 goto bad;
 482
 483         /* Step 1: Prepare scatter list. */
 484         npages = prepare_sg(sglist, nelems);
 485
 486         /* Step 2: Allocate a cluster and context, if necessary. */
 487         spin_lock_irqsave(&iommu->lock, flags);
 488         entry = pci_arena_alloc(&iommu->arena, npages);
 489         spin_unlock_irqrestore(&iommu->lock, flags);
 490
 491         if (unlikely(entry < 0L))
 492                 goto bad;
 493
 494         dma_base = iommu->page_table_map_base +
 495                 (entry << IO_PAGE_SHIFT);
 496
 497         /* Step 3: Normalize DMA addresses. */
 498         used = nelems;
 499
 500         sgtmp = sglist;
 501         while (used && sgtmp->dma_length) {
 502                 sgtmp->dma_address += dma_base;
 503                 sgtmp++;
 504                 used--;
 505         }
 506         used = nelems - used;
 507
 508         /* Step 4: Create the mappings. */
 509         prot = HV_PCI_MAP_ATTR_READ;
 510         if (direction != PCI_DMA_TODEVICE)
 511                 prot |= HV_PCI_MAP_ATTR_WRITE;
 512
 513         err = fill_sg(entry, pdev, sglist, used, nelems, prot);
 514         if (unlikely(err < 0L))
 515                 goto iommu_map_failed;
 516
 517         return used;
 518
 519 bad:
 520         if (printk_ratelimit())
 521                 WARN_ON(1);
 522         return 0;
 523
 524 iommu_map_failed:
 525         spin_lock_irqsave(&iommu->lock, flags);
 526         pci_arena_free(&iommu->arena, entry, npages);
 527         spin_unlock_irqrestore(&iommu->lock, flags);
 528
 529         return 0;
 530 }
 531
 532 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 533 {
 534         struct pci_pbm_info *pbm;
 535         struct pci_iommu *iommu;
 536         unsigned long flags, i, npages;
 537         long entry;
 538         u32 devhandle, bus_addr;
 539
 540         if (unlikely(direction == PCI_DMA_NONE)) {
 541                 if (printk_ratelimit())
 542                         WARN_ON(1);
 543         }
 544
 545         iommu = pdev->dev.archdata.iommu;
 546         pbm = pdev->dev.archdata.host_controller;
 547         devhandle = pbm->devhandle;
 548
 549         bus_addr = sglist->dma_address & IO_PAGE_MASK;
 550
 551         for (i = 1; i < nelems; i++)
 552                 if (sglist[i].dma_length == 0)
 553                         break;
 554         i--;
 555         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
 556                   bus_addr) >> IO_PAGE_SHIFT;
 557
 558         entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 559
 560         spin_lock_irqsave(&iommu->lock, flags);
 561
 562         pci_arena_free(&iommu->arena, entry, npages);
 563
 564         do {
 565                 unsigned long num;
 566
 567                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
 568                                             npages);
 569                 entry += num;
 570                 npages -= num;
 571         } while (npages != 0);
 572
 573         spin_unlock_irqrestore(&iommu->lock, flags);
 574 }
 575
 576 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 577 {
 578         /* Nothing to do... */
 579 }
 580
 581 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 582 {
 583         /* Nothing to do... */
 584 }
 585
 586 struct pci_iommu_ops pci_sun4v_iommu_ops = {
 587         .alloc_consistent               = pci_4v_alloc_consistent,
 588         .free_consistent                = pci_4v_free_consistent,
 589         .map_single                     = pci_4v_map_single,
 590         .unmap_single                   = pci_4v_unmap_single,
 591         .map_sg                         = pci_4v_map_sg,
 592         .unmap_sg                       = pci_4v_unmap_sg,
 593         .dma_sync_single_for_cpu        = pci_4v_dma_sync_single_for_cpu,
 594         .dma_sync_sg_for_cpu            = pci_4v_dma_sync_sg_for_cpu,
 595 };
 596
 597 static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
 598 {
 599         if (bus < pbm->pci_first_busno ||
 600             bus > pbm->pci_last_busno)
 601                 return 1;
 602         return 0;
 603 }
 604
 605 static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 606                                   int where, int size, u32 *value)
 607 {
 608         struct pci_pbm_info *pbm = bus_dev->sysdata;
 609         u32 devhandle = pbm->devhandle;
 610         unsigned int bus = bus_dev->number;
 611         unsigned int device = PCI_SLOT(devfn);
 612         unsigned int func = PCI_FUNC(devfn);
 613         unsigned long ret;
 614
 615         if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
 616                 ret = ~0UL;
 617         } else {
 618                 ret = pci_sun4v_config_get(devhandle,
 619                                 HV_PCI_DEVICE_BUILD(bus, device, func),
 620                                 where, size);
 621 #if 0
 622                 printk("rcfg: [%x:%x:%x:%d]=[%lx]\n",
 623                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
 624                        where, size, ret);
 625 #endif
 626         }
 627         switch (size) {
 628         case 1:
 629                 *value = ret & 0xff;
 630                 break;
 631         case 2:
 632                 *value = ret & 0xffff;
 633                 break;
 634         case 4:
 635                 *value = ret & 0xffffffff;
 636                 break;
 637         };
 638
 639
 640         return PCIBIOS_SUCCESSFUL;
 641 }
 642
 643 static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 644                                    int where, int size, u32 value)
 645 {
 646         struct pci_pbm_info *pbm = bus_dev->sysdata;
 647         u32 devhandle = pbm->devhandle;
 648         unsigned int bus = bus_dev->number;
 649         unsigned int device = PCI_SLOT(devfn);
 650         unsigned int func = PCI_FUNC(devfn);
 651         unsigned long ret;
 652
 653         if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
 654                 /* Do nothing. */
 655         } else {
 656                 ret = pci_sun4v_config_put(devhandle,
 657                                 HV_PCI_DEVICE_BUILD(bus, device, func),
 658                                 where, size, value);
 659 #if 0
 660                 printk("wcfg: [%x:%x:%x:%d] v[%x] == [%lx]\n",
 661                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
 662                        where, size, value, ret);
 663 #endif
 664         }
 665         return PCIBIOS_SUCCESSFUL;
 666 }
 667
 668 static struct pci_ops pci_sun4v_ops = {
 669         .read =         pci_sun4v_read_pci_cfg,
 670         .write =        pci_sun4v_write_pci_cfg,
 671 };
 672
 673
 674 static void pbm_scan_bus(struct pci_controller_info *p,
 675                          struct pci_pbm_info *pbm)
 676 {
 677         pbm->pci_bus = pci_scan_one_pbm(pbm);
 678 }
 679
 680 static void pci_sun4v_scan_bus(struct pci_controller_info *p)
 681 {
 682         struct property *prop;
 683         struct device_node *dp;
 684
 685         if ((dp = p->pbm_A.prom_node) != NULL) {
 686                 prop = of_find_property(dp, "66mhz-capable", NULL);
 687                 p->pbm_A.is_66mhz_capable = (prop != NULL);
 688
 689                 pbm_scan_bus(p, &p->pbm_A);
 690         }
 691         if ((dp = p->pbm_B.prom_node) != NULL) {
 692                 prop = of_find_property(dp, "66mhz-capable", NULL);
 693                 p->pbm_B.is_66mhz_capable = (prop != NULL);
 694
 695                 pbm_scan_bus(p, &p->pbm_B);
 696         }
 697
 698         /* XXX register error interrupt handlers XXX */
 699 }
 700
 701 static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
 702 {
 703         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 704         struct resource *res, *root;
 705         u32 reg;
 706         int where, size, is_64bit;
 707
 708         res = &pdev->resource[resource];
 709         if (resource < 6) {
 710                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
 711         } else if (resource == PCI_ROM_RESOURCE) {
 712                 where = pdev->rom_base_reg;
 713         } else {
 714                 /* Somebody might have asked allocation of a non-standard resource */
 715                 return;
 716         }
 717
 718         /* XXX 64-bit MEM handling is not %100 correct... XXX */
 719         is_64bit = 0;
 720         if (res->flags & IORESOURCE_IO)
 721                 root = &pbm->io_space;
 722         else {
 723                 root = &pbm->mem_space;
 724                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 725                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
 726                         is_64bit = 1;
 727         }
 728
 729         size = res->end - res->start;
 730         pci_read_config_dword(pdev, where, &reg);
 731         reg = ((reg & size) |
 732                (((u32)(res->start - root->start)) & ~size));
 733         if (resource == PCI_ROM_RESOURCE) {
 734                 reg |= PCI_ROM_ADDRESS_ENABLE;
 735                 res->flags |= IORESOURCE_ROM_ENABLE;
 736         }
 737         pci_write_config_dword(pdev, where, reg);
 738
 739         /* This knows that the upper 32-bits of the address
 740          * must be zero.  Our PCI common layer enforces this.
 741          */
 742         if (is_64bit)
 743                 pci_write_config_dword(pdev, where + 4, 0);
 744 }
 745
 746 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
 747                                             struct pci_iommu *iommu)
 748 {
 749         struct pci_iommu_arena *arena = &iommu->arena;
 750         unsigned long i, cnt = 0;
 751         u32 devhandle;
 752
 753         devhandle = pbm->devhandle;
 754         for (i = 0; i < arena->limit; i++) {
 755                 unsigned long ret, io_attrs, ra;
 756
 757                 ret = pci_sun4v_iommu_getmap(devhandle,
 758                                              HV_PCI_TSBID(0, i),
 759                                              &io_attrs, &ra);
 760                 if (ret == HV_EOK) {
 761                         if (page_in_phys_avail(ra)) {
 762                                 pci_sun4v_iommu_demap(devhandle,
 763                                                       HV_PCI_TSBID(0, i), 1);
 764                         } else {
 765                                 cnt++;
 766                                 __set_bit(i, arena->map);
 767                         }
 768                 }
 769         }
 770
 771         return cnt;
 772 }
 773
 774 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 775 {
 776         struct pci_iommu *iommu = pbm->iommu;
 777         struct property *prop;
 778         unsigned long num_tsb_entries, sz;
 779         u32 vdma[2], dma_mask, dma_offset;
 780         int tsbsize;
 781
 782         prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
 783         if (prop) {
 784                 u32 *val = prop->value;
 785
 786                 vdma[0] = val[0];
 787                 vdma[1] = val[1];
 788         } else {
 789                 /* No property, use default values. */
 790                 vdma[0] = 0x80000000;
 791                 vdma[1] = 0x80000000;
 792         }
 793
 794         dma_mask = vdma[0];
 795         switch (vdma[1]) {
 796                 case 0x20000000:
 797                         dma_mask |= 0x1fffffff;
 798                         tsbsize = 64;
 799                         break;
 800
 801                 case 0x40000000:
 802                         dma_mask |= 0x3fffffff;
 803                         tsbsize = 128;
 804                         break;
 805
 806                 case 0x80000000:
 807                         dma_mask |= 0x7fffffff;
 808                         tsbsize = 256;
 809                         break;
 810
 811                 default:
 812                         prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
 813                         prom_halt();
 814         };
 815
 816         tsbsize *= (8 * 1024);
 817
 818         num_tsb_entries = tsbsize / sizeof(iopte_t);
 819
 820         dma_offset = vdma[0];
 821
 822         /* Setup initial software IOMMU state. */
 823         spin_lock_init(&iommu->lock);
 824         iommu->ctx_lowest_free = 1;
 825         iommu->page_table_map_base = dma_offset;
 826         iommu->dma_addr_mask = dma_mask;
 827
 828         /* Allocate and initialize the free area map.  */
 829         sz = num_tsb_entries / 8;
 830         sz = (sz + 7UL) & ~7UL;
 831         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
 832         if (!iommu->arena.map) {
 833                 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
 834                 prom_halt();
 835         }
 836         iommu->arena.limit = num_tsb_entries;
 837
 838         sz = probe_existing_entries(pbm, iommu);
 839         if (sz)
 840                 printk("%s: Imported %lu TSB entries from OBP\n",
 841                        pbm->name, sz);
 842 }
 843
 844 static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm)
 845 {
 846         struct property *prop;
 847         unsigned int *busrange;
 848
 849         prop = of_find_property(pbm->prom_node, "bus-range", NULL);
 850
 851         busrange = prop->value;
 852
 853         pbm->pci_first_busno = busrange[0];
 854         pbm->pci_last_busno = busrange[1];
 855
 856 }
 857
 858 #ifdef CONFIG_PCI_MSI
 859 struct pci_sun4v_msiq_entry {
 860         u64             version_type;
 861 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
 862 #define MSIQ_VERSION_SHIFT              32
 863 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
 864 #define MSIQ_TYPE_SHIFT                 0
 865 #define MSIQ_TYPE_NONE                  0x00
 866 #define MSIQ_TYPE_MSG                   0x01
 867 #define MSIQ_TYPE_MSI32                 0x02
 868 #define MSIQ_TYPE_MSI64                 0x03
 869 #define MSIQ_TYPE_INTX                  0x08
 870 #define MSIQ_TYPE_NONE2                 0xff
 871
 872         u64             intx_sysino;
 873         u64             reserved1;
 874         u64             stick;
 875         u64             req_id;  /* bus/device/func */
 876 #define MSIQ_REQID_BUS_MASK             0xff00UL
 877 #define MSIQ_REQID_BUS_SHIFT            8
 878 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
 879 #define MSIQ_REQID_DEVICE_SHIFT         3
 880 #define MSIQ_REQID_FUNC_MASK            0x0007UL
 881 #define MSIQ_REQID_FUNC_SHIFT           0
 882
 883         u64             msi_address;
 884
 885         /* The format of this value is message type dependant.
 886          * For MSI bits 15:0 are the data from the MSI packet.
 887          * For MSI-X bits 31:0 are the data from the MSI packet.
 888          * For MSG, the message code and message routing code where:
 889          *      bits 39:32 is the bus/device/fn of the msg target-id
 890          *      bits 18:16 is the message routing code
 891          *      bits 7:0 is the message code
 892          * For INTx the low order 2-bits are:
 893          *      00 - INTA
 894          *      01 - INTB
 895          *      10 - INTC
 896          *      11 - INTD
 897          */
 898         u64             msi_data;
 899
 900         u64             reserved2;
 901 };
 902
 903 /* For now this just runs as a pre-handler for the real interrupt handler.
 904  * So we just walk through the queue and ACK all the entries, update the
 905  * head pointer, and return.
 906  *
 907  * In the longer term it would be nice to do something more integrated
 908  * wherein we can pass in some of this MSI info to the drivers.  This
 909  * would be most useful for PCIe fabric error messages, although we could
 910  * invoke those directly from the loop here in order to pass the info around.
 911  */
 912 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
 913 {
 914         struct pci_pbm_info *pbm = data1;
 915         struct pci_sun4v_msiq_entry *base, *ep;
 916         unsigned long msiqid, orig_head, head, type, err;
 917
 918         msiqid = (unsigned long) data2;
 919
 920         head = 0xdeadbeef;
 921         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
 922         if (unlikely(err))
 923                 goto hv_error_get;
 924
 925         if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
 926                 goto bad_offset;
 927
 928         head /= sizeof(struct pci_sun4v_msiq_entry);
 929         orig_head = head;
 930         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
 931                                    (pbm->msiq_ent_count *
 932                                     sizeof(struct pci_sun4v_msiq_entry))));
 933         ep = &base[head];
 934         while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
 935                 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
 936                 if (unlikely(type != MSIQ_TYPE_MSI32 &&
 937                              type != MSIQ_TYPE_MSI64))
 938                         goto bad_type;
 939
 940                 pci_sun4v_msi_setstate(pbm->devhandle,
 941                                        ep->msi_data /* msi_num */,
 942                                        HV_MSISTATE_IDLE);
 943
 944                 /* Clear the entry.  */
 945                 ep->version_type &= ~MSIQ_TYPE_MASK;
 946
 947                 /* Go to next entry in ring.  */
 948                 head++;
 949                 if (head >= pbm->msiq_ent_count)
 950                         head = 0;
 951                 ep = &base[head];
 952         }
 953
 954         if (likely(head != orig_head)) {
 955                 /* ACK entries by updating head pointer.  */
 956                 head *= sizeof(struct pci_sun4v_msiq_entry);
 957                 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
 958                 if (unlikely(err))
 959                         goto hv_error_set;
 960         }
 961         return;
 962
 963 hv_error_set:
 964         printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
 965         goto hv_error_cont;
 966
 967 hv_error_get:
 968         printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
 969
 970 hv_error_cont:
 971         printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
 972                pbm->devhandle, msiqid, head);
 973         return;
 974
 975 bad_offset:
 976         printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
 977                head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
 978         return;
 979
 980 bad_type:
 981         printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
 982         return;
 983 }
 984
 985 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
 986 {
 987         unsigned long size, bits_per_ulong;
 988
 989         bits_per_ulong = sizeof(unsigned long) * 8;
 990         size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
 991         size /= 8;
 992         BUG_ON(size % sizeof(unsigned long));
 993
 994         pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
 995         if (!pbm->msi_bitmap)
 996                 return -ENOMEM;
 997
 998         return 0;
 999 }
1000
1001 static void msi_bitmap_free(struct pci_pbm_info *pbm)
1002 {
1003         kfree(pbm->msi_bitmap);
1004         pbm->msi_bitmap = NULL;
1005 }
1006
1007 static int msi_queue_alloc(struct pci_pbm_info *pbm)
1008 {
1009         unsigned long q_size, alloc_size, pages, order;
1010         int i;
1011
1012         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1013         alloc_size = (pbm->msiq_num * q_size);
1014         order = get_order(alloc_size);
1015         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1016         if (pages == 0UL) {
1017                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1018                        order);
1019                 return -ENOMEM;
1020         }
1021         memset((char *)pages, 0, PAGE_SIZE << order);
1022         pbm->msi_queues = (void *) pages;
1023
1024         for (i = 0; i < pbm->msiq_num; i++) {
1025                 unsigned long err, base = __pa(pages + (i * q_size));
1026                 unsigned long ret1, ret2;
1027
1028                 err = pci_sun4v_msiq_conf(pbm->devhandle,
1029                                           pbm->msiq_first + i,
1030                                           base, pbm->msiq_ent_count);
1031                 if (err) {
1032                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1033                                err);
1034                         goto h_error;
1035                 }
1036
1037                 err = pci_sun4v_msiq_info(pbm->devhandle,
1038                                           pbm->msiq_first + i,
1039                                           &ret1, &ret2);
1040                 if (err) {
1041                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1042                                err);
1043                         goto h_error;
1044                 }
1045                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1046                         printk(KERN_ERR "MSI: Bogus qconf "
1047                                "expected[%lx:%x] got[%lx:%lx]\n",
1048                                base, pbm->msiq_ent_count,
1049                                ret1, ret2);
1050                         goto h_error;
1051                 }
1052         }
1053
1054         return 0;
1055
1056 h_error:
1057         free_pages(pages, order);
1058         return -EINVAL;
1059 }
1060
1061 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1062 {
1063         const u32 *val;
1064         int len;
1065
1066         val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1067         if (!val || len != 4)
1068                 goto no_msi;
1069         pbm->msiq_num = *val;
1070         if (pbm->msiq_num) {
1071                 const struct msiq_prop {
1072                         u32 first_msiq;
1073                         u32 num_msiq;
1074                         u32 first_devino;
1075                 } *mqp;
1076                 const struct msi_range_prop {
1077                         u32 first_msi;
1078                         u32 num_msi;
1079                 } *mrng;
1080                 const struct addr_range_prop {
1081                         u32 msi32_high;
1082                         u32 msi32_low;
1083                         u32 msi32_len;
1084                         u32 msi64_high;
1085                         u32 msi64_low;
1086                         u32 msi64_len;
1087                 } *arng;
1088
1089                 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1090                 if (!val || len != 4)
1091                         goto no_msi;
1092
1093                 pbm->msiq_ent_count = *val;
1094
1095                 mqp = of_get_property(pbm->prom_node,
1096                                       "msi-eq-to-devino", &len);
1097                 if (!mqp || len != sizeof(struct msiq_prop))
1098                         goto no_msi;
1099
1100                 pbm->msiq_first = mqp->first_msiq;
1101                 pbm->msiq_first_devino = mqp->first_devino;
1102
1103                 val = of_get_property(pbm->prom_node, "#msi", &len);
1104                 if (!val || len != 4)
1105                         goto no_msi;
1106                 pbm->msi_num = *val;
1107
1108                 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1109                 if (!mrng || len != sizeof(struct msi_range_prop))
1110                         goto no_msi;
1111                 pbm->msi_first = mrng->first_msi;
1112
1113                 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1114                 if (!val || len != 4)
1115                         goto no_msi;
1116                 pbm->msi_data_mask = *val;
1117
1118                 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1119                 if (!val || len != 4)
1120                         goto no_msi;
1121                 pbm->msix_data_width = *val;
1122
1123                 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1124                                        &len);
1125                 if (!arng || len != sizeof(struct addr_range_prop))
1126                         goto no_msi;
1127                 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1128                         (u64) arng->msi32_low;
1129                 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1130                         (u64) arng->msi64_low;
1131                 pbm->msi32_len = arng->msi32_len;
1132                 pbm->msi64_len = arng->msi64_len;
1133
1134                 if (msi_bitmap_alloc(pbm))
1135                         goto no_msi;
1136
1137                 if (msi_queue_alloc(pbm)) {
1138                         msi_bitmap_free(pbm);
1139                         goto no_msi;
1140                 }
1141
1142                 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1143                        "devino[0x%x]\n",
1144                        pbm->name,
1145                        pbm->msiq_first, pbm->msiq_num,
1146                        pbm->msiq_ent_count,
1147                        pbm->msiq_first_devino);
1148                 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1149                        "width[%u]\n",
1150                        pbm->name,
1151                        pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1152                        pbm->msix_data_width);
1153                 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1154                        "addr64[0x%lx:0x%x]\n",
1155                        pbm->name,
1156                        pbm->msi32_start, pbm->msi32_len,
1157                        pbm->msi64_start, pbm->msi64_len);
1158                 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1159                        pbm->name,
1160                        pbm->msi_queues);
1161         }
1162
1163         return;
1164
1165 no_msi:
1166         pbm->msiq_num = 0;
1167         printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1168 }
1169
1170 static int alloc_msi(struct pci_pbm_info *pbm)
1171 {
1172         int i;
1173
1174         for (i = 0; i < pbm->msi_num; i++) {
1175                 if (!test_and_set_bit(i, pbm->msi_bitmap))
1176                         return i + pbm->msi_first;
1177         }
1178
1179         return -ENOENT;
1180 }
1181
1182 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
1183 {
1184         msi_num -= pbm->msi_first;
1185         clear_bit(msi_num, pbm->msi_bitmap);
1186 }
1187
1188 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
1189                                    struct pci_dev *pdev,
1190                                    struct msi_desc *entry)
1191 {
1192         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1193         unsigned long devino, msiqid;
1194         struct msi_msg msg;
1195         int msi_num, err;
1196
1197         *virt_irq_p = 0;
1198
1199         msi_num = alloc_msi(pbm);
1200         if (msi_num < 0)
1201                 return msi_num;
1202
1203         devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
1204                                  pbm->msiq_first_devino,
1205                                  (pbm->msiq_first_devino +
1206                                   pbm->msiq_num));
1207         err = -ENOMEM;
1208         if (!devino)
1209                 goto out_err;
1210
1211         set_irq_msi(*virt_irq_p, entry);
1212
1213         msiqid = ((devino - pbm->msiq_first_devino) +
1214                   pbm->msiq_first);
1215
1216         err = -EINVAL;
1217         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1218         if (err)
1219                 goto out_err;
1220
1221         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1222                 goto out_err;
1223
1224         if (pci_sun4v_msi_setmsiq(pbm->devhandle,
1225                                   msi_num, msiqid,
1226                                   (entry->msi_attrib.is_64 ?
1227                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1228                 goto out_err;
1229
1230         if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
1231                 goto out_err;
1232
1233         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
1234                 goto out_err;
1235
1236         pdev->dev.archdata.msi_num = msi_num;
1237
1238         if (entry->msi_attrib.is_64) {
1239                 msg.address_hi = pbm->msi64_start >> 32;
1240                 msg.address_lo = pbm->msi64_start & 0xffffffff;
1241         } else {
1242                 msg.address_hi = 0;
1243                 msg.address_lo = pbm->msi32_start;
1244         }
1245         msg.data = msi_num;
1246         write_msi_msg(*virt_irq_p, &msg);
1247
1248         irq_install_pre_handler(*virt_irq_p,
1249                                 pci_sun4v_msi_prehandler,
1250                                 pbm, (void *) msiqid);
1251
1252         return 0;
1253
1254 out_err:
1255         free_msi(pbm, msi_num);
1256         sun4v_destroy_msi(*virt_irq_p);
1257         *virt_irq_p = 0;
1258         return err;
1259
1260 }
1261
1262 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
1263                                        struct pci_dev *pdev)
1264 {
1265         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1266         unsigned long msiqid, err;
1267         unsigned int msi_num;
1268
1269         msi_num = pdev->dev.archdata.msi_num;
1270         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
1271         if (err) {
1272                 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
1273                        pbm->name, err);
1274                 return;
1275         }
1276
1277         pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1278         pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1279
1280         free_msi(pbm, msi_num);
1281
1282         /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1283          * allocation.
1284          */
1285         sun4v_destroy_msi(virt_irq);
1286 }
1287 #else /* CONFIG_PCI_MSI */
1288 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1289 {
1290 }
1291 #endif /* !(CONFIG_PCI_MSI) */
1292
1293 static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1294 {
1295         struct pci_pbm_info *pbm;
1296
1297         if (devhandle & 0x40)
1298                 pbm = &p->pbm_B;
1299         else
1300                 pbm = &p->pbm_A;
1301
1302         pbm->parent = p;
1303         pbm->prom_node = dp;
1304         pbm->pci_first_slot = 1;
1305
1306         pbm->devhandle = devhandle;
1307
1308         pbm->name = dp->full_name;
1309
1310         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1311
1312         pci_determine_mem_io_space(pbm);
1313
1314         pci_sun4v_get_bus_range(pbm);
1315         pci_sun4v_iommu_init(pbm);
1316         pci_sun4v_msi_init(pbm);
1317 }
1318
1319 void sun4v_pci_init(struct device_node *dp, char *model_name)
1320 {
1321         struct pci_controller_info *p;
1322         struct pci_iommu *iommu;
1323         struct property *prop;
1324         struct linux_prom64_registers *regs;
1325         u32 devhandle;
1326         int i;
1327
1328         prop = of_find_property(dp, "reg", NULL);
1329         regs = prop->value;
1330
1331         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1332
1333         for (p = pci_controller_root; p; p = p->next) {
1334                 struct pci_pbm_info *pbm;
1335
1336                 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
1337                         continue;
1338
1339                 pbm = (p->pbm_A.prom_node ?
1340                        &p->pbm_A :
1341                        &p->pbm_B);
1342
1343                 if (pbm->devhandle == (devhandle ^ 0x40)) {
1344                         pci_sun4v_pbm_init(p, dp, devhandle);
1345                         return;
1346                 }
1347         }
1348
1349         for_each_possible_cpu(i) {
1350                 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1351
1352                 if (!page)
1353                         goto fatal_memory_error;
1354
1355                 per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
1356         }
1357
1358         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1359         if (!p)
1360                 goto fatal_memory_error;
1361
1362         iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1363         if (!iommu)
1364                 goto fatal_memory_error;
1365
1366         p->pbm_A.iommu = iommu;
1367
1368         iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1369         if (!iommu)
1370                 goto fatal_memory_error;
1371
1372         p->pbm_B.iommu = iommu;
1373
1374         p->next = pci_controller_root;
1375         pci_controller_root = p;
1376
1377         p->index = pci_num_controllers++;
1378         p->pbms_same_domain = 0;
1379
1380         p->scan_bus = pci_sun4v_scan_bus;
1381         p->base_address_update = pci_sun4v_base_address_update;
1382 #ifdef CONFIG_PCI_MSI
1383         p->setup_msi_irq = pci_sun4v_setup_msi_irq;
1384         p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1385 #endif
1386         p->pci_ops = &pci_sun4v_ops;
1387
1388         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1389          * for memory space.
1390          */
1391         pci_memspace_mask = 0x7fffffffUL;
1392
1393         pci_sun4v_pbm_init(p, dp, devhandle);
1394         return;
1395
1396 fatal_memory_error:
1397         prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1398         prom_halt();
1399 }