2 * Interrupt handling for IPR-based IRQ.
4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
5 * Copyright (C) 2000 Kazumoto Kojima
6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
7 * Copyright (C) 2006 Paul Mundt
10 * On-chip supporting modules (TMU, RTC, etc.).
11 * On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
12 * Hitachi SolutionEngine external I/O:
13 * MS7709SE01, MS7709ASE01, and MS7750SE01
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <asm/system.h>
24 #include <asm/machvec.h>
27 unsigned int addr; /* Address of Interrupt Priority Register */
28 int shift; /* Shifts of the 16-bit data */
29 int priority; /* The priority */
32 static void disable_ipr_irq(unsigned int irq)
34 struct ipr_data *p = get_irq_chip_data(irq);
35 /* Set the priority in IPR to 0 */
36 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
39 static void enable_ipr_irq(unsigned int irq)
41 struct ipr_data *p = get_irq_chip_data(irq);
42 /* Set priority in IPR back to original value */
43 ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
46 static struct irq_chip ipr_irq_chip = {
48 .mask = disable_ipr_irq,
49 .unmask = enable_ipr_irq,
50 .mask_ack = disable_ipr_irq,
53 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
55 struct ipr_data ipr_data;
57 disable_irq_nosync(irq);
60 ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
61 ipr_data.priority = priority;
63 set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
64 handle_level_irq, "level");
65 set_irq_chip_data(irq, &ipr_data);
70 /* XXX: This needs to die a horrible death.. */
71 void __init init_IRQ(void)
73 #ifndef CONFIG_CPU_SUBTYPE_SH7780
74 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
75 make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
77 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
81 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
82 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
83 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
87 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
88 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
89 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
90 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
93 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
94 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
95 make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
96 make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
97 make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
101 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
102 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
103 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
104 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
108 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
109 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
110 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
111 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
114 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
115 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
116 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
118 * Initialize the Interrupt Controller (INTC)
119 * registers to their power on values
123 * Enable external irq (INTC IRQ mode).
124 * You should set corresponding bits of PFC to "00"
125 * to enable these interrupts.
127 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
128 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
129 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
130 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
131 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
132 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
136 #ifdef CONFIG_CPU_HAS_PINT_IRQ
140 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
143 /* Perform the machine specific initialisation */
144 if (sh_mv.mv_init_irq != NULL)
147 irq_ctx_init(smp_processor_id());
150 #if !defined(CONFIG_CPU_HAS_PINT_IRQ)
151 int ipr_irq_demux(int irq)
157 EXPORT_SYMBOL(make_ipr_irq);